1 //===- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// AMDGPU target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
19 
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
23 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm/ADT/ArrayRef.h"
26 #include "llvm/Analysis/TargetTransformInfo.h"
27 #include "llvm/CodeGen/BasicTTIImpl.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/SubtargetFeature.h"
30 #include "llvm/Support/MathExtras.h"
31 #include <cassert>
32 
33 namespace llvm {
34 
35 class AMDGPUTargetLowering;
36 class Loop;
37 class ScalarEvolution;
38 class Type;
39 class Value;
40 
41 class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
42   using BaseT = BasicTTIImplBase<AMDGPUTTIImpl>;
43   using TTI = TargetTransformInfo;
44 
45   friend BaseT;
46 
47   Triple TargetTriple;
48 
49   const GCNSubtarget *ST;
50   const TargetLoweringBase *TLI;
51 
52   const TargetSubtargetInfo *getST() const { return ST; }
53   const TargetLoweringBase *getTLI() const { return TLI; }
54 
55 public:
56   explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
57       : BaseT(TM, F.getParent()->getDataLayout()),
58         TargetTriple(TM->getTargetTriple()),
59         ST(static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F))),
60         TLI(ST->getTargetLowering()) {}
61 
62   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
63                                TTI::UnrollingPreferences &UP);
64 };
65 
66 class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
67   using BaseT = BasicTTIImplBase<GCNTTIImpl>;
68   using TTI = TargetTransformInfo;
69 
70   friend BaseT;
71 
72   const GCNSubtarget *ST;
73   const SITargetLowering *TLI;
74   AMDGPUTTIImpl CommonTTI;
75   bool IsGraphicsShader;
76   bool HasFP32Denormals;
77 
78   const FeatureBitset InlineFeatureIgnoreList = {
79     // Codegen control options which don't matter.
80     AMDGPU::FeatureEnableLoadStoreOpt,
81     AMDGPU::FeatureEnableSIScheduler,
82     AMDGPU::FeatureEnableUnsafeDSOffsetFolding,
83     AMDGPU::FeatureFlatForGlobal,
84     AMDGPU::FeaturePromoteAlloca,
85     AMDGPU::FeatureUnalignedBufferAccess,
86     AMDGPU::FeatureUnalignedScratchAccess,
87 
88     AMDGPU::FeatureAutoWaitcntBeforeBarrier,
89 
90     // Property of the kernel/environment which can't actually differ.
91     AMDGPU::FeatureSGPRInitBug,
92     AMDGPU::FeatureXNACK,
93     AMDGPU::FeatureTrapHandler,
94     AMDGPU::FeatureCodeObjectV3,
95 
96     // The default assumption needs to be ecc is enabled, but no directly
97     // exposed operations depend on it, so it can be safely inlined.
98     AMDGPU::FeatureSRAMECC,
99 
100     // Perf-tuning features
101     AMDGPU::FeatureFastFMAF32,
102     AMDGPU::HalfRate64Ops
103   };
104 
105   const GCNSubtarget *getST() const { return ST; }
106   const AMDGPUTargetLowering *getTLI() const { return TLI; }
107 
108   static inline int getFullRateInstrCost() {
109     return TargetTransformInfo::TCC_Basic;
110   }
111 
112   static inline int getHalfRateInstrCost() {
113     return 2 * TargetTransformInfo::TCC_Basic;
114   }
115 
116   // TODO: The size is usually 8 bytes, but takes 4x as many cycles. Maybe
117   // should be 2 or 4.
118   static inline int getQuarterRateInstrCost() {
119     return 3 * TargetTransformInfo::TCC_Basic;
120   }
121 
122    // On some parts, normal fp64 operations are half rate, and others
123    // quarter. This also applies to some integer operations.
124   inline int get64BitInstrCost() const {
125     return ST->hasHalfRate64Ops() ?
126       getHalfRateInstrCost() : getQuarterRateInstrCost();
127   }
128 
129 public:
130   explicit GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
131     : BaseT(TM, F.getParent()->getDataLayout()),
132       ST(static_cast<const GCNSubtarget*>(TM->getSubtargetImpl(F))),
133       TLI(ST->getTargetLowering()),
134       CommonTTI(TM, F),
135       IsGraphicsShader(AMDGPU::isShader(F.getCallingConv())),
136       HasFP32Denormals(ST->hasFP32Denormals(F)) { }
137 
138   bool hasBranchDivergence() { return true; }
139   bool useGPUDivergenceAnalysis() const;
140 
141   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
142                                TTI::UnrollingPreferences &UP);
143 
144   TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {
145     assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
146     return TTI::PSK_FastHardware;
147   }
148 
149   unsigned getHardwareNumberOfRegisters(bool Vector) const;
150   unsigned getNumberOfRegisters(bool Vector) const;
151   unsigned getRegisterBitWidth(bool Vector) const;
152   unsigned getMinVectorRegisterBitWidth() const;
153   unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
154                                unsigned ChainSizeInBytes,
155                                VectorType *VecTy) const;
156   unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
157                                 unsigned ChainSizeInBytes,
158                                 VectorType *VecTy) const;
159   unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
160 
161   bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes,
162                                   unsigned Alignment,
163                                   unsigned AddrSpace) const;
164   bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
165                                    unsigned Alignment,
166                                    unsigned AddrSpace) const;
167   bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
168                                     unsigned Alignment,
169                                     unsigned AddrSpace) const;
170 
171   unsigned getMaxInterleaveFactor(unsigned VF);
172 
173   bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const;
174 
175   int getArithmeticInstrCost(
176       unsigned Opcode, Type *Ty,
177       TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
178       TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
179       TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
180       TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
181       ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
182       const Instruction *CxtI = nullptr);
183 
184   unsigned getCFInstrCost(unsigned Opcode);
185 
186   bool isInlineAsmSourceOfDivergence(const CallInst *CI,
187                                      ArrayRef<unsigned> Indices = {}) const;
188 
189   int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index);
190   bool isSourceOfDivergence(const Value *V) const;
191   bool isAlwaysUniform(const Value *V) const;
192 
193   unsigned getFlatAddressSpace() const {
194     // Don't bother running InferAddressSpaces pass on graphics shaders which
195     // don't use flat addressing.
196     if (IsGraphicsShader)
197       return -1;
198     return AMDGPUAS::FLAT_ADDRESS;
199   }
200 
201   bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
202                                   Intrinsic::ID IID) const;
203   bool rewriteIntrinsicWithAddressSpace(IntrinsicInst *II,
204                                         Value *OldV, Value *NewV) const;
205 
206   unsigned getVectorSplitCost() { return 0; }
207 
208   unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
209                           Type *SubTp);
210 
211   bool areInlineCompatible(const Function *Caller,
212                            const Function *Callee) const;
213 
214   unsigned getInliningThresholdMultiplier() { return 11; }
215 
216   int getInlinerVectorBonusPercent() { return 0; }
217 
218   int getArithmeticReductionCost(unsigned Opcode,
219                                  Type *Ty,
220                                  bool IsPairwise);
221   template <typename T>
222   int getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
223                             ArrayRef<T *> Args, FastMathFlags FMF,
224                             unsigned VF);
225   int getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
226                             ArrayRef<Type *> Tys, FastMathFlags FMF,
227                             unsigned ScalarizationCostPassed = UINT_MAX);
228   int getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
229                             ArrayRef<Value *> Args, FastMathFlags FMF,
230                             unsigned VF = 1);
231   int getMinMaxReductionCost(Type *Ty, Type *CondTy,
232                              bool IsPairwiseForm,
233                              bool IsUnsigned);
234   unsigned getUserCost(const User *U, ArrayRef<const Value *> Operands);
235 };
236 
237 class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
238   using BaseT = BasicTTIImplBase<R600TTIImpl>;
239   using TTI = TargetTransformInfo;
240 
241   friend BaseT;
242 
243   const R600Subtarget *ST;
244   const AMDGPUTargetLowering *TLI;
245   AMDGPUTTIImpl CommonTTI;
246 
247 public:
248   explicit R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
249     : BaseT(TM, F.getParent()->getDataLayout()),
250       ST(static_cast<const R600Subtarget*>(TM->getSubtargetImpl(F))),
251       TLI(ST->getTargetLowering()),
252       CommonTTI(TM, F)	{}
253 
254   const R600Subtarget *getST() const { return ST; }
255   const AMDGPUTargetLowering *getTLI() const { return TLI; }
256 
257   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
258                                TTI::UnrollingPreferences &UP);
259   unsigned getHardwareNumberOfRegisters(bool Vec) const;
260   unsigned getNumberOfRegisters(bool Vec) const;
261   unsigned getRegisterBitWidth(bool Vector) const;
262   unsigned getMinVectorRegisterBitWidth() const;
263   unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
264   bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, unsigned Alignment,
265                                   unsigned AddrSpace) const;
266   bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
267 		                   unsigned Alignment,
268                                    unsigned AddrSpace) const;
269   bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
270                                     unsigned Alignment,
271                                     unsigned AddrSpace) const;
272   unsigned getMaxInterleaveFactor(unsigned VF);
273   unsigned getCFInstrCost(unsigned Opcode);
274   int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index);
275 };
276 
277 } // end namespace llvm
278 
279 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
280