1 //===-- AMDGPUTargetTransformInfo.cpp - AMDGPU specific TTI pass ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // \file
11 // This file implements a TargetTransformInfo analysis pass specific to the
12 // AMDGPU target machine. It uses the target's detailed information to provide
13 // more precise answers to certain TTI queries, while letting the target
14 // independent and default TTI implementations handle the rest.
15 //
16 //===----------------------------------------------------------------------===//
17 
18 #include "AMDGPUTargetTransformInfo.h"
19 #include "llvm/Analysis/LoopInfo.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Analysis/ValueTracking.h"
22 #include "llvm/CodeGen/BasicTTIImpl.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/IR/Intrinsics.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Target/CostTable.h"
27 #include "llvm/Target/TargetLowering.h"
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "AMDGPUtti"
31 
32 static cl::opt<unsigned> UnrollThresholdPrivate(
33   "amdgpu-unroll-threshold-private",
34   cl::desc("Unroll threshold for AMDGPU if private memory used in a loop"),
35   cl::init(2000), cl::Hidden);
36 
37 void AMDGPUTTIImpl::getUnrollingPreferences(Loop *L,
38                                             TTI::UnrollingPreferences &UP) {
39   UP.Threshold = 300; // Twice the default.
40   UP.MaxCount = UINT_MAX;
41   UP.Partial = true;
42 
43   // TODO: Do we want runtime unrolling?
44 
45   // Maximum alloca size than can fit registers. Reserve 16 registers.
46   const unsigned MaxAlloca = (256 - 16) * 4;
47   for (const BasicBlock *BB : L->getBlocks()) {
48     const DataLayout &DL = BB->getModule()->getDataLayout();
49     for (const Instruction &I : *BB) {
50       const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(&I);
51       if (!GEP || GEP->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
52         continue;
53 
54       const Value *Ptr = GEP->getPointerOperand();
55       const AllocaInst *Alloca =
56           dyn_cast<AllocaInst>(GetUnderlyingObject(Ptr, DL));
57       if (Alloca && Alloca->isStaticAlloca()) {
58         Type *Ty = Alloca->getAllocatedType();
59         unsigned AllocaSize = Ty->isSized() ? DL.getTypeAllocSize(Ty) : 0;
60         if (AllocaSize > MaxAlloca)
61           continue;
62 
63         // Check if GEP depends on a value defined by this loop itself.
64         bool HasLoopDef = false;
65         for (const Value *Op : GEP->operands()) {
66           const Instruction *Inst = dyn_cast<Instruction>(Op);
67           if (!Inst || L->isLoopInvariant(Op))
68             continue;
69           if (any_of(L->getSubLoops(), [Inst](const Loop* SubLoop) {
70                return SubLoop->contains(Inst); }))
71             continue;
72           HasLoopDef = true;
73           break;
74         }
75         if (!HasLoopDef)
76           continue;
77 
78         // We want to do whatever we can to limit the number of alloca
79         // instructions that make it through to the code generator.  allocas
80         // require us to use indirect addressing, which is slow and prone to
81         // compiler bugs.  If this loop does an address calculation on an
82         // alloca ptr, then we want to use a higher than normal loop unroll
83         // threshold. This will give SROA a better chance to eliminate these
84         // allocas.
85         //
86         // Don't use the maximum allowed value here as it will make some
87         // programs way too big.
88         UP.Threshold = UnrollThresholdPrivate;
89         return;
90       }
91     }
92   }
93 }
94 
95 unsigned AMDGPUTTIImpl::getNumberOfRegisters(bool Vec) {
96   if (Vec)
97     return 0;
98 
99   // Number of VGPRs on SI.
100   if (ST->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
101     return 256;
102 
103   return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
104 }
105 
106 unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool Vector) {
107   return Vector ? 0 : 32;
108 }
109 
110 unsigned AMDGPUTTIImpl::getLoadStoreVecRegBitWidth(unsigned AddrSpace) const {
111   switch (AddrSpace) {
112   case AMDGPUAS::GLOBAL_ADDRESS:
113   case AMDGPUAS::CONSTANT_ADDRESS:
114   case AMDGPUAS::FLAT_ADDRESS:
115     return 128;
116   case AMDGPUAS::LOCAL_ADDRESS:
117   case AMDGPUAS::REGION_ADDRESS:
118     return 64;
119   case AMDGPUAS::PRIVATE_ADDRESS:
120     return 8 * ST->getMaxPrivateElementSize();
121   default:
122     if (ST->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS &&
123         (AddrSpace == AMDGPUAS::PARAM_D_ADDRESS ||
124          AddrSpace == AMDGPUAS::PARAM_I_ADDRESS ||
125          (AddrSpace >= AMDGPUAS::CONSTANT_BUFFER_0 &&
126           AddrSpace <= AMDGPUAS::CONSTANT_BUFFER_15)))
127       return 128;
128     llvm_unreachable("unhandled address space");
129   }
130 }
131 
132 unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {
133   // Semi-arbitrary large amount.
134   return 64;
135 }
136 
137 int AMDGPUTTIImpl::getArithmeticInstrCost(
138     unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
139     TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
140     TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args ) {
141 
142   EVT OrigTy = TLI->getValueType(DL, Ty);
143   if (!OrigTy.isSimple()) {
144     return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
145                                          Opd1PropInfo, Opd2PropInfo);
146   }
147 
148   // Legalize the type.
149   std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
150   int ISD = TLI->InstructionOpcodeToISD(Opcode);
151 
152   // Because we don't have any legal vector operations, but the legal types, we
153   // need to account for split vectors.
154   unsigned NElts = LT.second.isVector() ?
155     LT.second.getVectorNumElements() : 1;
156 
157   MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy;
158 
159   switch (ISD) {
160   case ISD::SHL:
161   case ISD::SRL:
162   case ISD::SRA: {
163     if (SLT == MVT::i64)
164       return get64BitInstrCost() * LT.first * NElts;
165 
166     // i32
167     return getFullRateInstrCost() * LT.first * NElts;
168   }
169   case ISD::ADD:
170   case ISD::SUB:
171   case ISD::AND:
172   case ISD::OR:
173   case ISD::XOR: {
174     if (SLT == MVT::i64){
175       // and, or and xor are typically split into 2 VALU instructions.
176       return 2 * getFullRateInstrCost() * LT.first * NElts;
177     }
178 
179     return LT.first * NElts * getFullRateInstrCost();
180   }
181   case ISD::MUL: {
182     const int QuarterRateCost = getQuarterRateInstrCost();
183     if (SLT == MVT::i64) {
184       const int FullRateCost = getFullRateInstrCost();
185       return (4 * QuarterRateCost + (2 * 2) * FullRateCost) * LT.first * NElts;
186     }
187 
188     // i32
189     return QuarterRateCost * NElts * LT.first;
190   }
191   case ISD::FADD:
192   case ISD::FSUB:
193   case ISD::FMUL:
194     if (SLT == MVT::f64)
195       return LT.first * NElts * get64BitInstrCost();
196 
197     if (SLT == MVT::f32 || SLT == MVT::f16)
198       return LT.first * NElts * getFullRateInstrCost();
199     break;
200 
201   case ISD::FDIV:
202   case ISD::FREM:
203     // FIXME: frem should be handled separately. The fdiv in it is most of it,
204     // but the current lowering is also not entirely correct.
205     if (SLT == MVT::f64) {
206       int Cost = 4 * get64BitInstrCost() + 7 * getQuarterRateInstrCost();
207 
208       // Add cost of workaround.
209       if (ST->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
210         Cost += 3 * getFullRateInstrCost();
211 
212       return LT.first * Cost * NElts;
213     }
214 
215     // Assuming no fp32 denormals lowering.
216     if (SLT == MVT::f32 || SLT == MVT::f16) {
217       assert(!ST->hasFP32Denormals() && "will change when supported");
218       int Cost = 7 * getFullRateInstrCost() + 1 * getQuarterRateInstrCost();
219       return LT.first * NElts * Cost;
220     }
221 
222     break;
223   default:
224     break;
225   }
226 
227   return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
228                                        Opd1PropInfo, Opd2PropInfo);
229 }
230 
231 unsigned AMDGPUTTIImpl::getCFInstrCost(unsigned Opcode) {
232   // XXX - For some reason this isn't called for switch.
233   switch (Opcode) {
234   case Instruction::Br:
235   case Instruction::Ret:
236     return 10;
237   default:
238     return BaseT::getCFInstrCost(Opcode);
239   }
240 }
241 
242 int AMDGPUTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
243                                       unsigned Index) {
244   switch (Opcode) {
245   case Instruction::ExtractElement:
246   case Instruction::InsertElement:
247     // Extracts are just reads of a subregister, so are free. Inserts are
248     // considered free because we don't want to have any cost for scalarizing
249     // operations, and we don't have to copy into a different register class.
250 
251     // Dynamic indexing isn't free and is best avoided.
252     return Index == ~0u ? 2 : 0;
253   default:
254     return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
255   }
256 }
257 
258 static bool isIntrinsicSourceOfDivergence(const TargetIntrinsicInfo *TII,
259                                           const IntrinsicInst *I) {
260   switch (I->getIntrinsicID()) {
261   default:
262     return false;
263   case Intrinsic::not_intrinsic:
264     // This means we have an intrinsic that isn't defined in
265     // IntrinsicsAMDGPU.td
266     break;
267 
268   case Intrinsic::amdgcn_workitem_id_x:
269   case Intrinsic::amdgcn_workitem_id_y:
270   case Intrinsic::amdgcn_workitem_id_z:
271   case Intrinsic::amdgcn_interp_mov:
272   case Intrinsic::amdgcn_interp_p1:
273   case Intrinsic::amdgcn_interp_p2:
274   case Intrinsic::amdgcn_mbcnt_hi:
275   case Intrinsic::amdgcn_mbcnt_lo:
276   case Intrinsic::r600_read_tidig_x:
277   case Intrinsic::r600_read_tidig_y:
278   case Intrinsic::r600_read_tidig_z:
279   case Intrinsic::amdgcn_atomic_inc:
280   case Intrinsic::amdgcn_atomic_dec:
281   case Intrinsic::amdgcn_image_atomic_swap:
282   case Intrinsic::amdgcn_image_atomic_add:
283   case Intrinsic::amdgcn_image_atomic_sub:
284   case Intrinsic::amdgcn_image_atomic_smin:
285   case Intrinsic::amdgcn_image_atomic_umin:
286   case Intrinsic::amdgcn_image_atomic_smax:
287   case Intrinsic::amdgcn_image_atomic_umax:
288   case Intrinsic::amdgcn_image_atomic_and:
289   case Intrinsic::amdgcn_image_atomic_or:
290   case Intrinsic::amdgcn_image_atomic_xor:
291   case Intrinsic::amdgcn_image_atomic_inc:
292   case Intrinsic::amdgcn_image_atomic_dec:
293   case Intrinsic::amdgcn_image_atomic_cmpswap:
294   case Intrinsic::amdgcn_buffer_atomic_swap:
295   case Intrinsic::amdgcn_buffer_atomic_add:
296   case Intrinsic::amdgcn_buffer_atomic_sub:
297   case Intrinsic::amdgcn_buffer_atomic_smin:
298   case Intrinsic::amdgcn_buffer_atomic_umin:
299   case Intrinsic::amdgcn_buffer_atomic_smax:
300   case Intrinsic::amdgcn_buffer_atomic_umax:
301   case Intrinsic::amdgcn_buffer_atomic_and:
302   case Intrinsic::amdgcn_buffer_atomic_or:
303   case Intrinsic::amdgcn_buffer_atomic_xor:
304   case Intrinsic::amdgcn_buffer_atomic_cmpswap:
305   case Intrinsic::amdgcn_ps_live:
306   case Intrinsic::amdgcn_ds_swizzle:
307     return true;
308   }
309 
310   StringRef Name = I->getCalledFunction()->getName();
311   switch (TII->lookupName((const char *)Name.bytes_begin(), Name.size())) {
312   default:
313     return false;
314   case AMDGPUIntrinsic::SI_fs_interp:
315   case AMDGPUIntrinsic::SI_fs_constant:
316     return true;
317   }
318 }
319 
320 static bool isArgPassedInSGPR(const Argument *A) {
321   const Function *F = A->getParent();
322 
323   // Arguments to compute shaders are never a source of divergence.
324   if (!AMDGPU::isShader(F->getCallingConv()))
325     return true;
326 
327   // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
328   if (F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::InReg) ||
329       F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::ByVal))
330     return true;
331 
332   // Everything else is in VGPRs.
333   return false;
334 }
335 
336 ///
337 /// \returns true if the result of the value could potentially be
338 /// different across workitems in a wavefront.
339 bool AMDGPUTTIImpl::isSourceOfDivergence(const Value *V) const {
340 
341   if (const Argument *A = dyn_cast<Argument>(V))
342     return !isArgPassedInSGPR(A);
343 
344   // Loads from the private address space are divergent, because threads
345   // can execute the load instruction with the same inputs and get different
346   // results.
347   //
348   // All other loads are not divergent, because if threads issue loads with the
349   // same arguments, they will always get the same result.
350   if (const LoadInst *Load = dyn_cast<LoadInst>(V))
351     return Load->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
352 
353   // Atomics are divergent because they are executed sequentially: when an
354   // atomic operation refers to the same address in each thread, then each
355   // thread after the first sees the value written by the previous thread as
356   // original value.
357   if (isa<AtomicRMWInst>(V) || isa<AtomicCmpXchgInst>(V))
358     return true;
359 
360   if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V)) {
361     const TargetMachine &TM = getTLI()->getTargetMachine();
362     return isIntrinsicSourceOfDivergence(TM.getIntrinsicInfo(), Intrinsic);
363   }
364 
365   // Assume all function calls are a source of divergence.
366   if (isa<CallInst>(V) || isa<InvokeInst>(V))
367     return true;
368 
369   return false;
370 }
371