1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU TargetMachine interface definition for hw codgen targets.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
16 
17 #include "GCNSubtarget.h"
18 #include "llvm/CodeGen/TargetPassConfig.h"
19 #include "llvm/Target/TargetMachine.h"
20 
21 namespace llvm {
22 
23 class ScheduleDAGMILive;
24 
25 //===----------------------------------------------------------------------===//
26 // AMDGPU Target Machine (R600+)
27 //===----------------------------------------------------------------------===//
28 
29 class AMDGPUTargetMachine : public LLVMTargetMachine {
30 protected:
31   std::unique_ptr<TargetLoweringObjectFile> TLOF;
32 
33   StringRef getGPUName(const Function &F) const;
34   StringRef getFeatureString(const Function &F) const;
35 
36 public:
37   static bool EnableLateStructurizeCFG;
38   static bool EnableFunctionCalls;
39   static bool EnableFixedFunctionABI;
40   static bool EnableLowerModuleLDS;
41 
42   AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
43                       StringRef FS, TargetOptions Options,
44                       Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
45                       CodeGenOpt::Level OL);
46   ~AMDGPUTargetMachine() override;
47 
48   const TargetSubtargetInfo *getSubtargetImpl() const;
49   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0;
50 
51   TargetLoweringObjectFile *getObjFileLowering() const override {
52     return TLOF.get();
53   }
54 
55   void adjustPassManager(PassManagerBuilder &) override;
56 
57   void registerPassBuilderCallbacks(PassBuilder &PB) override;
58   void registerDefaultAliasAnalyses(AAManager &) override;
59 
60   /// Get the integer value of a null pointer in the given address space.
61   static int64_t getNullPointerValue(unsigned AddrSpace);
62 
63   bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
64 
65   unsigned getAssumedAddrSpace(const Value *V) const override;
66 };
67 
68 //===----------------------------------------------------------------------===//
69 // GCN Target Machine (SI+)
70 //===----------------------------------------------------------------------===//
71 
72 class GCNTargetMachine final : public AMDGPUTargetMachine {
73 private:
74   mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
75 
76 public:
77   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
78                    StringRef FS, TargetOptions Options,
79                    Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
80                    CodeGenOpt::Level OL, bool JIT);
81 
82   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
83 
84   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override;
85 
86   TargetTransformInfo getTargetTransformInfo(const Function &F) override;
87 
88   bool useIPRA() const override {
89     return true;
90   }
91 
92   yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
93   yaml::MachineFunctionInfo *
94   convertFuncInfoToYAML(const MachineFunction &MF) const override;
95   bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
96                                 PerFunctionMIParsingState &PFS,
97                                 SMDiagnostic &Error,
98                                 SMRange &SourceRange) const override;
99 };
100 
101 //===----------------------------------------------------------------------===//
102 // AMDGPU Pass Setup
103 //===----------------------------------------------------------------------===//
104 
105 class AMDGPUPassConfig : public TargetPassConfig {
106 public:
107   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM);
108 
109   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
110     return getTM<AMDGPUTargetMachine>();
111   }
112 
113   ScheduleDAGInstrs *
114   createMachineScheduler(MachineSchedContext *C) const override;
115 
116   void addEarlyCSEOrGVNPass();
117   void addStraightLineScalarOptimizationPasses();
118   void addIRPasses() override;
119   void addCodeGenPrepare() override;
120   bool addPreISel() override;
121   bool addInstSelector() override;
122   bool addGCPasses() override;
123 
124   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
125 
126   /// Check if a pass is enabled given \p Opt option. The option always
127   /// overrides defaults if explicitely used. Otherwise its default will
128   /// be used given that a pass shall work at an optimization \p Level
129   /// minimum.
130   bool isPassEnabled(const cl::opt<bool> &Opt,
131                      CodeGenOpt::Level Level = CodeGenOpt::Default) const {
132     if (Opt.getNumOccurrences())
133       return Opt;
134     if (TM->getOptLevel() < Level)
135       return false;
136     return Opt;
137   }
138 };
139 
140 } // end namespace llvm
141 
142 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
143