1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU TargetMachine interface definition for hw codgen targets.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
17 
18 #include "AMDGPUIntrinsicInfo.h"
19 #include "AMDGPUSubtarget.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/StringMap.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/Support/CodeGen.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include <memory>
27 
28 namespace llvm {
29 
30 //===----------------------------------------------------------------------===//
31 // AMDGPU Target Machine (R600+)
32 //===----------------------------------------------------------------------===//
33 
34 class AMDGPUTargetMachine : public LLVMTargetMachine {
35 protected:
36   std::unique_ptr<TargetLoweringObjectFile> TLOF;
37   AMDGPUIntrinsicInfo IntrinsicInfo;
38   AMDGPUAS AS;
39 
40   StringRef getGPUName(const Function &F) const;
41   StringRef getFeatureString(const Function &F) const;
42 
43 public:
44   static bool EnableLateStructurizeCFG;
45 
46   AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
47                       StringRef FS, TargetOptions Options,
48                       Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
49                       CodeGenOpt::Level OL);
50   ~AMDGPUTargetMachine() override;
51 
52   const AMDGPUSubtarget *getSubtargetImpl() const;
53   const AMDGPUSubtarget *getSubtargetImpl(const Function &) const override = 0;
54 
55   const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
56     return &IntrinsicInfo;
57   }
58   TargetTransformInfo getTargetTransformInfo(const Function &F) override;
59 
60   TargetLoweringObjectFile *getObjFileLowering() const override {
61     return TLOF.get();
62   }
63   AMDGPUAS getAMDGPUAS() const {
64     return AS;
65   }
66 
67   void adjustPassManager(PassManagerBuilder &) override;
68   /// Get the integer value of a null pointer in the given address space.
69   uint64_t getNullPointerValue(unsigned AddrSpace) const {
70     if (AddrSpace == AS.LOCAL_ADDRESS || AddrSpace == AS.REGION_ADDRESS)
71       return -1;
72     return 0;
73   }
74 };
75 
76 //===----------------------------------------------------------------------===//
77 // R600 Target Machine (R600 -> Cayman)
78 //===----------------------------------------------------------------------===//
79 
80 class R600TargetMachine final : public AMDGPUTargetMachine {
81 private:
82   mutable StringMap<std::unique_ptr<R600Subtarget>> SubtargetMap;
83 
84 public:
85   R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
86                     StringRef FS, TargetOptions Options,
87                     Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
88                     CodeGenOpt::Level OL, bool JIT);
89 
90   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
91 
92   const R600Subtarget *getSubtargetImpl(const Function &) const override;
93 
94   bool isMachineVerifierClean() const override {
95     return false;
96   }
97 };
98 
99 //===----------------------------------------------------------------------===//
100 // GCN Target Machine (SI+)
101 //===----------------------------------------------------------------------===//
102 
103 class GCNTargetMachine final : public AMDGPUTargetMachine {
104 private:
105   mutable StringMap<std::unique_ptr<SISubtarget>> SubtargetMap;
106 
107 public:
108   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
109                    StringRef FS, TargetOptions Options,
110                    Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
111                    CodeGenOpt::Level OL, bool JIT);
112 
113   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
114 
115   const SISubtarget *getSubtargetImpl(const Function &) const override;
116 
117   bool useIPRA() const override {
118     return true;
119   }
120 };
121 
122 } // end namespace llvm
123 
124 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
125