1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU TargetMachine interface definition for hw codgen targets.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
16 
17 #include "GCNSubtarget.h"
18 #include "llvm/CodeGen/TargetPassConfig.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include <utility>
21 
22 namespace llvm {
23 
24 class ScheduleDAGMILive;
25 
26 //===----------------------------------------------------------------------===//
27 // AMDGPU Target Machine (R600+)
28 //===----------------------------------------------------------------------===//
29 
30 class AMDGPUTargetMachine : public LLVMTargetMachine {
31 protected:
32   std::unique_ptr<TargetLoweringObjectFile> TLOF;
33 
34   StringRef getGPUName(const Function &F) const;
35   StringRef getFeatureString(const Function &F) const;
36 
37 public:
38   static bool EnableLateStructurizeCFG;
39   static bool EnableFunctionCalls;
40   static bool EnableLowerModuleLDS;
41 
42   AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
43                       StringRef FS, TargetOptions Options,
44                       Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
45                       CodeGenOpt::Level OL);
46   ~AMDGPUTargetMachine() override;
47 
48   const TargetSubtargetInfo *getSubtargetImpl() const;
49   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0;
50 
51   TargetLoweringObjectFile *getObjFileLowering() const override {
52     return TLOF.get();
53   }
54 
55   void adjustPassManager(PassManagerBuilder &) override;
56 
57   void registerPassBuilderCallbacks(PassBuilder &PB) override;
58   void registerDefaultAliasAnalyses(AAManager &) override;
59 
60   /// Get the integer value of a null pointer in the given address space.
61   static int64_t getNullPointerValue(unsigned AddrSpace);
62 
63   bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
64 
65   unsigned getAssumedAddrSpace(const Value *V) const override;
66 
67   std::pair<const Value *, unsigned>
68   getPredicatedAddrSpace(const Value *V) const override;
69 };
70 
71 //===----------------------------------------------------------------------===//
72 // GCN Target Machine (SI+)
73 //===----------------------------------------------------------------------===//
74 
75 class GCNTargetMachine final : public AMDGPUTargetMachine {
76 private:
77   mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
78 
79 public:
80   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
81                    StringRef FS, TargetOptions Options,
82                    Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
83                    CodeGenOpt::Level OL, bool JIT);
84 
85   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
86 
87   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override;
88 
89   TargetTransformInfo getTargetTransformInfo(const Function &F) override;
90 
91   bool useIPRA() const override {
92     return true;
93   }
94 
95   yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
96   yaml::MachineFunctionInfo *
97   convertFuncInfoToYAML(const MachineFunction &MF) const override;
98   bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
99                                 PerFunctionMIParsingState &PFS,
100                                 SMDiagnostic &Error,
101                                 SMRange &SourceRange) const override;
102 };
103 
104 //===----------------------------------------------------------------------===//
105 // AMDGPU Pass Setup
106 //===----------------------------------------------------------------------===//
107 
108 class AMDGPUPassConfig : public TargetPassConfig {
109 public:
110   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM);
111 
112   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
113     return getTM<AMDGPUTargetMachine>();
114   }
115 
116   ScheduleDAGInstrs *
117   createMachineScheduler(MachineSchedContext *C) const override;
118 
119   void addEarlyCSEOrGVNPass();
120   void addStraightLineScalarOptimizationPasses();
121   void addIRPasses() override;
122   void addCodeGenPrepare() override;
123   bool addPreISel() override;
124   bool addInstSelector() override;
125   bool addGCPasses() override;
126 
127   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
128 
129   /// Check if a pass is enabled given \p Opt option. The option always
130   /// overrides defaults if explicitly used. Otherwise its default will
131   /// be used given that a pass shall work at an optimization \p Level
132   /// minimum.
133   bool isPassEnabled(const cl::opt<bool> &Opt,
134                      CodeGenOpt::Level Level = CodeGenOpt::Default) const {
135     if (Opt.getNumOccurrences())
136       return Opt;
137     if (TM->getOptLevel() < Level)
138       return false;
139     return Opt;
140   }
141 };
142 
143 } // end namespace llvm
144 
145 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
146