1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU TargetMachine interface definition for hw codgen targets.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
16 
17 #include "GCNSubtarget.h"
18 #include "llvm/CodeGen/TargetPassConfig.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include <utility>
21 
22 namespace llvm {
23 
24 class ScheduleDAGMILive;
25 
26 //===----------------------------------------------------------------------===//
27 // AMDGPU Target Machine (R600+)
28 //===----------------------------------------------------------------------===//
29 
30 class AMDGPUTargetMachine : public LLVMTargetMachine {
31 protected:
32   std::unique_ptr<TargetLoweringObjectFile> TLOF;
33 
34   StringRef getGPUName(const Function &F) const;
35   StringRef getFeatureString(const Function &F) const;
36 
37 public:
38   static bool EnableLateStructurizeCFG;
39   static bool EnableFunctionCalls;
40   static bool EnableFixedFunctionABI;
41   static bool EnableLowerModuleLDS;
42 
43   AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
44                       StringRef FS, TargetOptions Options,
45                       Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
46                       CodeGenOpt::Level OL);
47   ~AMDGPUTargetMachine() override;
48 
49   const TargetSubtargetInfo *getSubtargetImpl() const;
50   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0;
51 
52   TargetLoweringObjectFile *getObjFileLowering() const override {
53     return TLOF.get();
54   }
55 
56   void adjustPassManager(PassManagerBuilder &) override;
57 
58   void registerPassBuilderCallbacks(PassBuilder &PB) override;
59   void registerDefaultAliasAnalyses(AAManager &) override;
60 
61   /// Get the integer value of a null pointer in the given address space.
62   static int64_t getNullPointerValue(unsigned AddrSpace);
63 
64   bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
65 
66   unsigned getAssumedAddrSpace(const Value *V) const override;
67 
68   std::pair<const Value *, unsigned>
69   getPredicatedAddrSpace(const Value *V) const override;
70 };
71 
72 //===----------------------------------------------------------------------===//
73 // GCN Target Machine (SI+)
74 //===----------------------------------------------------------------------===//
75 
76 class GCNTargetMachine final : public AMDGPUTargetMachine {
77 private:
78   mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
79 
80 public:
81   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
82                    StringRef FS, TargetOptions Options,
83                    Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
84                    CodeGenOpt::Level OL, bool JIT);
85 
86   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
87 
88   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override;
89 
90   TargetTransformInfo getTargetTransformInfo(const Function &F) override;
91 
92   bool useIPRA() const override {
93     return true;
94   }
95 
96   yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
97   yaml::MachineFunctionInfo *
98   convertFuncInfoToYAML(const MachineFunction &MF) const override;
99   bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
100                                 PerFunctionMIParsingState &PFS,
101                                 SMDiagnostic &Error,
102                                 SMRange &SourceRange) const override;
103 };
104 
105 //===----------------------------------------------------------------------===//
106 // AMDGPU Pass Setup
107 //===----------------------------------------------------------------------===//
108 
109 class AMDGPUPassConfig : public TargetPassConfig {
110 public:
111   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM);
112 
113   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
114     return getTM<AMDGPUTargetMachine>();
115   }
116 
117   ScheduleDAGInstrs *
118   createMachineScheduler(MachineSchedContext *C) const override;
119 
120   void addEarlyCSEOrGVNPass();
121   void addStraightLineScalarOptimizationPasses();
122   void addIRPasses() override;
123   void addCodeGenPrepare() override;
124   bool addPreISel() override;
125   bool addInstSelector() override;
126   bool addGCPasses() override;
127 
128   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
129 
130   /// Check if a pass is enabled given \p Opt option. The option always
131   /// overrides defaults if explicitly used. Otherwise its default will
132   /// be used given that a pass shall work at an optimization \p Level
133   /// minimum.
134   bool isPassEnabled(const cl::opt<bool> &Opt,
135                      CodeGenOpt::Level Level = CodeGenOpt::Default) const {
136     if (Opt.getNumOccurrences())
137       return Opt;
138     if (TM->getOptLevel() < Level)
139       return false;
140     return Opt;
141   }
142 };
143 
144 } // end namespace llvm
145 
146 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
147