1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUInstructionSelector.h"
20 #include "AMDGPULegalizerInfo.h"
21 #include "AMDGPUMacroFusion.h"
22 #include "AMDGPUTargetObjectFile.h"
23 #include "AMDGPUTargetTransformInfo.h"
24 #include "GCNIterativeScheduler.h"
25 #include "GCNSchedStrategy.h"
26 #include "R600MachineScheduler.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIMachineScheduler.h"
29 #include "TargetInfo/AMDGPUTargetInfo.h"
30 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
31 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
32 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
33 #include "llvm/CodeGen/GlobalISel/Localizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MIRParser/MIParser.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/LegacyPassManager.h"
41 #include "llvm/InitializePasses.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/TargetRegistry.h"
46 #include "llvm/Target/TargetLoweringObjectFile.h"
47 #include "llvm/Transforms/IPO.h"
48 #include "llvm/Transforms/IPO/AlwaysInliner.h"
49 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
50 #include "llvm/Transforms/Scalar.h"
51 #include "llvm/Transforms/Scalar/GVN.h"
52 #include "llvm/Transforms/Utils.h"
53 #include "llvm/Transforms/Vectorize.h"
54 #include <memory>
55 
56 using namespace llvm;
57 
58 static cl::opt<bool> EnableR600StructurizeCFG(
59   "r600-ir-structurize",
60   cl::desc("Use StructurizeCFG IR pass"),
61   cl::init(true));
62 
63 static cl::opt<bool> EnableSROA(
64   "amdgpu-sroa",
65   cl::desc("Run SROA after promote alloca pass"),
66   cl::ReallyHidden,
67   cl::init(true));
68 
69 static cl::opt<bool>
70 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
71                         cl::desc("Run early if-conversion"),
72                         cl::init(false));
73 
74 static cl::opt<bool>
75 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
76             cl::desc("Run pre-RA exec mask optimizations"),
77             cl::init(true));
78 
79 static cl::opt<bool> EnableR600IfConvert(
80   "r600-if-convert",
81   cl::desc("Use if conversion pass"),
82   cl::ReallyHidden,
83   cl::init(true));
84 
85 // Option to disable vectorizer for tests.
86 static cl::opt<bool> EnableLoadStoreVectorizer(
87   "amdgpu-load-store-vectorizer",
88   cl::desc("Enable load store vectorizer"),
89   cl::init(true),
90   cl::Hidden);
91 
92 // Option to control global loads scalarization
93 static cl::opt<bool> ScalarizeGlobal(
94   "amdgpu-scalarize-global-loads",
95   cl::desc("Enable global load scalarization"),
96   cl::init(true),
97   cl::Hidden);
98 
99 // Option to run internalize pass.
100 static cl::opt<bool> InternalizeSymbols(
101   "amdgpu-internalize-symbols",
102   cl::desc("Enable elimination of non-kernel functions and unused globals"),
103   cl::init(false),
104   cl::Hidden);
105 
106 // Option to inline all early.
107 static cl::opt<bool> EarlyInlineAll(
108   "amdgpu-early-inline-all",
109   cl::desc("Inline all functions early"),
110   cl::init(false),
111   cl::Hidden);
112 
113 static cl::opt<bool> EnableSDWAPeephole(
114   "amdgpu-sdwa-peephole",
115   cl::desc("Enable SDWA peepholer"),
116   cl::init(true));
117 
118 static cl::opt<bool> EnableDPPCombine(
119   "amdgpu-dpp-combine",
120   cl::desc("Enable DPP combiner"),
121   cl::init(true));
122 
123 // Enable address space based alias analysis
124 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
125   cl::desc("Enable AMDGPU Alias Analysis"),
126   cl::init(true));
127 
128 // Option to run late CFG structurizer
129 static cl::opt<bool, true> LateCFGStructurize(
130   "amdgpu-late-structurize",
131   cl::desc("Enable late CFG structurization"),
132   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
133   cl::Hidden);
134 
135 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
136   "amdgpu-function-calls",
137   cl::desc("Enable AMDGPU function call support"),
138   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
139   cl::init(true),
140   cl::Hidden);
141 
142 // Enable lib calls simplifications
143 static cl::opt<bool> EnableLibCallSimplify(
144   "amdgpu-simplify-libcall",
145   cl::desc("Enable amdgpu library simplifications"),
146   cl::init(true),
147   cl::Hidden);
148 
149 static cl::opt<bool> EnableLowerKernelArguments(
150   "amdgpu-ir-lower-kernel-arguments",
151   cl::desc("Lower kernel argument loads in IR pass"),
152   cl::init(true),
153   cl::Hidden);
154 
155 static cl::opt<bool> EnableRegReassign(
156   "amdgpu-reassign-regs",
157   cl::desc("Enable register reassign optimizations on gfx10+"),
158   cl::init(true),
159   cl::Hidden);
160 
161 // Enable atomic optimization
162 static cl::opt<bool> EnableAtomicOptimizations(
163   "amdgpu-atomic-optimizations",
164   cl::desc("Enable atomic optimizations"),
165   cl::init(false),
166   cl::Hidden);
167 
168 // Enable Mode register optimization
169 static cl::opt<bool> EnableSIModeRegisterPass(
170   "amdgpu-mode-register",
171   cl::desc("Enable mode register pass"),
172   cl::init(true),
173   cl::Hidden);
174 
175 // Option is used in lit tests to prevent deadcoding of patterns inspected.
176 static cl::opt<bool>
177 EnableDCEInRA("amdgpu-dce-in-ra",
178     cl::init(true), cl::Hidden,
179     cl::desc("Enable machine DCE inside regalloc"));
180 
181 static cl::opt<bool> EnableScalarIRPasses(
182   "amdgpu-scalar-ir-passes",
183   cl::desc("Enable scalar IR passes"),
184   cl::init(true),
185   cl::Hidden);
186 
187 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
188   // Register the target
189   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
190   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
191 
192   PassRegistry *PR = PassRegistry::getPassRegistry();
193   initializeR600ClauseMergePassPass(*PR);
194   initializeR600ControlFlowFinalizerPass(*PR);
195   initializeR600PacketizerPass(*PR);
196   initializeR600ExpandSpecialInstrsPassPass(*PR);
197   initializeR600VectorRegMergerPass(*PR);
198   initializeGlobalISel(*PR);
199   initializeAMDGPUDAGToDAGISelPass(*PR);
200   initializeGCNDPPCombinePass(*PR);
201   initializeSILowerI1CopiesPass(*PR);
202   initializeSILowerSGPRSpillsPass(*PR);
203   initializeSIFixSGPRCopiesPass(*PR);
204   initializeSIFixVGPRCopiesPass(*PR);
205   initializeSIFixupVectorISelPass(*PR);
206   initializeSIFoldOperandsPass(*PR);
207   initializeSIPeepholeSDWAPass(*PR);
208   initializeSIShrinkInstructionsPass(*PR);
209   initializeSIOptimizeExecMaskingPreRAPass(*PR);
210   initializeSILoadStoreOptimizerPass(*PR);
211   initializeAMDGPUFixFunctionBitcastsPass(*PR);
212   initializeAMDGPUAlwaysInlinePass(*PR);
213   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
214   initializeAMDGPUAnnotateUniformValuesPass(*PR);
215   initializeAMDGPUArgumentUsageInfoPass(*PR);
216   initializeAMDGPUAtomicOptimizerPass(*PR);
217   initializeAMDGPULowerKernelArgumentsPass(*PR);
218   initializeAMDGPULowerKernelAttributesPass(*PR);
219   initializeAMDGPULowerIntrinsicsPass(*PR);
220   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
221   initializeAMDGPUPreLegalizerCombinerPass(*PR);
222   initializeAMDGPUPromoteAllocaPass(*PR);
223   initializeAMDGPUCodeGenPreparePass(*PR);
224   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
225   initializeAMDGPUPropagateAttributesLatePass(*PR);
226   initializeAMDGPURewriteOutArgumentsPass(*PR);
227   initializeAMDGPUUnifyMetadataPass(*PR);
228   initializeSIAnnotateControlFlowPass(*PR);
229   initializeSIInsertWaitcntsPass(*PR);
230   initializeSIModeRegisterPass(*PR);
231   initializeSIWholeQuadModePass(*PR);
232   initializeSILowerControlFlowPass(*PR);
233   initializeSIRemoveShortExecBranchesPass(*PR);
234   initializeSIInsertSkipsPass(*PR);
235   initializeSIMemoryLegalizerPass(*PR);
236   initializeSIOptimizeExecMaskingPass(*PR);
237   initializeSIPreAllocateWWMRegsPass(*PR);
238   initializeSIFormMemoryClausesPass(*PR);
239   initializeSIPostRABundlerPass(*PR);
240   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
241   initializeAMDGPUAAWrapperPassPass(*PR);
242   initializeAMDGPUExternalAAWrapperPass(*PR);
243   initializeAMDGPUUseNativeCallsPass(*PR);
244   initializeAMDGPUSimplifyLibCallsPass(*PR);
245   initializeAMDGPUInlinerPass(*PR);
246   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
247   initializeGCNRegBankReassignPass(*PR);
248   initializeGCNNSAReassignPass(*PR);
249   initializeSIAddIMGInitPass(*PR);
250 }
251 
252 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
253   return std::make_unique<AMDGPUTargetObjectFile>();
254 }
255 
256 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
257   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
258 }
259 
260 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
261   return new SIScheduleDAGMI(C);
262 }
263 
264 static ScheduleDAGInstrs *
265 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
266   ScheduleDAGMILive *DAG =
267     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
268   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
269   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
270   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
271   return DAG;
272 }
273 
274 static ScheduleDAGInstrs *
275 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
276   auto DAG = new GCNIterativeScheduler(C,
277     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
278   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
279   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
280   return DAG;
281 }
282 
283 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
284   return new GCNIterativeScheduler(C,
285     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
286 }
287 
288 static ScheduleDAGInstrs *
289 createIterativeILPMachineScheduler(MachineSchedContext *C) {
290   auto DAG = new GCNIterativeScheduler(C,
291     GCNIterativeScheduler::SCHEDULE_ILP);
292   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
293   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
294   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
295   return DAG;
296 }
297 
298 static MachineSchedRegistry
299 R600SchedRegistry("r600", "Run R600's custom scheduler",
300                    createR600MachineScheduler);
301 
302 static MachineSchedRegistry
303 SISchedRegistry("si", "Run SI's custom scheduler",
304                 createSIMachineScheduler);
305 
306 static MachineSchedRegistry
307 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
308                              "Run GCN scheduler to maximize occupancy",
309                              createGCNMaxOccupancyMachineScheduler);
310 
311 static MachineSchedRegistry
312 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
313   "Run GCN scheduler to maximize occupancy (experimental)",
314   createIterativeGCNMaxOccupancyMachineScheduler);
315 
316 static MachineSchedRegistry
317 GCNMinRegSchedRegistry("gcn-minreg",
318   "Run GCN iterative scheduler for minimal register usage (experimental)",
319   createMinRegScheduler);
320 
321 static MachineSchedRegistry
322 GCNILPSchedRegistry("gcn-ilp",
323   "Run GCN iterative scheduler for ILP scheduling (experimental)",
324   createIterativeILPMachineScheduler);
325 
326 static StringRef computeDataLayout(const Triple &TT) {
327   if (TT.getArch() == Triple::r600) {
328     // 32-bit pointers.
329       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
330              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
331   }
332 
333   // 32-bit private, local, and region pointers. 64-bit global, constant and
334   // flat, non-integral buffer fat pointers.
335     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
336          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
337          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
338          "-ni:7";
339 }
340 
341 LLVM_READNONE
342 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
343   if (!GPU.empty())
344     return GPU;
345 
346   // Need to default to a target with flat support for HSA.
347   if (TT.getArch() == Triple::amdgcn)
348     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
349 
350   return "r600";
351 }
352 
353 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
354   // The AMDGPU toolchain only supports generating shared objects, so we
355   // must always use PIC.
356   return Reloc::PIC_;
357 }
358 
359 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
360                                          StringRef CPU, StringRef FS,
361                                          TargetOptions Options,
362                                          Optional<Reloc::Model> RM,
363                                          Optional<CodeModel::Model> CM,
364                                          CodeGenOpt::Level OptLevel)
365     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
366                         FS, Options, getEffectiveRelocModel(RM),
367                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
368       TLOF(createTLOF(getTargetTriple())) {
369   initAsmInfo();
370 }
371 
372 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
373 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
374 
375 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
376 
377 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
378   Attribute GPUAttr = F.getFnAttribute("target-cpu");
379   return GPUAttr.hasAttribute(Attribute::None) ?
380     getTargetCPU() : GPUAttr.getValueAsString();
381 }
382 
383 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
384   Attribute FSAttr = F.getFnAttribute("target-features");
385 
386   return FSAttr.hasAttribute(Attribute::None) ?
387     getTargetFeatureString() :
388     FSAttr.getValueAsString();
389 }
390 
391 /// Predicate for Internalize pass.
392 static bool mustPreserveGV(const GlobalValue &GV) {
393   if (const Function *F = dyn_cast<Function>(&GV))
394     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
395 
396   return !GV.use_empty();
397 }
398 
399 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
400   Builder.DivergentTarget = true;
401 
402   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
403   bool Internalize = InternalizeSymbols;
404   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
405   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
406   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
407 
408   if (EnableFunctionCalls) {
409     delete Builder.Inliner;
410     Builder.Inliner = createAMDGPUFunctionInliningPass();
411   }
412 
413   Builder.addExtension(
414     PassManagerBuilder::EP_ModuleOptimizerEarly,
415     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
416                                                legacy::PassManagerBase &PM) {
417       if (AMDGPUAA) {
418         PM.add(createAMDGPUAAWrapperPass());
419         PM.add(createAMDGPUExternalAAWrapperPass());
420       }
421       PM.add(createAMDGPUUnifyMetadataPass());
422       PM.add(createAMDGPUPrintfRuntimeBinding());
423       PM.add(createAMDGPUPropagateAttributesLatePass(this));
424       if (Internalize) {
425         PM.add(createInternalizePass(mustPreserveGV));
426         PM.add(createGlobalDCEPass());
427       }
428       if (EarlyInline)
429         PM.add(createAMDGPUAlwaysInlinePass(false));
430   });
431 
432   const auto &Opt = Options;
433   Builder.addExtension(
434     PassManagerBuilder::EP_EarlyAsPossible,
435     [AMDGPUAA, LibCallSimplify, &Opt, this](const PassManagerBuilder &,
436                                             legacy::PassManagerBase &PM) {
437       if (AMDGPUAA) {
438         PM.add(createAMDGPUAAWrapperPass());
439         PM.add(createAMDGPUExternalAAWrapperPass());
440       }
441       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
442       PM.add(llvm::createAMDGPUUseNativeCallsPass());
443       if (LibCallSimplify)
444         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt, this));
445   });
446 
447   Builder.addExtension(
448     PassManagerBuilder::EP_CGSCCOptimizerLate,
449     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
450       // Add infer address spaces pass to the opt pipeline after inlining
451       // but before SROA to increase SROA opportunities.
452       PM.add(createInferAddressSpacesPass());
453 
454       // This should run after inlining to have any chance of doing anything,
455       // and before other cleanup optimizations.
456       PM.add(createAMDGPULowerKernelAttributesPass());
457   });
458 }
459 
460 //===----------------------------------------------------------------------===//
461 // R600 Target Machine (R600 -> Cayman)
462 //===----------------------------------------------------------------------===//
463 
464 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
465                                      StringRef CPU, StringRef FS,
466                                      TargetOptions Options,
467                                      Optional<Reloc::Model> RM,
468                                      Optional<CodeModel::Model> CM,
469                                      CodeGenOpt::Level OL, bool JIT)
470     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
471   setRequiresStructuredCFG(true);
472 
473   // Override the default since calls aren't supported for r600.
474   if (EnableFunctionCalls &&
475       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
476     EnableFunctionCalls = false;
477 }
478 
479 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
480   const Function &F) const {
481   StringRef GPU = getGPUName(F);
482   StringRef FS = getFeatureString(F);
483 
484   SmallString<128> SubtargetKey(GPU);
485   SubtargetKey.append(FS);
486 
487   auto &I = SubtargetMap[SubtargetKey];
488   if (!I) {
489     // This needs to be done before we create a new subtarget since any
490     // creation will depend on the TM and the code generation flags on the
491     // function that reside in TargetOptions.
492     resetTargetOptions(F);
493     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
494   }
495 
496   return I.get();
497 }
498 
499 TargetTransformInfo
500 R600TargetMachine::getTargetTransformInfo(const Function &F) {
501   return TargetTransformInfo(R600TTIImpl(this, F));
502 }
503 
504 //===----------------------------------------------------------------------===//
505 // GCN Target Machine (SI+)
506 //===----------------------------------------------------------------------===//
507 
508 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
509                                    StringRef CPU, StringRef FS,
510                                    TargetOptions Options,
511                                    Optional<Reloc::Model> RM,
512                                    Optional<CodeModel::Model> CM,
513                                    CodeGenOpt::Level OL, bool JIT)
514     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
515 
516 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
517   StringRef GPU = getGPUName(F);
518   StringRef FS = getFeatureString(F);
519 
520   SmallString<128> SubtargetKey(GPU);
521   SubtargetKey.append(FS);
522 
523   auto &I = SubtargetMap[SubtargetKey];
524   if (!I) {
525     // This needs to be done before we create a new subtarget since any
526     // creation will depend on the TM and the code generation flags on the
527     // function that reside in TargetOptions.
528     resetTargetOptions(F);
529     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
530   }
531 
532   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
533 
534   return I.get();
535 }
536 
537 TargetTransformInfo
538 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
539   return TargetTransformInfo(GCNTTIImpl(this, F));
540 }
541 
542 //===----------------------------------------------------------------------===//
543 // AMDGPU Pass Setup
544 //===----------------------------------------------------------------------===//
545 
546 namespace {
547 
548 class AMDGPUPassConfig : public TargetPassConfig {
549 public:
550   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
551     : TargetPassConfig(TM, PM) {
552     // Exceptions and StackMaps are not supported, so these passes will never do
553     // anything.
554     disablePass(&StackMapLivenessID);
555     disablePass(&FuncletLayoutID);
556   }
557 
558   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
559     return getTM<AMDGPUTargetMachine>();
560   }
561 
562   ScheduleDAGInstrs *
563   createMachineScheduler(MachineSchedContext *C) const override {
564     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
565     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
566     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
567     return DAG;
568   }
569 
570   void addEarlyCSEOrGVNPass();
571   void addStraightLineScalarOptimizationPasses();
572   void addIRPasses() override;
573   void addCodeGenPrepare() override;
574   bool addPreISel() override;
575   bool addInstSelector() override;
576   bool addGCPasses() override;
577 
578   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
579 };
580 
581 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
582   return getStandardCSEConfigForOpt(TM->getOptLevel());
583 }
584 
585 class R600PassConfig final : public AMDGPUPassConfig {
586 public:
587   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
588     : AMDGPUPassConfig(TM, PM) {}
589 
590   ScheduleDAGInstrs *createMachineScheduler(
591     MachineSchedContext *C) const override {
592     return createR600MachineScheduler(C);
593   }
594 
595   bool addPreISel() override;
596   bool addInstSelector() override;
597   void addPreRegAlloc() override;
598   void addPreSched2() override;
599   void addPreEmitPass() override;
600 };
601 
602 class GCNPassConfig final : public AMDGPUPassConfig {
603 public:
604   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
605     : AMDGPUPassConfig(TM, PM) {
606     // It is necessary to know the register usage of the entire call graph.  We
607     // allow calls without EnableAMDGPUFunctionCalls if they are marked
608     // noinline, so this is always required.
609     setRequiresCodeGenSCCOrder(true);
610   }
611 
612   GCNTargetMachine &getGCNTargetMachine() const {
613     return getTM<GCNTargetMachine>();
614   }
615 
616   ScheduleDAGInstrs *
617   createMachineScheduler(MachineSchedContext *C) const override;
618 
619   bool addPreISel() override;
620   void addMachineSSAOptimization() override;
621   bool addILPOpts() override;
622   bool addInstSelector() override;
623   bool addIRTranslator() override;
624   void addPreLegalizeMachineIR() override;
625   bool addLegalizeMachineIR() override;
626   bool addRegBankSelect() override;
627   bool addGlobalInstructionSelect() override;
628   void addFastRegAlloc() override;
629   void addOptimizedRegAlloc() override;
630   void addPreRegAlloc() override;
631   bool addPreRewrite() override;
632   void addPostRegAlloc() override;
633   void addPreSched2() override;
634   void addPreEmitPass() override;
635 };
636 
637 } // end anonymous namespace
638 
639 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
640   if (getOptLevel() == CodeGenOpt::Aggressive)
641     addPass(createGVNPass());
642   else
643     addPass(createEarlyCSEPass());
644 }
645 
646 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
647   addPass(createLICMPass());
648   addPass(createSeparateConstOffsetFromGEPPass());
649   addPass(createSpeculativeExecutionPass());
650   // ReassociateGEPs exposes more opportunites for SLSR. See
651   // the example in reassociate-geps-and-slsr.ll.
652   addPass(createStraightLineStrengthReducePass());
653   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
654   // EarlyCSE can reuse.
655   addEarlyCSEOrGVNPass();
656   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
657   addPass(createNaryReassociatePass());
658   // NaryReassociate on GEPs creates redundant common expressions, so run
659   // EarlyCSE after it.
660   addPass(createEarlyCSEPass());
661 }
662 
663 void AMDGPUPassConfig::addIRPasses() {
664   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
665 
666   // There is no reason to run these.
667   disablePass(&StackMapLivenessID);
668   disablePass(&FuncletLayoutID);
669   disablePass(&PatchableFunctionID);
670 
671   addPass(createAMDGPUPrintfRuntimeBinding());
672 
673   // This must occur before inlining, as the inliner will not look through
674   // bitcast calls.
675   addPass(createAMDGPUFixFunctionBitcastsPass());
676 
677   // A call to propagate attributes pass in the backend in case opt was not run.
678   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
679 
680   addPass(createAtomicExpandPass());
681 
682 
683   addPass(createAMDGPULowerIntrinsicsPass());
684 
685   // Function calls are not supported, so make sure we inline everything.
686   addPass(createAMDGPUAlwaysInlinePass());
687   addPass(createAlwaysInlinerLegacyPass());
688   // We need to add the barrier noop pass, otherwise adding the function
689   // inlining pass will cause all of the PassConfigs passes to be run
690   // one function at a time, which means if we have a nodule with two
691   // functions, then we will generate code for the first function
692   // without ever running any passes on the second.
693   addPass(createBarrierNoopPass());
694 
695   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
696   if (TM.getTargetTriple().getArch() == Triple::r600)
697     addPass(createR600OpenCLImageTypeLoweringPass());
698 
699   // Replace OpenCL enqueued block function pointers with global variables.
700   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
701 
702   if (TM.getOptLevel() > CodeGenOpt::None) {
703     addPass(createInferAddressSpacesPass());
704     addPass(createAMDGPUPromoteAlloca());
705 
706     if (EnableSROA)
707       addPass(createSROAPass());
708 
709     if (EnableScalarIRPasses)
710       addStraightLineScalarOptimizationPasses();
711 
712     if (EnableAMDGPUAliasAnalysis) {
713       addPass(createAMDGPUAAWrapperPass());
714       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
715                                              AAResults &AAR) {
716         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
717           AAR.addAAResult(WrapperPass->getResult());
718         }));
719     }
720   }
721 
722   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
723     // TODO: May want to move later or split into an early and late one.
724     addPass(createAMDGPUCodeGenPreparePass());
725   }
726 
727   TargetPassConfig::addIRPasses();
728 
729   // EarlyCSE is not always strong enough to clean up what LSR produces. For
730   // example, GVN can combine
731   //
732   //   %0 = add %a, %b
733   //   %1 = add %b, %a
734   //
735   // and
736   //
737   //   %0 = shl nsw %a, 2
738   //   %1 = shl %a, 2
739   //
740   // but EarlyCSE can do neither of them.
741   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
742     addEarlyCSEOrGVNPass();
743 }
744 
745 void AMDGPUPassConfig::addCodeGenPrepare() {
746   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
747     addPass(createAMDGPUAnnotateKernelFeaturesPass());
748 
749   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
750       EnableLowerKernelArguments)
751     addPass(createAMDGPULowerKernelArgumentsPass());
752 
753   addPass(&AMDGPUPerfHintAnalysisID);
754 
755   TargetPassConfig::addCodeGenPrepare();
756 
757   if (EnableLoadStoreVectorizer)
758     addPass(createLoadStoreVectorizerPass());
759 }
760 
761 bool AMDGPUPassConfig::addPreISel() {
762   addPass(createLowerSwitchPass());
763   addPass(createFlattenCFGPass());
764   return false;
765 }
766 
767 bool AMDGPUPassConfig::addInstSelector() {
768   // Defer the verifier until FinalizeISel.
769   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
770   return false;
771 }
772 
773 bool AMDGPUPassConfig::addGCPasses() {
774   // Do nothing. GC is not supported.
775   return false;
776 }
777 
778 //===----------------------------------------------------------------------===//
779 // R600 Pass Setup
780 //===----------------------------------------------------------------------===//
781 
782 bool R600PassConfig::addPreISel() {
783   AMDGPUPassConfig::addPreISel();
784 
785   if (EnableR600StructurizeCFG)
786     addPass(createStructurizeCFGPass());
787   return false;
788 }
789 
790 bool R600PassConfig::addInstSelector() {
791   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
792   return false;
793 }
794 
795 void R600PassConfig::addPreRegAlloc() {
796   addPass(createR600VectorRegMerger());
797 }
798 
799 void R600PassConfig::addPreSched2() {
800   addPass(createR600EmitClauseMarkers(), false);
801   if (EnableR600IfConvert)
802     addPass(&IfConverterID, false);
803   addPass(createR600ClauseMergePass(), false);
804 }
805 
806 void R600PassConfig::addPreEmitPass() {
807   addPass(createAMDGPUCFGStructurizerPass(), false);
808   addPass(createR600ExpandSpecialInstrsPass(), false);
809   addPass(&FinalizeMachineBundlesID, false);
810   addPass(createR600Packetizer(), false);
811   addPass(createR600ControlFlowFinalizer(), false);
812 }
813 
814 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
815   return new R600PassConfig(*this, PM);
816 }
817 
818 //===----------------------------------------------------------------------===//
819 // GCN Pass Setup
820 //===----------------------------------------------------------------------===//
821 
822 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
823   MachineSchedContext *C) const {
824   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
825   if (ST.enableSIScheduler())
826     return createSIMachineScheduler(C);
827   return createGCNMaxOccupancyMachineScheduler(C);
828 }
829 
830 bool GCNPassConfig::addPreISel() {
831   AMDGPUPassConfig::addPreISel();
832 
833   if (EnableAtomicOptimizations) {
834     addPass(createAMDGPUAtomicOptimizerPass());
835   }
836 
837   // FIXME: We need to run a pass to propagate the attributes when calls are
838   // supported.
839 
840   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
841   // regions formed by them.
842   addPass(&AMDGPUUnifyDivergentExitNodesID);
843   if (!LateCFGStructurize) {
844     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
845   }
846   addPass(createSinkingPass());
847   addPass(createAMDGPUAnnotateUniformValues());
848   if (!LateCFGStructurize) {
849     addPass(createSIAnnotateControlFlowPass());
850   }
851   addPass(createLCSSAPass());
852 
853   return false;
854 }
855 
856 void GCNPassConfig::addMachineSSAOptimization() {
857   TargetPassConfig::addMachineSSAOptimization();
858 
859   // We want to fold operands after PeepholeOptimizer has run (or as part of
860   // it), because it will eliminate extra copies making it easier to fold the
861   // real source operand. We want to eliminate dead instructions after, so that
862   // we see fewer uses of the copies. We then need to clean up the dead
863   // instructions leftover after the operands are folded as well.
864   //
865   // XXX - Can we get away without running DeadMachineInstructionElim again?
866   addPass(&SIFoldOperandsID);
867   if (EnableDPPCombine)
868     addPass(&GCNDPPCombineID);
869   addPass(&DeadMachineInstructionElimID);
870   addPass(&SILoadStoreOptimizerID);
871   if (EnableSDWAPeephole) {
872     addPass(&SIPeepholeSDWAID);
873     addPass(&EarlyMachineLICMID);
874     addPass(&MachineCSEID);
875     addPass(&SIFoldOperandsID);
876     addPass(&DeadMachineInstructionElimID);
877   }
878   addPass(createSIShrinkInstructionsPass());
879 }
880 
881 bool GCNPassConfig::addILPOpts() {
882   if (EnableEarlyIfConversion)
883     addPass(&EarlyIfConverterID);
884 
885   TargetPassConfig::addILPOpts();
886   return false;
887 }
888 
889 bool GCNPassConfig::addInstSelector() {
890   AMDGPUPassConfig::addInstSelector();
891   addPass(&SIFixSGPRCopiesID);
892   addPass(createSILowerI1CopiesPass());
893   addPass(createSIFixupVectorISelPass());
894   addPass(createSIAddIMGInitPass());
895   return false;
896 }
897 
898 bool GCNPassConfig::addIRTranslator() {
899   addPass(new IRTranslator());
900   return false;
901 }
902 
903 void GCNPassConfig::addPreLegalizeMachineIR() {
904   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
905   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
906   addPass(new Localizer());
907 }
908 
909 bool GCNPassConfig::addLegalizeMachineIR() {
910   addPass(new Legalizer());
911   return false;
912 }
913 
914 bool GCNPassConfig::addRegBankSelect() {
915   addPass(new RegBankSelect());
916   return false;
917 }
918 
919 bool GCNPassConfig::addGlobalInstructionSelect() {
920   addPass(new InstructionSelect());
921   return false;
922 }
923 
924 void GCNPassConfig::addPreRegAlloc() {
925   if (LateCFGStructurize) {
926     addPass(createAMDGPUMachineCFGStructurizerPass());
927   }
928   addPass(createSIWholeQuadModePass());
929 }
930 
931 void GCNPassConfig::addFastRegAlloc() {
932   // FIXME: We have to disable the verifier here because of PHIElimination +
933   // TwoAddressInstructions disabling it.
934 
935   // This must be run immediately after phi elimination and before
936   // TwoAddressInstructions, otherwise the processing of the tied operand of
937   // SI_ELSE will introduce a copy of the tied operand source after the else.
938   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
939 
940   // This must be run just after RegisterCoalescing.
941   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
942 
943   TargetPassConfig::addFastRegAlloc();
944 }
945 
946 void GCNPassConfig::addOptimizedRegAlloc() {
947   if (OptExecMaskPreRA) {
948     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
949     insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
950   } else {
951     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
952   }
953 
954   // This must be run immediately after phi elimination and before
955   // TwoAddressInstructions, otherwise the processing of the tied operand of
956   // SI_ELSE will introduce a copy of the tied operand source after the else.
957   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
958 
959   // This must be run just after RegisterCoalescing.
960   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
961 
962   if (EnableDCEInRA)
963     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
964 
965   TargetPassConfig::addOptimizedRegAlloc();
966 }
967 
968 bool GCNPassConfig::addPreRewrite() {
969   if (EnableRegReassign) {
970     addPass(&GCNNSAReassignID);
971     addPass(&GCNRegBankReassignID);
972   }
973   return true;
974 }
975 
976 void GCNPassConfig::addPostRegAlloc() {
977   addPass(&SIFixVGPRCopiesID);
978   if (getOptLevel() > CodeGenOpt::None)
979     addPass(&SIOptimizeExecMaskingID);
980   TargetPassConfig::addPostRegAlloc();
981 
982   // Equivalent of PEI for SGPRs.
983   addPass(&SILowerSGPRSpillsID);
984 }
985 
986 void GCNPassConfig::addPreSched2() {
987   addPass(&SIPostRABundlerID);
988 }
989 
990 void GCNPassConfig::addPreEmitPass() {
991   addPass(createSIMemoryLegalizerPass());
992   addPass(createSIInsertWaitcntsPass());
993   addPass(createSIShrinkInstructionsPass());
994   addPass(createSIModeRegisterPass());
995 
996   // The hazard recognizer that runs as part of the post-ra scheduler does not
997   // guarantee to be able handle all hazards correctly. This is because if there
998   // are multiple scheduling regions in a basic block, the regions are scheduled
999   // bottom up, so when we begin to schedule a region we don't know what
1000   // instructions were emitted directly before it.
1001   //
1002   // Here we add a stand-alone hazard recognizer pass which can handle all
1003   // cases.
1004   //
1005   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
1006   // be better for it to emit S_NOP <N> when possible.
1007   addPass(&PostRAHazardRecognizerID);
1008 
1009   addPass(&SIRemoveShortExecBranchesID);
1010   addPass(&SIInsertSkipsPassID);
1011   addPass(&BranchRelaxationPassID);
1012 }
1013 
1014 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1015   return new GCNPassConfig(*this, PM);
1016 }
1017 
1018 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1019   return new yaml::SIMachineFunctionInfo();
1020 }
1021 
1022 yaml::MachineFunctionInfo *
1023 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1024   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1025   return new yaml::SIMachineFunctionInfo(*MFI,
1026                                          *MF.getSubtarget().getRegisterInfo());
1027 }
1028 
1029 bool GCNTargetMachine::parseMachineFunctionInfo(
1030     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1031     SMDiagnostic &Error, SMRange &SourceRange) const {
1032   const yaml::SIMachineFunctionInfo &YamlMFI =
1033       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1034   MachineFunction &MF = PFS.MF;
1035   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1036 
1037   MFI->initializeBaseYamlFields(YamlMFI);
1038 
1039   auto parseRegister = [&](const yaml::StringValue &RegName, unsigned &RegVal) {
1040     if (parseNamedRegisterReference(PFS, RegVal, RegName.Value, Error)) {
1041       SourceRange = RegName.SourceRange;
1042       return true;
1043     }
1044 
1045     return false;
1046   };
1047 
1048   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1049     // Create a diagnostic for a the register string literal.
1050     const MemoryBuffer &Buffer =
1051         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1052     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1053                          RegName.Value.size(), SourceMgr::DK_Error,
1054                          "incorrect register class for field", RegName.Value,
1055                          None, None);
1056     SourceRange = RegName.SourceRange;
1057     return true;
1058   };
1059 
1060   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1061       parseRegister(YamlMFI.ScratchWaveOffsetReg, MFI->ScratchWaveOffsetReg) ||
1062       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1063       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1064     return true;
1065 
1066   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1067       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1068     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1069   }
1070 
1071   if (MFI->ScratchWaveOffsetReg != AMDGPU::SCRATCH_WAVE_OFFSET_REG &&
1072       !AMDGPU::SGPR_32RegClass.contains(MFI->ScratchWaveOffsetReg)) {
1073     return diagnoseRegisterClass(YamlMFI.ScratchWaveOffsetReg);
1074   }
1075 
1076   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1077       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1078     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1079   }
1080 
1081   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1082       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1083     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1084   }
1085 
1086   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1087                                    const TargetRegisterClass &RC,
1088                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1089                                    unsigned SystemSGPRs) {
1090     // Skip parsing if it's not present.
1091     if (!A)
1092       return false;
1093 
1094     if (A->IsRegister) {
1095       unsigned Reg;
1096       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1097         SourceRange = A->RegisterName.SourceRange;
1098         return true;
1099       }
1100       if (!RC.contains(Reg))
1101         return diagnoseRegisterClass(A->RegisterName);
1102       Arg = ArgDescriptor::createRegister(Reg);
1103     } else
1104       Arg = ArgDescriptor::createStack(A->StackOffset);
1105     // Check and apply the optional mask.
1106     if (A->Mask)
1107       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1108 
1109     MFI->NumUserSGPRs += UserSGPRs;
1110     MFI->NumSystemSGPRs += SystemSGPRs;
1111     return false;
1112   };
1113 
1114   if (YamlMFI.ArgInfo &&
1115       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1116                              AMDGPU::SGPR_128RegClass,
1117                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1118        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1119                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1120                              2, 0) ||
1121        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1122                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1123        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1124                              AMDGPU::SReg_64RegClass,
1125                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1126        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1127                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1128                              2, 0) ||
1129        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1130                              AMDGPU::SReg_64RegClass,
1131                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1132        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1133                              AMDGPU::SGPR_32RegClass,
1134                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1135        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1136                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1137                              0, 1) ||
1138        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1139                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1140                              0, 1) ||
1141        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1142                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1143                              0, 1) ||
1144        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1145                              AMDGPU::SGPR_32RegClass,
1146                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1147        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1148                              AMDGPU::SGPR_32RegClass,
1149                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1150        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1151                              AMDGPU::SReg_64RegClass,
1152                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1153        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1154                              AMDGPU::SReg_64RegClass,
1155                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1156        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1157                              AMDGPU::VGPR_32RegClass,
1158                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1159        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1160                              AMDGPU::VGPR_32RegClass,
1161                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1162        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1163                              AMDGPU::VGPR_32RegClass,
1164                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1165     return true;
1166 
1167   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1168   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1169   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1170   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1171   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1172   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1173 
1174   return false;
1175 }
1176