1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUInstructionSelector.h"
20 #include "AMDGPULegalizerInfo.h"
21 #include "AMDGPUMacroFusion.h"
22 #include "AMDGPUTargetObjectFile.h"
23 #include "AMDGPUTargetTransformInfo.h"
24 #include "GCNIterativeScheduler.h"
25 #include "GCNSchedStrategy.h"
26 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineFunctionInfo.h"
29 #include "SIMachineScheduler.h"
30 #include "TargetInfo/AMDGPUTargetInfo.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/Localizer.h"
35 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
36 #include "llvm/CodeGen/MIRParser/MIParser.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/TargetPassConfig.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/LegacyPassManager.h"
42 #include "llvm/InitializePasses.h"
43 #include "llvm/Pass.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Transforms/IPO.h"
49 #include "llvm/Transforms/IPO/AlwaysInliner.h"
50 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
51 #include "llvm/Transforms/Scalar.h"
52 #include "llvm/Transforms/Scalar/GVN.h"
53 #include "llvm/Transforms/Utils.h"
54 #include "llvm/Transforms/Vectorize.h"
55 #include <memory>
56 
57 using namespace llvm;
58 
59 static cl::opt<bool> EnableR600StructurizeCFG(
60   "r600-ir-structurize",
61   cl::desc("Use StructurizeCFG IR pass"),
62   cl::init(true));
63 
64 static cl::opt<bool> EnableSROA(
65   "amdgpu-sroa",
66   cl::desc("Run SROA after promote alloca pass"),
67   cl::ReallyHidden,
68   cl::init(true));
69 
70 static cl::opt<bool>
71 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
72                         cl::desc("Run early if-conversion"),
73                         cl::init(false));
74 
75 static cl::opt<bool>
76 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
77             cl::desc("Run pre-RA exec mask optimizations"),
78             cl::init(true));
79 
80 static cl::opt<bool> EnableR600IfConvert(
81   "r600-if-convert",
82   cl::desc("Use if conversion pass"),
83   cl::ReallyHidden,
84   cl::init(true));
85 
86 // Option to disable vectorizer for tests.
87 static cl::opt<bool> EnableLoadStoreVectorizer(
88   "amdgpu-load-store-vectorizer",
89   cl::desc("Enable load store vectorizer"),
90   cl::init(true),
91   cl::Hidden);
92 
93 // Option to control global loads scalarization
94 static cl::opt<bool> ScalarizeGlobal(
95   "amdgpu-scalarize-global-loads",
96   cl::desc("Enable global load scalarization"),
97   cl::init(true),
98   cl::Hidden);
99 
100 // Option to run internalize pass.
101 static cl::opt<bool> InternalizeSymbols(
102   "amdgpu-internalize-symbols",
103   cl::desc("Enable elimination of non-kernel functions and unused globals"),
104   cl::init(false),
105   cl::Hidden);
106 
107 // Option to inline all early.
108 static cl::opt<bool> EarlyInlineAll(
109   "amdgpu-early-inline-all",
110   cl::desc("Inline all functions early"),
111   cl::init(false),
112   cl::Hidden);
113 
114 static cl::opt<bool> EnableSDWAPeephole(
115   "amdgpu-sdwa-peephole",
116   cl::desc("Enable SDWA peepholer"),
117   cl::init(true));
118 
119 static cl::opt<bool> EnableDPPCombine(
120   "amdgpu-dpp-combine",
121   cl::desc("Enable DPP combiner"),
122   cl::init(true));
123 
124 // Enable address space based alias analysis
125 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
126   cl::desc("Enable AMDGPU Alias Analysis"),
127   cl::init(true));
128 
129 // Option to run late CFG structurizer
130 static cl::opt<bool, true> LateCFGStructurize(
131   "amdgpu-late-structurize",
132   cl::desc("Enable late CFG structurization"),
133   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
134   cl::Hidden);
135 
136 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
137   "amdgpu-function-calls",
138   cl::desc("Enable AMDGPU function call support"),
139   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
140   cl::init(true),
141   cl::Hidden);
142 
143 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
144   "amdgpu-fixed-function-abi",
145   cl::desc("Enable all implicit function arguments"),
146   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
147   cl::init(false),
148   cl::Hidden);
149 
150 // Enable lib calls simplifications
151 static cl::opt<bool> EnableLibCallSimplify(
152   "amdgpu-simplify-libcall",
153   cl::desc("Enable amdgpu library simplifications"),
154   cl::init(true),
155   cl::Hidden);
156 
157 static cl::opt<bool> EnableLowerKernelArguments(
158   "amdgpu-ir-lower-kernel-arguments",
159   cl::desc("Lower kernel argument loads in IR pass"),
160   cl::init(true),
161   cl::Hidden);
162 
163 static cl::opt<bool> EnableRegReassign(
164   "amdgpu-reassign-regs",
165   cl::desc("Enable register reassign optimizations on gfx10+"),
166   cl::init(true),
167   cl::Hidden);
168 
169 // Enable atomic optimization
170 static cl::opt<bool> EnableAtomicOptimizations(
171   "amdgpu-atomic-optimizations",
172   cl::desc("Enable atomic optimizations"),
173   cl::init(false),
174   cl::Hidden);
175 
176 // Enable Mode register optimization
177 static cl::opt<bool> EnableSIModeRegisterPass(
178   "amdgpu-mode-register",
179   cl::desc("Enable mode register pass"),
180   cl::init(true),
181   cl::Hidden);
182 
183 // Option is used in lit tests to prevent deadcoding of patterns inspected.
184 static cl::opt<bool>
185 EnableDCEInRA("amdgpu-dce-in-ra",
186     cl::init(true), cl::Hidden,
187     cl::desc("Enable machine DCE inside regalloc"));
188 
189 static cl::opt<bool> EnableScalarIRPasses(
190   "amdgpu-scalar-ir-passes",
191   cl::desc("Enable scalar IR passes"),
192   cl::init(true),
193   cl::Hidden);
194 
195 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
196   // Register the target
197   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
198   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
199 
200   PassRegistry *PR = PassRegistry::getPassRegistry();
201   initializeR600ClauseMergePassPass(*PR);
202   initializeR600ControlFlowFinalizerPass(*PR);
203   initializeR600PacketizerPass(*PR);
204   initializeR600ExpandSpecialInstrsPassPass(*PR);
205   initializeR600VectorRegMergerPass(*PR);
206   initializeGlobalISel(*PR);
207   initializeAMDGPUDAGToDAGISelPass(*PR);
208   initializeGCNDPPCombinePass(*PR);
209   initializeSILowerI1CopiesPass(*PR);
210   initializeSILowerSGPRSpillsPass(*PR);
211   initializeSIFixSGPRCopiesPass(*PR);
212   initializeSIFixVGPRCopiesPass(*PR);
213   initializeSIFixupVectorISelPass(*PR);
214   initializeSIFoldOperandsPass(*PR);
215   initializeSIPeepholeSDWAPass(*PR);
216   initializeSIShrinkInstructionsPass(*PR);
217   initializeSIOptimizeExecMaskingPreRAPass(*PR);
218   initializeSILoadStoreOptimizerPass(*PR);
219   initializeAMDGPUFixFunctionBitcastsPass(*PR);
220   initializeAMDGPUAlwaysInlinePass(*PR);
221   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
222   initializeAMDGPUAnnotateUniformValuesPass(*PR);
223   initializeAMDGPUArgumentUsageInfoPass(*PR);
224   initializeAMDGPUAtomicOptimizerPass(*PR);
225   initializeAMDGPULowerKernelArgumentsPass(*PR);
226   initializeAMDGPULowerKernelAttributesPass(*PR);
227   initializeAMDGPULowerIntrinsicsPass(*PR);
228   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
229   initializeAMDGPUPostLegalizerCombinerPass(*PR);
230   initializeAMDGPUPreLegalizerCombinerPass(*PR);
231   initializeAMDGPUPromoteAllocaPass(*PR);
232   initializeAMDGPUCodeGenPreparePass(*PR);
233   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
234   initializeAMDGPUPropagateAttributesLatePass(*PR);
235   initializeAMDGPURewriteOutArgumentsPass(*PR);
236   initializeAMDGPUUnifyMetadataPass(*PR);
237   initializeSIAnnotateControlFlowPass(*PR);
238   initializeSIInsertWaitcntsPass(*PR);
239   initializeSIModeRegisterPass(*PR);
240   initializeSIWholeQuadModePass(*PR);
241   initializeSILowerControlFlowPass(*PR);
242   initializeSIRemoveShortExecBranchesPass(*PR);
243   initializeSIPreEmitPeepholePass(*PR);
244   initializeSIInsertSkipsPass(*PR);
245   initializeSIMemoryLegalizerPass(*PR);
246   initializeSIOptimizeExecMaskingPass(*PR);
247   initializeSIPreAllocateWWMRegsPass(*PR);
248   initializeSIFormMemoryClausesPass(*PR);
249   initializeSIPostRABundlerPass(*PR);
250   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
251   initializeAMDGPUAAWrapperPassPass(*PR);
252   initializeAMDGPUExternalAAWrapperPass(*PR);
253   initializeAMDGPUUseNativeCallsPass(*PR);
254   initializeAMDGPUSimplifyLibCallsPass(*PR);
255   initializeAMDGPUInlinerPass(*PR);
256   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
257   initializeGCNRegBankReassignPass(*PR);
258   initializeGCNNSAReassignPass(*PR);
259   initializeSIAddIMGInitPass(*PR);
260 }
261 
262 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
263   return std::make_unique<AMDGPUTargetObjectFile>();
264 }
265 
266 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
267   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
268 }
269 
270 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
271   return new SIScheduleDAGMI(C);
272 }
273 
274 static ScheduleDAGInstrs *
275 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
276   ScheduleDAGMILive *DAG =
277     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
278   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
279   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
280   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
281   return DAG;
282 }
283 
284 static ScheduleDAGInstrs *
285 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
286   auto DAG = new GCNIterativeScheduler(C,
287     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
288   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
289   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
290   return DAG;
291 }
292 
293 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
294   return new GCNIterativeScheduler(C,
295     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
296 }
297 
298 static ScheduleDAGInstrs *
299 createIterativeILPMachineScheduler(MachineSchedContext *C) {
300   auto DAG = new GCNIterativeScheduler(C,
301     GCNIterativeScheduler::SCHEDULE_ILP);
302   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
303   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
304   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
305   return DAG;
306 }
307 
308 static MachineSchedRegistry
309 R600SchedRegistry("r600", "Run R600's custom scheduler",
310                    createR600MachineScheduler);
311 
312 static MachineSchedRegistry
313 SISchedRegistry("si", "Run SI's custom scheduler",
314                 createSIMachineScheduler);
315 
316 static MachineSchedRegistry
317 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
318                              "Run GCN scheduler to maximize occupancy",
319                              createGCNMaxOccupancyMachineScheduler);
320 
321 static MachineSchedRegistry
322 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
323   "Run GCN scheduler to maximize occupancy (experimental)",
324   createIterativeGCNMaxOccupancyMachineScheduler);
325 
326 static MachineSchedRegistry
327 GCNMinRegSchedRegistry("gcn-minreg",
328   "Run GCN iterative scheduler for minimal register usage (experimental)",
329   createMinRegScheduler);
330 
331 static MachineSchedRegistry
332 GCNILPSchedRegistry("gcn-ilp",
333   "Run GCN iterative scheduler for ILP scheduling (experimental)",
334   createIterativeILPMachineScheduler);
335 
336 static StringRef computeDataLayout(const Triple &TT) {
337   if (TT.getArch() == Triple::r600) {
338     // 32-bit pointers.
339       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
340              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
341   }
342 
343   // 32-bit private, local, and region pointers. 64-bit global, constant and
344   // flat, non-integral buffer fat pointers.
345     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
346          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
347          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
348          "-ni:7";
349 }
350 
351 LLVM_READNONE
352 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
353   if (!GPU.empty())
354     return GPU;
355 
356   // Need to default to a target with flat support for HSA.
357   if (TT.getArch() == Triple::amdgcn)
358     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
359 
360   return "r600";
361 }
362 
363 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
364   // The AMDGPU toolchain only supports generating shared objects, so we
365   // must always use PIC.
366   return Reloc::PIC_;
367 }
368 
369 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
370                                          StringRef CPU, StringRef FS,
371                                          TargetOptions Options,
372                                          Optional<Reloc::Model> RM,
373                                          Optional<CodeModel::Model> CM,
374                                          CodeGenOpt::Level OptLevel)
375     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
376                         FS, Options, getEffectiveRelocModel(RM),
377                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
378       TLOF(createTLOF(getTargetTriple())) {
379   initAsmInfo();
380   if (TT.getArch() == Triple::amdgcn) {
381     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
382       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
383     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
384       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
385   }
386 }
387 
388 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
389 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
390 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
391 
392 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
393 
394 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
395   Attribute GPUAttr = F.getFnAttribute("target-cpu");
396   return GPUAttr.hasAttribute(Attribute::None) ?
397     getTargetCPU() : GPUAttr.getValueAsString();
398 }
399 
400 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
401   Attribute FSAttr = F.getFnAttribute("target-features");
402 
403   return FSAttr.hasAttribute(Attribute::None) ?
404     getTargetFeatureString() :
405     FSAttr.getValueAsString();
406 }
407 
408 /// Predicate for Internalize pass.
409 static bool mustPreserveGV(const GlobalValue &GV) {
410   if (const Function *F = dyn_cast<Function>(&GV))
411     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
412 
413   return !GV.use_empty();
414 }
415 
416 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
417   Builder.DivergentTarget = true;
418 
419   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
420   bool Internalize = InternalizeSymbols;
421   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
422   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
423   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
424 
425   if (EnableFunctionCalls) {
426     delete Builder.Inliner;
427     Builder.Inliner = createAMDGPUFunctionInliningPass();
428   }
429 
430   Builder.addExtension(
431     PassManagerBuilder::EP_ModuleOptimizerEarly,
432     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
433                                                legacy::PassManagerBase &PM) {
434       if (AMDGPUAA) {
435         PM.add(createAMDGPUAAWrapperPass());
436         PM.add(createAMDGPUExternalAAWrapperPass());
437       }
438       PM.add(createAMDGPUUnifyMetadataPass());
439       PM.add(createAMDGPUPrintfRuntimeBinding());
440       PM.add(createAMDGPUPropagateAttributesLatePass(this));
441       if (Internalize) {
442         PM.add(createInternalizePass(mustPreserveGV));
443         PM.add(createGlobalDCEPass());
444       }
445       if (EarlyInline)
446         PM.add(createAMDGPUAlwaysInlinePass(false));
447   });
448 
449   const auto &Opt = Options;
450   Builder.addExtension(
451     PassManagerBuilder::EP_EarlyAsPossible,
452     [AMDGPUAA, LibCallSimplify, &Opt, this](const PassManagerBuilder &,
453                                             legacy::PassManagerBase &PM) {
454       if (AMDGPUAA) {
455         PM.add(createAMDGPUAAWrapperPass());
456         PM.add(createAMDGPUExternalAAWrapperPass());
457       }
458       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
459       PM.add(llvm::createAMDGPUUseNativeCallsPass());
460       if (LibCallSimplify)
461         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt, this));
462   });
463 
464   Builder.addExtension(
465     PassManagerBuilder::EP_CGSCCOptimizerLate,
466     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
467       // Add infer address spaces pass to the opt pipeline after inlining
468       // but before SROA to increase SROA opportunities.
469       PM.add(createInferAddressSpacesPass());
470 
471       // This should run after inlining to have any chance of doing anything,
472       // and before other cleanup optimizations.
473       PM.add(createAMDGPULowerKernelAttributesPass());
474   });
475 }
476 
477 //===----------------------------------------------------------------------===//
478 // R600 Target Machine (R600 -> Cayman)
479 //===----------------------------------------------------------------------===//
480 
481 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
482                                      StringRef CPU, StringRef FS,
483                                      TargetOptions Options,
484                                      Optional<Reloc::Model> RM,
485                                      Optional<CodeModel::Model> CM,
486                                      CodeGenOpt::Level OL, bool JIT)
487     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
488   setRequiresStructuredCFG(true);
489 
490   // Override the default since calls aren't supported for r600.
491   if (EnableFunctionCalls &&
492       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
493     EnableFunctionCalls = false;
494 }
495 
496 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
497   const Function &F) const {
498   StringRef GPU = getGPUName(F);
499   StringRef FS = getFeatureString(F);
500 
501   SmallString<128> SubtargetKey(GPU);
502   SubtargetKey.append(FS);
503 
504   auto &I = SubtargetMap[SubtargetKey];
505   if (!I) {
506     // This needs to be done before we create a new subtarget since any
507     // creation will depend on the TM and the code generation flags on the
508     // function that reside in TargetOptions.
509     resetTargetOptions(F);
510     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
511   }
512 
513   return I.get();
514 }
515 
516 TargetTransformInfo
517 R600TargetMachine::getTargetTransformInfo(const Function &F) {
518   return TargetTransformInfo(R600TTIImpl(this, F));
519 }
520 
521 //===----------------------------------------------------------------------===//
522 // GCN Target Machine (SI+)
523 //===----------------------------------------------------------------------===//
524 
525 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
526                                    StringRef CPU, StringRef FS,
527                                    TargetOptions Options,
528                                    Optional<Reloc::Model> RM,
529                                    Optional<CodeModel::Model> CM,
530                                    CodeGenOpt::Level OL, bool JIT)
531     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
532 
533 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
534   StringRef GPU = getGPUName(F);
535   StringRef FS = getFeatureString(F);
536 
537   SmallString<128> SubtargetKey(GPU);
538   SubtargetKey.append(FS);
539 
540   auto &I = SubtargetMap[SubtargetKey];
541   if (!I) {
542     // This needs to be done before we create a new subtarget since any
543     // creation will depend on the TM and the code generation flags on the
544     // function that reside in TargetOptions.
545     resetTargetOptions(F);
546     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
547   }
548 
549   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
550 
551   return I.get();
552 }
553 
554 TargetTransformInfo
555 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
556   return TargetTransformInfo(GCNTTIImpl(this, F));
557 }
558 
559 //===----------------------------------------------------------------------===//
560 // AMDGPU Pass Setup
561 //===----------------------------------------------------------------------===//
562 
563 namespace {
564 
565 class AMDGPUPassConfig : public TargetPassConfig {
566 public:
567   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
568     : TargetPassConfig(TM, PM) {
569     // Exceptions and StackMaps are not supported, so these passes will never do
570     // anything.
571     disablePass(&StackMapLivenessID);
572     disablePass(&FuncletLayoutID);
573   }
574 
575   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
576     return getTM<AMDGPUTargetMachine>();
577   }
578 
579   ScheduleDAGInstrs *
580   createMachineScheduler(MachineSchedContext *C) const override {
581     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
582     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
583     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
584     return DAG;
585   }
586 
587   void addEarlyCSEOrGVNPass();
588   void addStraightLineScalarOptimizationPasses();
589   void addIRPasses() override;
590   void addCodeGenPrepare() override;
591   bool addPreISel() override;
592   bool addInstSelector() override;
593   bool addGCPasses() override;
594 
595   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
596 };
597 
598 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
599   return getStandardCSEConfigForOpt(TM->getOptLevel());
600 }
601 
602 class R600PassConfig final : public AMDGPUPassConfig {
603 public:
604   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
605     : AMDGPUPassConfig(TM, PM) {}
606 
607   ScheduleDAGInstrs *createMachineScheduler(
608     MachineSchedContext *C) const override {
609     return createR600MachineScheduler(C);
610   }
611 
612   bool addPreISel() override;
613   bool addInstSelector() override;
614   void addPreRegAlloc() override;
615   void addPreSched2() override;
616   void addPreEmitPass() override;
617 };
618 
619 class GCNPassConfig final : public AMDGPUPassConfig {
620 public:
621   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
622     : AMDGPUPassConfig(TM, PM) {
623     // It is necessary to know the register usage of the entire call graph.  We
624     // allow calls without EnableAMDGPUFunctionCalls if they are marked
625     // noinline, so this is always required.
626     setRequiresCodeGenSCCOrder(true);
627   }
628 
629   GCNTargetMachine &getGCNTargetMachine() const {
630     return getTM<GCNTargetMachine>();
631   }
632 
633   ScheduleDAGInstrs *
634   createMachineScheduler(MachineSchedContext *C) const override;
635 
636   bool addPreISel() override;
637   void addMachineSSAOptimization() override;
638   bool addILPOpts() override;
639   bool addInstSelector() override;
640   bool addIRTranslator() override;
641   void addPreLegalizeMachineIR() override;
642   bool addLegalizeMachineIR() override;
643   void addPreRegBankSelect() override;
644   bool addRegBankSelect() override;
645   bool addGlobalInstructionSelect() override;
646   void addFastRegAlloc() override;
647   void addOptimizedRegAlloc() override;
648   void addPreRegAlloc() override;
649   bool addPreRewrite() override;
650   void addPostRegAlloc() override;
651   void addPreSched2() override;
652   void addPreEmitPass() override;
653 };
654 
655 } // end anonymous namespace
656 
657 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
658   if (getOptLevel() == CodeGenOpt::Aggressive)
659     addPass(createGVNPass());
660   else
661     addPass(createEarlyCSEPass());
662 }
663 
664 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
665   addPass(createLICMPass());
666   addPass(createSeparateConstOffsetFromGEPPass());
667   addPass(createSpeculativeExecutionPass());
668   // ReassociateGEPs exposes more opportunites for SLSR. See
669   // the example in reassociate-geps-and-slsr.ll.
670   addPass(createStraightLineStrengthReducePass());
671   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
672   // EarlyCSE can reuse.
673   addEarlyCSEOrGVNPass();
674   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
675   addPass(createNaryReassociatePass());
676   // NaryReassociate on GEPs creates redundant common expressions, so run
677   // EarlyCSE after it.
678   addPass(createEarlyCSEPass());
679 }
680 
681 void AMDGPUPassConfig::addIRPasses() {
682   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
683 
684   // There is no reason to run these.
685   disablePass(&StackMapLivenessID);
686   disablePass(&FuncletLayoutID);
687   disablePass(&PatchableFunctionID);
688 
689   addPass(createAMDGPUPrintfRuntimeBinding());
690 
691   // This must occur before inlining, as the inliner will not look through
692   // bitcast calls.
693   addPass(createAMDGPUFixFunctionBitcastsPass());
694 
695   // A call to propagate attributes pass in the backend in case opt was not run.
696   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
697 
698   addPass(createAtomicExpandPass());
699 
700 
701   addPass(createAMDGPULowerIntrinsicsPass());
702 
703   // Function calls are not supported, so make sure we inline everything.
704   addPass(createAMDGPUAlwaysInlinePass());
705   addPass(createAlwaysInlinerLegacyPass());
706   // We need to add the barrier noop pass, otherwise adding the function
707   // inlining pass will cause all of the PassConfigs passes to be run
708   // one function at a time, which means if we have a nodule with two
709   // functions, then we will generate code for the first function
710   // without ever running any passes on the second.
711   addPass(createBarrierNoopPass());
712 
713   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
714   if (TM.getTargetTriple().getArch() == Triple::r600)
715     addPass(createR600OpenCLImageTypeLoweringPass());
716 
717   // Replace OpenCL enqueued block function pointers with global variables.
718   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
719 
720   if (TM.getOptLevel() > CodeGenOpt::None) {
721     addPass(createInferAddressSpacesPass());
722     addPass(createAMDGPUPromoteAlloca());
723 
724     if (EnableSROA)
725       addPass(createSROAPass());
726 
727     if (EnableScalarIRPasses)
728       addStraightLineScalarOptimizationPasses();
729 
730     if (EnableAMDGPUAliasAnalysis) {
731       addPass(createAMDGPUAAWrapperPass());
732       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
733                                              AAResults &AAR) {
734         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
735           AAR.addAAResult(WrapperPass->getResult());
736         }));
737     }
738   }
739 
740   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
741     // TODO: May want to move later or split into an early and late one.
742     addPass(createAMDGPUCodeGenPreparePass());
743   }
744 
745   TargetPassConfig::addIRPasses();
746 
747   // EarlyCSE is not always strong enough to clean up what LSR produces. For
748   // example, GVN can combine
749   //
750   //   %0 = add %a, %b
751   //   %1 = add %b, %a
752   //
753   // and
754   //
755   //   %0 = shl nsw %a, 2
756   //   %1 = shl %a, 2
757   //
758   // but EarlyCSE can do neither of them.
759   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
760     addEarlyCSEOrGVNPass();
761 }
762 
763 void AMDGPUPassConfig::addCodeGenPrepare() {
764   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
765     addPass(createAMDGPUAnnotateKernelFeaturesPass());
766 
767   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
768       EnableLowerKernelArguments)
769     addPass(createAMDGPULowerKernelArgumentsPass());
770 
771   addPass(&AMDGPUPerfHintAnalysisID);
772 
773   TargetPassConfig::addCodeGenPrepare();
774 
775   if (EnableLoadStoreVectorizer)
776     addPass(createLoadStoreVectorizerPass());
777 }
778 
779 bool AMDGPUPassConfig::addPreISel() {
780   addPass(createLowerSwitchPass());
781   addPass(createFlattenCFGPass());
782   return false;
783 }
784 
785 bool AMDGPUPassConfig::addInstSelector() {
786   // Defer the verifier until FinalizeISel.
787   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
788   return false;
789 }
790 
791 bool AMDGPUPassConfig::addGCPasses() {
792   // Do nothing. GC is not supported.
793   return false;
794 }
795 
796 //===----------------------------------------------------------------------===//
797 // R600 Pass Setup
798 //===----------------------------------------------------------------------===//
799 
800 bool R600PassConfig::addPreISel() {
801   AMDGPUPassConfig::addPreISel();
802 
803   if (EnableR600StructurizeCFG)
804     addPass(createStructurizeCFGPass());
805   return false;
806 }
807 
808 bool R600PassConfig::addInstSelector() {
809   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
810   return false;
811 }
812 
813 void R600PassConfig::addPreRegAlloc() {
814   addPass(createR600VectorRegMerger());
815 }
816 
817 void R600PassConfig::addPreSched2() {
818   addPass(createR600EmitClauseMarkers(), false);
819   if (EnableR600IfConvert)
820     addPass(&IfConverterID, false);
821   addPass(createR600ClauseMergePass(), false);
822 }
823 
824 void R600PassConfig::addPreEmitPass() {
825   addPass(createAMDGPUCFGStructurizerPass(), false);
826   addPass(createR600ExpandSpecialInstrsPass(), false);
827   addPass(&FinalizeMachineBundlesID, false);
828   addPass(createR600Packetizer(), false);
829   addPass(createR600ControlFlowFinalizer(), false);
830 }
831 
832 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
833   return new R600PassConfig(*this, PM);
834 }
835 
836 //===----------------------------------------------------------------------===//
837 // GCN Pass Setup
838 //===----------------------------------------------------------------------===//
839 
840 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
841   MachineSchedContext *C) const {
842   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
843   if (ST.enableSIScheduler())
844     return createSIMachineScheduler(C);
845   return createGCNMaxOccupancyMachineScheduler(C);
846 }
847 
848 bool GCNPassConfig::addPreISel() {
849   AMDGPUPassConfig::addPreISel();
850 
851   if (EnableAtomicOptimizations) {
852     addPass(createAMDGPUAtomicOptimizerPass());
853   }
854 
855   // FIXME: We need to run a pass to propagate the attributes when calls are
856   // supported.
857 
858   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
859   // regions formed by them.
860   addPass(&AMDGPUUnifyDivergentExitNodesID);
861   if (!LateCFGStructurize) {
862     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
863   }
864   addPass(createSinkingPass());
865   addPass(createAMDGPUAnnotateUniformValues());
866   if (!LateCFGStructurize) {
867     addPass(createSIAnnotateControlFlowPass());
868   }
869   addPass(createLCSSAPass());
870 
871   return false;
872 }
873 
874 void GCNPassConfig::addMachineSSAOptimization() {
875   TargetPassConfig::addMachineSSAOptimization();
876 
877   // We want to fold operands after PeepholeOptimizer has run (or as part of
878   // it), because it will eliminate extra copies making it easier to fold the
879   // real source operand. We want to eliminate dead instructions after, so that
880   // we see fewer uses of the copies. We then need to clean up the dead
881   // instructions leftover after the operands are folded as well.
882   //
883   // XXX - Can we get away without running DeadMachineInstructionElim again?
884   addPass(&SIFoldOperandsID);
885   if (EnableDPPCombine)
886     addPass(&GCNDPPCombineID);
887   addPass(&DeadMachineInstructionElimID);
888   addPass(&SILoadStoreOptimizerID);
889   if (EnableSDWAPeephole) {
890     addPass(&SIPeepholeSDWAID);
891     addPass(&EarlyMachineLICMID);
892     addPass(&MachineCSEID);
893     addPass(&SIFoldOperandsID);
894     addPass(&DeadMachineInstructionElimID);
895   }
896   addPass(createSIShrinkInstructionsPass());
897 }
898 
899 bool GCNPassConfig::addILPOpts() {
900   if (EnableEarlyIfConversion)
901     addPass(&EarlyIfConverterID);
902 
903   TargetPassConfig::addILPOpts();
904   return false;
905 }
906 
907 bool GCNPassConfig::addInstSelector() {
908   AMDGPUPassConfig::addInstSelector();
909   addPass(&SIFixSGPRCopiesID);
910   addPass(createSILowerI1CopiesPass());
911   addPass(createSIFixupVectorISelPass());
912   addPass(createSIAddIMGInitPass());
913   return false;
914 }
915 
916 bool GCNPassConfig::addIRTranslator() {
917   addPass(new IRTranslator());
918   return false;
919 }
920 
921 void GCNPassConfig::addPreLegalizeMachineIR() {
922   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
923   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
924   addPass(new Localizer());
925 }
926 
927 bool GCNPassConfig::addLegalizeMachineIR() {
928   addPass(new Legalizer());
929   return false;
930 }
931 
932 void GCNPassConfig::addPreRegBankSelect() {
933   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
934   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
935 }
936 
937 bool GCNPassConfig::addRegBankSelect() {
938   addPass(new RegBankSelect());
939   return false;
940 }
941 
942 bool GCNPassConfig::addGlobalInstructionSelect() {
943   addPass(new InstructionSelect());
944   return false;
945 }
946 
947 void GCNPassConfig::addPreRegAlloc() {
948   if (LateCFGStructurize) {
949     addPass(createAMDGPUMachineCFGStructurizerPass());
950   }
951   addPass(createSIWholeQuadModePass());
952 }
953 
954 void GCNPassConfig::addFastRegAlloc() {
955   // FIXME: We have to disable the verifier here because of PHIElimination +
956   // TwoAddressInstructions disabling it.
957 
958   // This must be run immediately after phi elimination and before
959   // TwoAddressInstructions, otherwise the processing of the tied operand of
960   // SI_ELSE will introduce a copy of the tied operand source after the else.
961   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
962 
963   // This must be run just after RegisterCoalescing.
964   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
965 
966   TargetPassConfig::addFastRegAlloc();
967 }
968 
969 void GCNPassConfig::addOptimizedRegAlloc() {
970   if (OptExecMaskPreRA) {
971     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
972     insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
973   } else {
974     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
975   }
976 
977   // This must be run immediately after phi elimination and before
978   // TwoAddressInstructions, otherwise the processing of the tied operand of
979   // SI_ELSE will introduce a copy of the tied operand source after the else.
980   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
981 
982   // This must be run just after RegisterCoalescing.
983   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
984 
985   if (EnableDCEInRA)
986     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
987 
988   TargetPassConfig::addOptimizedRegAlloc();
989 }
990 
991 bool GCNPassConfig::addPreRewrite() {
992   if (EnableRegReassign) {
993     addPass(&GCNNSAReassignID);
994     addPass(&GCNRegBankReassignID);
995   }
996   return true;
997 }
998 
999 void GCNPassConfig::addPostRegAlloc() {
1000   addPass(&SIFixVGPRCopiesID);
1001   if (getOptLevel() > CodeGenOpt::None)
1002     addPass(&SIOptimizeExecMaskingID);
1003   TargetPassConfig::addPostRegAlloc();
1004 
1005   // Equivalent of PEI for SGPRs.
1006   addPass(&SILowerSGPRSpillsID);
1007 }
1008 
1009 void GCNPassConfig::addPreSched2() {
1010   addPass(&SIPostRABundlerID);
1011 }
1012 
1013 void GCNPassConfig::addPreEmitPass() {
1014   addPass(createSIMemoryLegalizerPass());
1015   addPass(createSIInsertWaitcntsPass());
1016   addPass(createSIShrinkInstructionsPass());
1017   addPass(createSIModeRegisterPass());
1018 
1019   // The hazard recognizer that runs as part of the post-ra scheduler does not
1020   // guarantee to be able handle all hazards correctly. This is because if there
1021   // are multiple scheduling regions in a basic block, the regions are scheduled
1022   // bottom up, so when we begin to schedule a region we don't know what
1023   // instructions were emitted directly before it.
1024   //
1025   // Here we add a stand-alone hazard recognizer pass which can handle all
1026   // cases.
1027   //
1028   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
1029   // be better for it to emit S_NOP <N> when possible.
1030   addPass(&PostRAHazardRecognizerID);
1031 
1032   addPass(&SIRemoveShortExecBranchesID);
1033   addPass(&SIPreEmitPeepholeID);
1034   addPass(&SIInsertSkipsPassID);
1035   addPass(&BranchRelaxationPassID);
1036 }
1037 
1038 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1039   return new GCNPassConfig(*this, PM);
1040 }
1041 
1042 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1043   return new yaml::SIMachineFunctionInfo();
1044 }
1045 
1046 yaml::MachineFunctionInfo *
1047 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1048   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1049   return new yaml::SIMachineFunctionInfo(*MFI,
1050                                          *MF.getSubtarget().getRegisterInfo());
1051 }
1052 
1053 bool GCNTargetMachine::parseMachineFunctionInfo(
1054     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1055     SMDiagnostic &Error, SMRange &SourceRange) const {
1056   const yaml::SIMachineFunctionInfo &YamlMFI =
1057       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1058   MachineFunction &MF = PFS.MF;
1059   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1060 
1061   MFI->initializeBaseYamlFields(YamlMFI);
1062 
1063   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1064     // FIXME: Update parseNamedRegsiterReference to take a Register.
1065     unsigned TempReg;
1066     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1067       SourceRange = RegName.SourceRange;
1068       return true;
1069     }
1070     RegVal = TempReg;
1071 
1072     return false;
1073   };
1074 
1075   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1076     // Create a diagnostic for a the register string literal.
1077     const MemoryBuffer &Buffer =
1078         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1079     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1080                          RegName.Value.size(), SourceMgr::DK_Error,
1081                          "incorrect register class for field", RegName.Value,
1082                          None, None);
1083     SourceRange = RegName.SourceRange;
1084     return true;
1085   };
1086 
1087   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1088       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1089       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1090     return true;
1091 
1092   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1093       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1094     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1095   }
1096 
1097   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1098       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1099     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1100   }
1101 
1102   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1103       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1104     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1105   }
1106 
1107   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1108                                    const TargetRegisterClass &RC,
1109                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1110                                    unsigned SystemSGPRs) {
1111     // Skip parsing if it's not present.
1112     if (!A)
1113       return false;
1114 
1115     if (A->IsRegister) {
1116       unsigned Reg;
1117       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1118         SourceRange = A->RegisterName.SourceRange;
1119         return true;
1120       }
1121       if (!RC.contains(Reg))
1122         return diagnoseRegisterClass(A->RegisterName);
1123       Arg = ArgDescriptor::createRegister(Reg);
1124     } else
1125       Arg = ArgDescriptor::createStack(A->StackOffset);
1126     // Check and apply the optional mask.
1127     if (A->Mask)
1128       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1129 
1130     MFI->NumUserSGPRs += UserSGPRs;
1131     MFI->NumSystemSGPRs += SystemSGPRs;
1132     return false;
1133   };
1134 
1135   if (YamlMFI.ArgInfo &&
1136       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1137                              AMDGPU::SGPR_128RegClass,
1138                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1139        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1140                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1141                              2, 0) ||
1142        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1143                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1144        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1145                              AMDGPU::SReg_64RegClass,
1146                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1147        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1148                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1149                              2, 0) ||
1150        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1151                              AMDGPU::SReg_64RegClass,
1152                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1153        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1154                              AMDGPU::SGPR_32RegClass,
1155                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1156        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1157                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1158                              0, 1) ||
1159        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1160                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1161                              0, 1) ||
1162        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1163                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1164                              0, 1) ||
1165        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1166                              AMDGPU::SGPR_32RegClass,
1167                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1168        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1169                              AMDGPU::SGPR_32RegClass,
1170                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1171        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1172                              AMDGPU::SReg_64RegClass,
1173                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1174        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1175                              AMDGPU::SReg_64RegClass,
1176                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1177        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1178                              AMDGPU::VGPR_32RegClass,
1179                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1180        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1181                              AMDGPU::VGPR_32RegClass,
1182                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1183        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1184                              AMDGPU::VGPR_32RegClass,
1185                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1186     return true;
1187 
1188   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1189   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1190   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1191   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1192   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1193   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1194 
1195   return false;
1196 }
1197