1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUTargetObjectFile.h"
20 #include "AMDGPUTargetTransformInfo.h"
21 #include "GCNSchedStrategy.h"
22 #include "R600ISelLowering.h"
23 #include "R600InstrInfo.h"
24 #include "R600MachineScheduler.h"
25 #include "SIISelLowering.h"
26 #include "SIInstrInfo.h"
27 #include "SIMachineScheduler.h"
28 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/TargetPassConfig.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Transforms/IPO.h"
33 #include "llvm/Transforms/IPO/AlwaysInliner.h"
34 #include "llvm/Transforms/Scalar.h"
35 #include "llvm/Transforms/Scalar/GVN.h"
36 #include "llvm/Transforms/Vectorize.h"
37 
38 using namespace llvm;
39 
40 static cl::opt<bool> EnableR600StructurizeCFG(
41   "r600-ir-structurize",
42   cl::desc("Use StructurizeCFG IR pass"),
43   cl::init(true));
44 
45 static cl::opt<bool> EnableSROA(
46   "amdgpu-sroa",
47   cl::desc("Run SROA after promote alloca pass"),
48   cl::ReallyHidden,
49   cl::init(true));
50 
51 static cl::opt<bool> EnableR600IfConvert(
52   "r600-if-convert",
53   cl::desc("Use if conversion pass"),
54   cl::ReallyHidden,
55   cl::init(true));
56 
57 // Option to disable vectorizer for tests.
58 static cl::opt<bool> EnableLoadStoreVectorizer(
59   "amdgpu-load-store-vectorizer",
60   cl::desc("Enable load store vectorizer"),
61   cl::init(true),
62   cl::Hidden);
63 
64 extern "C" void LLVMInitializeAMDGPUTarget() {
65   // Register the target
66   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
67   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
68 
69   PassRegistry *PR = PassRegistry::getPassRegistry();
70   initializeSILowerI1CopiesPass(*PR);
71   initializeSIFixSGPRCopiesPass(*PR);
72   initializeSIFoldOperandsPass(*PR);
73   initializeSIShrinkInstructionsPass(*PR);
74   initializeSIFixControlFlowLiveIntervalsPass(*PR);
75   initializeSILoadStoreOptimizerPass(*PR);
76   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
77   initializeAMDGPUAnnotateUniformValuesPass(*PR);
78   initializeAMDGPUPromoteAllocaPass(*PR);
79   initializeAMDGPUCodeGenPreparePass(*PR);
80   initializeSIAnnotateControlFlowPass(*PR);
81   initializeSIInsertWaitsPass(*PR);
82   initializeSIWholeQuadModePass(*PR);
83   initializeSILowerControlFlowPass(*PR);
84   initializeSIInsertSkipsPass(*PR);
85   initializeSIDebuggerInsertNopsPass(*PR);
86   initializeSIOptimizeExecMaskingPass(*PR);
87 }
88 
89 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
90   return make_unique<AMDGPUTargetObjectFile>();
91 }
92 
93 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
94   return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
95 }
96 
97 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
98   return new SIScheduleDAGMI(C);
99 }
100 
101 static ScheduleDAGInstrs *
102 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
103   ScheduleDAGMILive *DAG =
104       new ScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
105 
106   const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(DAG->TII);
107   if (TII->enableClusterLoads())
108     DAG->addMutation(createLoadClusterDAGMutation(TII, DAG->TRI));
109 
110   if (TII->enableClusterStores())
111     DAG->addMutation(createStoreClusterDAGMutation(TII, DAG->TRI));
112 
113   return DAG;
114 }
115 
116 static MachineSchedRegistry
117 R600SchedRegistry("r600", "Run R600's custom scheduler",
118                    createR600MachineScheduler);
119 
120 static MachineSchedRegistry
121 SISchedRegistry("si", "Run SI's custom scheduler",
122                 createSIMachineScheduler);
123 
124 static MachineSchedRegistry
125 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
126                              "Run GCN scheduler to maximize occupancy",
127                              createGCNMaxOccupancyMachineScheduler);
128 
129 static StringRef computeDataLayout(const Triple &TT) {
130   if (TT.getArch() == Triple::r600) {
131     // 32-bit pointers.
132     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
133             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
134   }
135 
136   // 32-bit private, local, and region pointers. 64-bit global, constant and
137   // flat.
138   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
139          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
140          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
141 }
142 
143 LLVM_READNONE
144 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
145   if (!GPU.empty())
146     return GPU;
147 
148   // HSA only supports CI+, so change the default GPU to a CI for HSA.
149   if (TT.getArch() == Triple::amdgcn)
150     return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
151 
152   return "r600";
153 }
154 
155 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
156   // The AMDGPU toolchain only supports generating shared objects, so we
157   // must always use PIC.
158   return Reloc::PIC_;
159 }
160 
161 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
162                                          StringRef CPU, StringRef FS,
163                                          TargetOptions Options,
164                                          Optional<Reloc::Model> RM,
165                                          CodeModel::Model CM,
166                                          CodeGenOpt::Level OptLevel)
167   : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
168                       FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
169     TLOF(createTLOF(getTargetTriple())),
170     IntrinsicInfo() {
171   setRequiresStructuredCFG(true);
172   initAsmInfo();
173 }
174 
175 AMDGPUTargetMachine::~AMDGPUTargetMachine() { }
176 
177 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
178   Attribute GPUAttr = F.getFnAttribute("target-cpu");
179   return GPUAttr.hasAttribute(Attribute::None) ?
180     getTargetCPU() : GPUAttr.getValueAsString();
181 }
182 
183 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
184   Attribute FSAttr = F.getFnAttribute("target-features");
185 
186   return FSAttr.hasAttribute(Attribute::None) ?
187     getTargetFeatureString() :
188     FSAttr.getValueAsString();
189 }
190 
191 //===----------------------------------------------------------------------===//
192 // R600 Target Machine (R600 -> Cayman)
193 //===----------------------------------------------------------------------===//
194 
195 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
196                                      StringRef CPU, StringRef FS,
197                                      TargetOptions Options,
198                                      Optional<Reloc::Model> RM,
199                                      CodeModel::Model CM, CodeGenOpt::Level OL)
200   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
201 
202 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
203   const Function &F) const {
204   StringRef GPU = getGPUName(F);
205   StringRef FS = getFeatureString(F);
206 
207   SmallString<128> SubtargetKey(GPU);
208   SubtargetKey.append(FS);
209 
210   auto &I = SubtargetMap[SubtargetKey];
211   if (!I) {
212     // This needs to be done before we create a new subtarget since any
213     // creation will depend on the TM and the code generation flags on the
214     // function that reside in TargetOptions.
215     resetTargetOptions(F);
216     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
217   }
218 
219   return I.get();
220 }
221 
222 //===----------------------------------------------------------------------===//
223 // GCN Target Machine (SI+)
224 //===----------------------------------------------------------------------===//
225 
226 #ifdef LLVM_BUILD_GLOBAL_ISEL
227 namespace {
228 struct SIGISelActualAccessor : public GISelAccessor {
229   std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
230   const AMDGPUCallLowering *getCallLowering() const override {
231     return CallLoweringInfo.get();
232   }
233 };
234 } // End anonymous namespace.
235 #endif
236 
237 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
238                                    StringRef CPU, StringRef FS,
239                                    TargetOptions Options,
240                                    Optional<Reloc::Model> RM,
241                                    CodeModel::Model CM, CodeGenOpt::Level OL)
242   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
243 
244 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
245   StringRef GPU = getGPUName(F);
246   StringRef FS = getFeatureString(F);
247 
248   SmallString<128> SubtargetKey(GPU);
249   SubtargetKey.append(FS);
250 
251   auto &I = SubtargetMap[SubtargetKey];
252   if (!I) {
253     // This needs to be done before we create a new subtarget since any
254     // creation will depend on the TM and the code generation flags on the
255     // function that reside in TargetOptions.
256     resetTargetOptions(F);
257     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
258 
259 #ifndef LLVM_BUILD_GLOBAL_ISEL
260     GISelAccessor *GISel = new GISelAccessor();
261 #else
262     SIGISelActualAccessor *GISel = new SIGISelActualAccessor();
263     GISel->CallLoweringInfo.reset(
264       new AMDGPUCallLowering(*I->getTargetLowering()));
265 #endif
266 
267     I->setGISelAccessor(*GISel);
268   }
269 
270   return I.get();
271 }
272 
273 //===----------------------------------------------------------------------===//
274 // AMDGPU Pass Setup
275 //===----------------------------------------------------------------------===//
276 
277 namespace {
278 
279 class AMDGPUPassConfig : public TargetPassConfig {
280 public:
281   AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
282     : TargetPassConfig(TM, PM) {
283 
284     // Exceptions and StackMaps are not supported, so these passes will never do
285     // anything.
286     disablePass(&StackMapLivenessID);
287     disablePass(&FuncletLayoutID);
288   }
289 
290   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
291     return getTM<AMDGPUTargetMachine>();
292   }
293 
294   void addEarlyCSEOrGVNPass();
295   void addStraightLineScalarOptimizationPasses();
296   void addIRPasses() override;
297   void addCodeGenPrepare() override;
298   bool addPreISel() override;
299   bool addInstSelector() override;
300   bool addGCPasses() override;
301 };
302 
303 class R600PassConfig final : public AMDGPUPassConfig {
304 public:
305   R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
306     : AMDGPUPassConfig(TM, PM) { }
307 
308   ScheduleDAGInstrs *createMachineScheduler(
309     MachineSchedContext *C) const override {
310     return createR600MachineScheduler(C);
311   }
312 
313   bool addPreISel() override;
314   void addPreRegAlloc() override;
315   void addPreSched2() override;
316   void addPreEmitPass() override;
317 };
318 
319 class GCNPassConfig final : public AMDGPUPassConfig {
320 public:
321   GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
322     : AMDGPUPassConfig(TM, PM) { }
323 
324   GCNTargetMachine &getGCNTargetMachine() const {
325     return getTM<GCNTargetMachine>();
326   }
327 
328   ScheduleDAGInstrs *
329   createMachineScheduler(MachineSchedContext *C) const override;
330 
331   void addIRPasses() override;
332   bool addPreISel() override;
333   void addMachineSSAOptimization() override;
334   bool addInstSelector() override;
335 #ifdef LLVM_BUILD_GLOBAL_ISEL
336   bool addIRTranslator() override;
337   bool addLegalizeMachineIR() override;
338   bool addRegBankSelect() override;
339   bool addGlobalInstructionSelect() override;
340 #endif
341   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
342   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
343   void addPreRegAlloc() override;
344   void addPostRegAlloc() override;
345   void addPreSched2() override;
346   void addPreEmitPass() override;
347 };
348 
349 } // End of anonymous namespace
350 
351 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
352   return TargetIRAnalysis([this](const Function &F) {
353     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
354   });
355 }
356 
357 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
358   if (getOptLevel() == CodeGenOpt::Aggressive)
359     addPass(createGVNPass());
360   else
361     addPass(createEarlyCSEPass());
362 }
363 
364 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
365   addPass(createSeparateConstOffsetFromGEPPass());
366   addPass(createSpeculativeExecutionPass());
367   // ReassociateGEPs exposes more opportunites for SLSR. See
368   // the example in reassociate-geps-and-slsr.ll.
369   addPass(createStraightLineStrengthReducePass());
370   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
371   // EarlyCSE can reuse.
372   addEarlyCSEOrGVNPass();
373   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
374   addPass(createNaryReassociatePass());
375   // NaryReassociate on GEPs creates redundant common expressions, so run
376   // EarlyCSE after it.
377   addPass(createEarlyCSEPass());
378 }
379 
380 void AMDGPUPassConfig::addIRPasses() {
381   // There is no reason to run these.
382   disablePass(&StackMapLivenessID);
383   disablePass(&FuncletLayoutID);
384   disablePass(&PatchableFunctionID);
385 
386   // Function calls are not supported, so make sure we inline everything.
387   addPass(createAMDGPUAlwaysInlinePass());
388   addPass(createAlwaysInlinerLegacyPass());
389   // We need to add the barrier noop pass, otherwise adding the function
390   // inlining pass will cause all of the PassConfigs passes to be run
391   // one function at a time, which means if we have a nodule with two
392   // functions, then we will generate code for the first function
393   // without ever running any passes on the second.
394   addPass(createBarrierNoopPass());
395 
396   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
397   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
398 
399   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
400   if (TM.getOptLevel() > CodeGenOpt::None) {
401     addPass(createAMDGPUPromoteAlloca(&TM));
402 
403     if (EnableSROA)
404       addPass(createSROAPass());
405 
406     addStraightLineScalarOptimizationPasses();
407   }
408 
409   TargetPassConfig::addIRPasses();
410 
411   // EarlyCSE is not always strong enough to clean up what LSR produces. For
412   // example, GVN can combine
413   //
414   //   %0 = add %a, %b
415   //   %1 = add %b, %a
416   //
417   // and
418   //
419   //   %0 = shl nsw %a, 2
420   //   %1 = shl %a, 2
421   //
422   // but EarlyCSE can do neither of them.
423   if (getOptLevel() != CodeGenOpt::None)
424     addEarlyCSEOrGVNPass();
425 }
426 
427 void AMDGPUPassConfig::addCodeGenPrepare() {
428   TargetPassConfig::addCodeGenPrepare();
429 
430   if (EnableLoadStoreVectorizer)
431     addPass(createLoadStoreVectorizerPass());
432 }
433 
434 bool AMDGPUPassConfig::addPreISel() {
435   addPass(createFlattenCFGPass());
436   return false;
437 }
438 
439 bool AMDGPUPassConfig::addInstSelector() {
440   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));
441   return false;
442 }
443 
444 bool AMDGPUPassConfig::addGCPasses() {
445   // Do nothing. GC is not supported.
446   return false;
447 }
448 
449 //===----------------------------------------------------------------------===//
450 // R600 Pass Setup
451 //===----------------------------------------------------------------------===//
452 
453 bool R600PassConfig::addPreISel() {
454   AMDGPUPassConfig::addPreISel();
455 
456   if (EnableR600StructurizeCFG)
457     addPass(createStructurizeCFGPass());
458   return false;
459 }
460 
461 void R600PassConfig::addPreRegAlloc() {
462   addPass(createR600VectorRegMerger(*TM));
463 }
464 
465 void R600PassConfig::addPreSched2() {
466   addPass(createR600EmitClauseMarkers(), false);
467   if (EnableR600IfConvert)
468     addPass(&IfConverterID, false);
469   addPass(createR600ClauseMergePass(*TM), false);
470 }
471 
472 void R600PassConfig::addPreEmitPass() {
473   addPass(createAMDGPUCFGStructurizerPass(), false);
474   addPass(createR600ExpandSpecialInstrsPass(*TM), false);
475   addPass(&FinalizeMachineBundlesID, false);
476   addPass(createR600Packetizer(*TM), false);
477   addPass(createR600ControlFlowFinalizer(*TM), false);
478 }
479 
480 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
481   return new R600PassConfig(this, PM);
482 }
483 
484 //===----------------------------------------------------------------------===//
485 // GCN Pass Setup
486 //===----------------------------------------------------------------------===//
487 
488 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
489   MachineSchedContext *C) const {
490   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
491   if (ST.enableSIScheduler())
492     return createSIMachineScheduler(C);
493   return createGCNMaxOccupancyMachineScheduler(C);
494 }
495 
496 bool GCNPassConfig::addPreISel() {
497   AMDGPUPassConfig::addPreISel();
498 
499   // FIXME: We need to run a pass to propagate the attributes when calls are
500   // supported.
501   addPass(&AMDGPUAnnotateKernelFeaturesID);
502   addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
503   addPass(createSinkingPass());
504   addPass(createSITypeRewriter());
505   addPass(createAMDGPUAnnotateUniformValues());
506   addPass(createSIAnnotateControlFlowPass());
507 
508   return false;
509 }
510 
511 void GCNPassConfig::addMachineSSAOptimization() {
512   TargetPassConfig::addMachineSSAOptimization();
513 
514   // We want to fold operands after PeepholeOptimizer has run (or as part of
515   // it), because it will eliminate extra copies making it easier to fold the
516   // real source operand. We want to eliminate dead instructions after, so that
517   // we see fewer uses of the copies. We then need to clean up the dead
518   // instructions leftover after the operands are folded as well.
519   //
520   // XXX - Can we get away without running DeadMachineInstructionElim again?
521   addPass(&SIFoldOperandsID);
522   addPass(&DeadMachineInstructionElimID);
523   addPass(&SILoadStoreOptimizerID);
524 }
525 
526 void GCNPassConfig::addIRPasses() {
527   // TODO: May want to move later or split into an early and late one.
528   addPass(createAMDGPUCodeGenPreparePass(&getGCNTargetMachine()));
529 
530   AMDGPUPassConfig::addIRPasses();
531 }
532 
533 bool GCNPassConfig::addInstSelector() {
534   AMDGPUPassConfig::addInstSelector();
535   addPass(createSILowerI1CopiesPass());
536   addPass(&SIFixSGPRCopiesID);
537   return false;
538 }
539 
540 #ifdef LLVM_BUILD_GLOBAL_ISEL
541 bool GCNPassConfig::addIRTranslator() {
542   addPass(new IRTranslator());
543   return false;
544 }
545 
546 bool GCNPassConfig::addLegalizeMachineIR() {
547   return false;
548 }
549 
550 bool GCNPassConfig::addRegBankSelect() {
551   return false;
552 }
553 
554 bool GCNPassConfig::addGlobalInstructionSelect() {
555   return false;
556 }
557 #endif
558 
559 void GCNPassConfig::addPreRegAlloc() {
560   addPass(createSIShrinkInstructionsPass());
561   addPass(createSIWholeQuadModePass());
562 }
563 
564 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
565   // FIXME: We have to disable the verifier here because of PHIElimination +
566   // TwoAddressInstructions disabling it.
567 
568   // This must be run immediately after phi elimination and before
569   // TwoAddressInstructions, otherwise the processing of the tied operand of
570   // SI_ELSE will introduce a copy of the tied operand source after the else.
571   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
572 
573   TargetPassConfig::addFastRegAlloc(RegAllocPass);
574 }
575 
576 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
577   // This needs to be run directly before register allocation because earlier
578   // passes might recompute live intervals.
579   insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
580 
581   // This must be run immediately after phi elimination and before
582   // TwoAddressInstructions, otherwise the processing of the tied operand of
583   // SI_ELSE will introduce a copy of the tied operand source after the else.
584   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
585 
586   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
587 }
588 
589 void GCNPassConfig::addPostRegAlloc() {
590   addPass(&SIOptimizeExecMaskingID);
591   TargetPassConfig::addPostRegAlloc();
592 }
593 
594 void GCNPassConfig::addPreSched2() {
595 }
596 
597 void GCNPassConfig::addPreEmitPass() {
598   // The hazard recognizer that runs as part of the post-ra scheduler does not
599   // guarantee to be able handle all hazards correctly. This is because if there
600   // are multiple scheduling regions in a basic block, the regions are scheduled
601   // bottom up, so when we begin to schedule a region we don't know what
602   // instructions were emitted directly before it.
603   //
604   // Here we add a stand-alone hazard recognizer pass which can handle all
605   // cases.
606   addPass(&PostRAHazardRecognizerID);
607 
608   addPass(createSIInsertWaitsPass());
609   addPass(createSIShrinkInstructionsPass());
610   addPass(&SIInsertSkipsPassID);
611   addPass(createSIDebuggerInsertNopsPass());
612   addPass(&BranchRelaxationPassID);
613 }
614 
615 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
616   return new GCNPassConfig(this, PM);
617 }
618