1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600MachineScheduler.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIMachineScheduler.h"
27 #include "TargetInfo/AMDGPUTargetInfo.h"
28 #include "llvm/Analysis/CGSCCPassManager.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/Localizer.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MIRParser/MIParser.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/LegacyPassManager.h"
37 #include "llvm/IR/PassManager.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/Passes/PassBuilder.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Transforms/IPO.h"
42 #include "llvm/Transforms/IPO/AlwaysInliner.h"
43 #include "llvm/Transforms/IPO/GlobalDCE.h"
44 #include "llvm/Transforms/IPO/Internalize.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
49 #include "llvm/Transforms/Utils.h"
50 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
51 #include "llvm/Transforms/Vectorize.h"
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73             cl::desc("Run pre-RA exec mask optimizations"),
74             cl::init(true));
75 
76 static cl::opt<bool> EnableR600IfConvert(
77   "r600-if-convert",
78   cl::desc("Use if conversion pass"),
79   cl::ReallyHidden,
80   cl::init(true));
81 
82 // Option to disable vectorizer for tests.
83 static cl::opt<bool> EnableLoadStoreVectorizer(
84   "amdgpu-load-store-vectorizer",
85   cl::desc("Enable load store vectorizer"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to control global loads scalarization
90 static cl::opt<bool> ScalarizeGlobal(
91   "amdgpu-scalarize-global-loads",
92   cl::desc("Enable global load scalarization"),
93   cl::init(true),
94   cl::Hidden);
95 
96 // Option to run internalize pass.
97 static cl::opt<bool> InternalizeSymbols(
98   "amdgpu-internalize-symbols",
99   cl::desc("Enable elimination of non-kernel functions and unused globals"),
100   cl::init(false),
101   cl::Hidden);
102 
103 // Option to inline all early.
104 static cl::opt<bool> EarlyInlineAll(
105   "amdgpu-early-inline-all",
106   cl::desc("Inline all functions early"),
107   cl::init(false),
108   cl::Hidden);
109 
110 static cl::opt<bool> EnableSDWAPeephole(
111   "amdgpu-sdwa-peephole",
112   cl::desc("Enable SDWA peepholer"),
113   cl::init(true));
114 
115 static cl::opt<bool> EnableDPPCombine(
116   "amdgpu-dpp-combine",
117   cl::desc("Enable DPP combiner"),
118   cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122   cl::desc("Enable AMDGPU Alias Analysis"),
123   cl::init(true));
124 
125 // Option to run late CFG structurizer
126 static cl::opt<bool, true> LateCFGStructurize(
127   "amdgpu-late-structurize",
128   cl::desc("Enable late CFG structurization"),
129   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
130   cl::Hidden);
131 
132 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
133   "amdgpu-function-calls",
134   cl::desc("Enable AMDGPU function call support"),
135   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
136   cl::init(true),
137   cl::Hidden);
138 
139 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
140   "amdgpu-fixed-function-abi",
141   cl::desc("Enable all implicit function arguments"),
142   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
143   cl::init(false),
144   cl::Hidden);
145 
146 // Enable lib calls simplifications
147 static cl::opt<bool> EnableLibCallSimplify(
148   "amdgpu-simplify-libcall",
149   cl::desc("Enable amdgpu library simplifications"),
150   cl::init(true),
151   cl::Hidden);
152 
153 static cl::opt<bool> EnableLowerKernelArguments(
154   "amdgpu-ir-lower-kernel-arguments",
155   cl::desc("Lower kernel argument loads in IR pass"),
156   cl::init(true),
157   cl::Hidden);
158 
159 static cl::opt<bool> EnableRegReassign(
160   "amdgpu-reassign-regs",
161   cl::desc("Enable register reassign optimizations on gfx10+"),
162   cl::init(true),
163   cl::Hidden);
164 
165 // Enable atomic optimization
166 static cl::opt<bool> EnableAtomicOptimizations(
167   "amdgpu-atomic-optimizations",
168   cl::desc("Enable atomic optimizations"),
169   cl::init(false),
170   cl::Hidden);
171 
172 // Enable Mode register optimization
173 static cl::opt<bool> EnableSIModeRegisterPass(
174   "amdgpu-mode-register",
175   cl::desc("Enable mode register pass"),
176   cl::init(true),
177   cl::Hidden);
178 
179 // Option is used in lit tests to prevent deadcoding of patterns inspected.
180 static cl::opt<bool>
181 EnableDCEInRA("amdgpu-dce-in-ra",
182     cl::init(true), cl::Hidden,
183     cl::desc("Enable machine DCE inside regalloc"));
184 
185 static cl::opt<bool> EnableScalarIRPasses(
186   "amdgpu-scalar-ir-passes",
187   cl::desc("Enable scalar IR passes"),
188   cl::init(true),
189   cl::Hidden);
190 
191 static cl::opt<bool> EnableStructurizerWorkarounds(
192     "amdgpu-enable-structurizer-workarounds",
193     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
194     cl::Hidden);
195 
196 static cl::opt<bool, true> EnableLowerModuleLDS(
197     "amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"),
198     cl::location(AMDGPUTargetMachine::EnableLowerModuleLDS), cl::init(true),
199     cl::Hidden);
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFoldOperandsPass(*PR);
220   initializeSIPeepholeSDWAPass(*PR);
221   initializeSIShrinkInstructionsPass(*PR);
222   initializeSIOptimizeExecMaskingPreRAPass(*PR);
223   initializeSILoadStoreOptimizerPass(*PR);
224   initializeAMDGPUFixFunctionBitcastsPass(*PR);
225   initializeAMDGPUAlwaysInlinePass(*PR);
226   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
227   initializeAMDGPUAnnotateUniformValuesPass(*PR);
228   initializeAMDGPUArgumentUsageInfoPass(*PR);
229   initializeAMDGPUAtomicOptimizerPass(*PR);
230   initializeAMDGPULowerKernelArgumentsPass(*PR);
231   initializeAMDGPULowerKernelAttributesPass(*PR);
232   initializeAMDGPULowerIntrinsicsPass(*PR);
233   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
234   initializeAMDGPUPostLegalizerCombinerPass(*PR);
235   initializeAMDGPUPreLegalizerCombinerPass(*PR);
236   initializeAMDGPURegBankCombinerPass(*PR);
237   initializeAMDGPUPromoteAllocaPass(*PR);
238   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
239   initializeAMDGPUCodeGenPreparePass(*PR);
240   initializeAMDGPULateCodeGenPreparePass(*PR);
241   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
242   initializeAMDGPUPropagateAttributesLatePass(*PR);
243   initializeAMDGPULowerModuleLDSPass(*PR);
244   initializeAMDGPURewriteOutArgumentsPass(*PR);
245   initializeAMDGPUUnifyMetadataPass(*PR);
246   initializeSIAnnotateControlFlowPass(*PR);
247   initializeSIInsertHardClausesPass(*PR);
248   initializeSIInsertWaitcntsPass(*PR);
249   initializeSIModeRegisterPass(*PR);
250   initializeSIWholeQuadModePass(*PR);
251   initializeSILowerControlFlowPass(*PR);
252   initializeSIPreEmitPeepholePass(*PR);
253   initializeSILateBranchLoweringPass(*PR);
254   initializeSIMemoryLegalizerPass(*PR);
255   initializeSIOptimizeExecMaskingPass(*PR);
256   initializeSIPreAllocateWWMRegsPass(*PR);
257   initializeSIFormMemoryClausesPass(*PR);
258   initializeSIPostRABundlerPass(*PR);
259   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
260   initializeAMDGPUAAWrapperPassPass(*PR);
261   initializeAMDGPUExternalAAWrapperPass(*PR);
262   initializeAMDGPUUseNativeCallsPass(*PR);
263   initializeAMDGPUSimplifyLibCallsPass(*PR);
264   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
265   initializeGCNRegBankReassignPass(*PR);
266   initializeGCNNSAReassignPass(*PR);
267 }
268 
269 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
270   return std::make_unique<AMDGPUTargetObjectFile>();
271 }
272 
273 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
274   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
275 }
276 
277 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
278   return new SIScheduleDAGMI(C);
279 }
280 
281 static ScheduleDAGInstrs *
282 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
283   ScheduleDAGMILive *DAG =
284     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
285   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
286   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
287   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
288   return DAG;
289 }
290 
291 static ScheduleDAGInstrs *
292 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
293   auto DAG = new GCNIterativeScheduler(C,
294     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
295   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
296   return DAG;
297 }
298 
299 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
300   return new GCNIterativeScheduler(C,
301     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
302 }
303 
304 static ScheduleDAGInstrs *
305 createIterativeILPMachineScheduler(MachineSchedContext *C) {
306   auto DAG = new GCNIterativeScheduler(C,
307     GCNIterativeScheduler::SCHEDULE_ILP);
308   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
309   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
310   return DAG;
311 }
312 
313 static MachineSchedRegistry
314 R600SchedRegistry("r600", "Run R600's custom scheduler",
315                    createR600MachineScheduler);
316 
317 static MachineSchedRegistry
318 SISchedRegistry("si", "Run SI's custom scheduler",
319                 createSIMachineScheduler);
320 
321 static MachineSchedRegistry
322 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
323                              "Run GCN scheduler to maximize occupancy",
324                              createGCNMaxOccupancyMachineScheduler);
325 
326 static MachineSchedRegistry
327 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
328   "Run GCN scheduler to maximize occupancy (experimental)",
329   createIterativeGCNMaxOccupancyMachineScheduler);
330 
331 static MachineSchedRegistry
332 GCNMinRegSchedRegistry("gcn-minreg",
333   "Run GCN iterative scheduler for minimal register usage (experimental)",
334   createMinRegScheduler);
335 
336 static MachineSchedRegistry
337 GCNILPSchedRegistry("gcn-ilp",
338   "Run GCN iterative scheduler for ILP scheduling (experimental)",
339   createIterativeILPMachineScheduler);
340 
341 static StringRef computeDataLayout(const Triple &TT) {
342   if (TT.getArch() == Triple::r600) {
343     // 32-bit pointers.
344     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
345            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
346   }
347 
348   // 32-bit private, local, and region pointers. 64-bit global, constant and
349   // flat, non-integral buffer fat pointers.
350   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
351          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
352          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
353          "-ni:7";
354 }
355 
356 LLVM_READNONE
357 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
358   if (!GPU.empty())
359     return GPU;
360 
361   // Need to default to a target with flat support for HSA.
362   if (TT.getArch() == Triple::amdgcn)
363     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
364 
365   return "r600";
366 }
367 
368 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
369   // The AMDGPU toolchain only supports generating shared objects, so we
370   // must always use PIC.
371   return Reloc::PIC_;
372 }
373 
374 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
375                                          StringRef CPU, StringRef FS,
376                                          TargetOptions Options,
377                                          Optional<Reloc::Model> RM,
378                                          Optional<CodeModel::Model> CM,
379                                          CodeGenOpt::Level OptLevel)
380     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
381                         FS, Options, getEffectiveRelocModel(RM),
382                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
383       TLOF(createTLOF(getTargetTriple())) {
384   initAsmInfo();
385   if (TT.getArch() == Triple::amdgcn) {
386     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
387       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
388     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
389       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
390   }
391 }
392 
393 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
394 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
395 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
396 bool AMDGPUTargetMachine::EnableLowerModuleLDS = true;
397 
398 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
399 
400 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
401   Attribute GPUAttr = F.getFnAttribute("target-cpu");
402   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
403 }
404 
405 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
406   Attribute FSAttr = F.getFnAttribute("target-features");
407 
408   return FSAttr.isValid() ? FSAttr.getValueAsString()
409                           : getTargetFeatureString();
410 }
411 
412 /// Predicate for Internalize pass.
413 static bool mustPreserveGV(const GlobalValue &GV) {
414   if (const Function *F = dyn_cast<Function>(&GV))
415     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
416 
417   return !GV.use_empty();
418 }
419 
420 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
421   Builder.DivergentTarget = true;
422 
423   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
424   bool Internalize = InternalizeSymbols;
425   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
426   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
427   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
428 
429   if (EnableFunctionCalls) {
430     delete Builder.Inliner;
431     Builder.Inliner = createFunctionInliningPass();
432   }
433 
434   Builder.addExtension(
435     PassManagerBuilder::EP_ModuleOptimizerEarly,
436     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
437                                                legacy::PassManagerBase &PM) {
438       if (AMDGPUAA) {
439         PM.add(createAMDGPUAAWrapperPass());
440         PM.add(createAMDGPUExternalAAWrapperPass());
441       }
442       PM.add(createAMDGPUUnifyMetadataPass());
443       PM.add(createAMDGPUPrintfRuntimeBinding());
444       if (Internalize)
445         PM.add(createInternalizePass(mustPreserveGV));
446       PM.add(createAMDGPUPropagateAttributesLatePass(this));
447       if (Internalize)
448         PM.add(createGlobalDCEPass());
449       if (EarlyInline)
450         PM.add(createAMDGPUAlwaysInlinePass(false));
451   });
452 
453   Builder.addExtension(
454     PassManagerBuilder::EP_EarlyAsPossible,
455     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
456                                       legacy::PassManagerBase &PM) {
457       if (AMDGPUAA) {
458         PM.add(createAMDGPUAAWrapperPass());
459         PM.add(createAMDGPUExternalAAWrapperPass());
460       }
461       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
462       PM.add(llvm::createAMDGPUUseNativeCallsPass());
463       if (LibCallSimplify)
464         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
465   });
466 
467   Builder.addExtension(
468     PassManagerBuilder::EP_CGSCCOptimizerLate,
469     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
470       // Add infer address spaces pass to the opt pipeline after inlining
471       // but before SROA to increase SROA opportunities.
472       PM.add(createInferAddressSpacesPass());
473 
474       // This should run after inlining to have any chance of doing anything,
475       // and before other cleanup optimizations.
476       PM.add(createAMDGPULowerKernelAttributesPass());
477 
478       // Promote alloca to vector before SROA and loop unroll. If we manage
479       // to eliminate allocas before unroll we may choose to unroll less.
480       if (EnableOpt)
481         PM.add(createAMDGPUPromoteAllocaToVector());
482   });
483 }
484 
485 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
486   AAM.registerFunctionAnalysis<AMDGPUAA>();
487 }
488 
489 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
490                                                        bool DebugPassManager) {
491   PB.registerPipelineParsingCallback(
492       [this](StringRef PassName, ModulePassManager &PM,
493              ArrayRef<PassBuilder::PipelineElement>) {
494         if (PassName == "amdgpu-propagate-attributes-late") {
495           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
496           return true;
497         }
498         if (PassName == "amdgpu-unify-metadata") {
499           PM.addPass(AMDGPUUnifyMetadataPass());
500           return true;
501         }
502         if (PassName == "amdgpu-printf-runtime-binding") {
503           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
504           return true;
505         }
506         if (PassName == "amdgpu-always-inline") {
507           PM.addPass(AMDGPUAlwaysInlinePass());
508           return true;
509         }
510         if (PassName == "amdgpu-lower-module-lds") {
511           PM.addPass(AMDGPULowerModuleLDSPass());
512           return true;
513         }
514         return false;
515       });
516   PB.registerPipelineParsingCallback(
517       [this](StringRef PassName, FunctionPassManager &PM,
518              ArrayRef<PassBuilder::PipelineElement>) {
519         if (PassName == "amdgpu-simplifylib") {
520           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
521           return true;
522         }
523         if (PassName == "amdgpu-usenative") {
524           PM.addPass(AMDGPUUseNativeCallsPass());
525           return true;
526         }
527         if (PassName == "amdgpu-promote-alloca") {
528           PM.addPass(AMDGPUPromoteAllocaPass(*this));
529           return true;
530         }
531         if (PassName == "amdgpu-promote-alloca-to-vector") {
532           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
533           return true;
534         }
535         if (PassName == "amdgpu-lower-kernel-attributes") {
536           PM.addPass(AMDGPULowerKernelAttributesPass());
537           return true;
538         }
539         if (PassName == "amdgpu-propagate-attributes-early") {
540           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
541           return true;
542         }
543         return false;
544       });
545 
546   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
547     FAM.registerPass([&] { return AMDGPUAA(); });
548   });
549 
550   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
551     if (AAName == "amdgpu-aa") {
552       AAM.registerFunctionAnalysis<AMDGPUAA>();
553       return true;
554     }
555     return false;
556   });
557 
558   PB.registerPipelineStartEPCallback([this, DebugPassManager](
559                                          ModulePassManager &PM,
560                                          PassBuilder::OptimizationLevel Level) {
561     FunctionPassManager FPM(DebugPassManager);
562     FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
563     FPM.addPass(AMDGPUUseNativeCallsPass());
564     if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
565       FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
566     PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
567   });
568 
569   PB.registerPipelineEarlySimplificationEPCallback(
570       [this](ModulePassManager &PM, PassBuilder::OptimizationLevel Level) {
571         if (Level == PassBuilder::OptimizationLevel::O0)
572           return;
573 
574         PM.addPass(AMDGPUUnifyMetadataPass());
575         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
576 
577         if (InternalizeSymbols) {
578           // Global variables may have dead uses which need to be removed.
579           // Otherwise these useless global variables will not get internalized.
580           PM.addPass(GlobalDCEPass());
581           PM.addPass(InternalizePass(mustPreserveGV));
582         }
583         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
584         if (InternalizeSymbols) {
585           PM.addPass(GlobalDCEPass());
586         }
587         if (EarlyInlineAll && !EnableFunctionCalls)
588           PM.addPass(AMDGPUAlwaysInlinePass());
589       });
590 
591   PB.registerCGSCCOptimizerLateEPCallback(
592       [this, DebugPassManager](CGSCCPassManager &PM,
593                                PassBuilder::OptimizationLevel Level) {
594         if (Level == PassBuilder::OptimizationLevel::O0)
595           return;
596 
597         FunctionPassManager FPM(DebugPassManager);
598 
599         // Add infer address spaces pass to the opt pipeline after inlining
600         // but before SROA to increase SROA opportunities.
601         FPM.addPass(InferAddressSpacesPass());
602 
603         // This should run after inlining to have any chance of doing
604         // anything, and before other cleanup optimizations.
605         FPM.addPass(AMDGPULowerKernelAttributesPass());
606 
607         if (Level != PassBuilder::OptimizationLevel::O0) {
608           // Promote alloca to vector before SROA and loop unroll. If we
609           // manage to eliminate allocas before unroll we may choose to unroll
610           // less.
611           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
612         }
613 
614         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
615       });
616 }
617 
618 //===----------------------------------------------------------------------===//
619 // R600 Target Machine (R600 -> Cayman)
620 //===----------------------------------------------------------------------===//
621 
622 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
623                                      StringRef CPU, StringRef FS,
624                                      TargetOptions Options,
625                                      Optional<Reloc::Model> RM,
626                                      Optional<CodeModel::Model> CM,
627                                      CodeGenOpt::Level OL, bool JIT)
628     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
629   setRequiresStructuredCFG(true);
630 
631   // Override the default since calls aren't supported for r600.
632   if (EnableFunctionCalls &&
633       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
634     EnableFunctionCalls = false;
635 }
636 
637 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
638   const Function &F) const {
639   StringRef GPU = getGPUName(F);
640   StringRef FS = getFeatureString(F);
641 
642   SmallString<128> SubtargetKey(GPU);
643   SubtargetKey.append(FS);
644 
645   auto &I = SubtargetMap[SubtargetKey];
646   if (!I) {
647     // This needs to be done before we create a new subtarget since any
648     // creation will depend on the TM and the code generation flags on the
649     // function that reside in TargetOptions.
650     resetTargetOptions(F);
651     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
652   }
653 
654   return I.get();
655 }
656 
657 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
658   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
659           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
660           AddrSpace == AMDGPUAS::REGION_ADDRESS)
661              ? -1
662              : 0;
663 }
664 
665 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
666                                               unsigned DestAS) const {
667   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
668          AMDGPU::isFlatGlobalAddrSpace(DestAS);
669 }
670 
671 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
672   const auto *LD = dyn_cast<LoadInst>(V);
673   if (!LD)
674     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
675 
676   // It must be a generic pointer loaded.
677   assert(V->getType()->isPointerTy() &&
678          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
679 
680   const auto *Ptr = LD->getPointerOperand();
681   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
682     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
683   // For a generic pointer loaded from the constant memory, it could be assumed
684   // as a global pointer since the constant memory is only populated on the
685   // host side. As implied by the offload programming model, only global
686   // pointers could be referenced on the host side.
687   return AMDGPUAS::GLOBAL_ADDRESS;
688 }
689 
690 TargetTransformInfo
691 R600TargetMachine::getTargetTransformInfo(const Function &F) {
692   return TargetTransformInfo(R600TTIImpl(this, F));
693 }
694 
695 //===----------------------------------------------------------------------===//
696 // GCN Target Machine (SI+)
697 //===----------------------------------------------------------------------===//
698 
699 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
700                                    StringRef CPU, StringRef FS,
701                                    TargetOptions Options,
702                                    Optional<Reloc::Model> RM,
703                                    Optional<CodeModel::Model> CM,
704                                    CodeGenOpt::Level OL, bool JIT)
705     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
706 
707 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
708   StringRef GPU = getGPUName(F);
709   StringRef FS = getFeatureString(F);
710 
711   SmallString<128> SubtargetKey(GPU);
712   SubtargetKey.append(FS);
713 
714   auto &I = SubtargetMap[SubtargetKey];
715   if (!I) {
716     // This needs to be done before we create a new subtarget since any
717     // creation will depend on the TM and the code generation flags on the
718     // function that reside in TargetOptions.
719     resetTargetOptions(F);
720     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
721   }
722 
723   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
724 
725   return I.get();
726 }
727 
728 TargetTransformInfo
729 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
730   return TargetTransformInfo(GCNTTIImpl(this, F));
731 }
732 
733 //===----------------------------------------------------------------------===//
734 // AMDGPU Pass Setup
735 //===----------------------------------------------------------------------===//
736 
737 namespace {
738 
739 class AMDGPUPassConfig : public TargetPassConfig {
740 public:
741   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
742     : TargetPassConfig(TM, PM) {
743     // Exceptions and StackMaps are not supported, so these passes will never do
744     // anything.
745     disablePass(&StackMapLivenessID);
746     disablePass(&FuncletLayoutID);
747   }
748 
749   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
750     return getTM<AMDGPUTargetMachine>();
751   }
752 
753   ScheduleDAGInstrs *
754   createMachineScheduler(MachineSchedContext *C) const override {
755     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
756     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
757     return DAG;
758   }
759 
760   void addEarlyCSEOrGVNPass();
761   void addStraightLineScalarOptimizationPasses();
762   void addIRPasses() override;
763   void addCodeGenPrepare() override;
764   bool addPreISel() override;
765   bool addInstSelector() override;
766   bool addGCPasses() override;
767 
768   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
769 };
770 
771 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
772   return getStandardCSEConfigForOpt(TM->getOptLevel());
773 }
774 
775 class R600PassConfig final : public AMDGPUPassConfig {
776 public:
777   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
778     : AMDGPUPassConfig(TM, PM) {}
779 
780   ScheduleDAGInstrs *createMachineScheduler(
781     MachineSchedContext *C) const override {
782     return createR600MachineScheduler(C);
783   }
784 
785   bool addPreISel() override;
786   bool addInstSelector() override;
787   void addPreRegAlloc() override;
788   void addPreSched2() override;
789   void addPreEmitPass() override;
790 };
791 
792 class GCNPassConfig final : public AMDGPUPassConfig {
793 public:
794   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
795     : AMDGPUPassConfig(TM, PM) {
796     // It is necessary to know the register usage of the entire call graph.  We
797     // allow calls without EnableAMDGPUFunctionCalls if they are marked
798     // noinline, so this is always required.
799     setRequiresCodeGenSCCOrder(true);
800   }
801 
802   GCNTargetMachine &getGCNTargetMachine() const {
803     return getTM<GCNTargetMachine>();
804   }
805 
806   ScheduleDAGInstrs *
807   createMachineScheduler(MachineSchedContext *C) const override;
808 
809   bool addPreISel() override;
810   void addMachineSSAOptimization() override;
811   bool addILPOpts() override;
812   bool addInstSelector() override;
813   bool addIRTranslator() override;
814   void addPreLegalizeMachineIR() override;
815   bool addLegalizeMachineIR() override;
816   void addPreRegBankSelect() override;
817   bool addRegBankSelect() override;
818   void addPreGlobalInstructionSelect() override;
819   bool addGlobalInstructionSelect() override;
820   void addFastRegAlloc() override;
821   void addOptimizedRegAlloc() override;
822   void addPreRegAlloc() override;
823   bool addPreRewrite() override;
824   void addPostRegAlloc() override;
825   void addPreSched2() override;
826   void addPreEmitPass() override;
827 };
828 
829 } // end anonymous namespace
830 
831 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
832   if (getOptLevel() == CodeGenOpt::Aggressive)
833     addPass(createGVNPass());
834   else
835     addPass(createEarlyCSEPass());
836 }
837 
838 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
839   addPass(createLICMPass());
840   addPass(createSeparateConstOffsetFromGEPPass());
841   addPass(createSpeculativeExecutionPass());
842   // ReassociateGEPs exposes more opportunites for SLSR. See
843   // the example in reassociate-geps-and-slsr.ll.
844   addPass(createStraightLineStrengthReducePass());
845   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
846   // EarlyCSE can reuse.
847   addEarlyCSEOrGVNPass();
848   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
849   addPass(createNaryReassociatePass());
850   // NaryReassociate on GEPs creates redundant common expressions, so run
851   // EarlyCSE after it.
852   addPass(createEarlyCSEPass());
853 }
854 
855 void AMDGPUPassConfig::addIRPasses() {
856   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
857 
858   // There is no reason to run these.
859   disablePass(&StackMapLivenessID);
860   disablePass(&FuncletLayoutID);
861   disablePass(&PatchableFunctionID);
862 
863   addPass(createAMDGPUPrintfRuntimeBinding());
864 
865   // This must occur before inlining, as the inliner will not look through
866   // bitcast calls.
867   addPass(createAMDGPUFixFunctionBitcastsPass());
868 
869   // A call to propagate attributes pass in the backend in case opt was not run.
870   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
871 
872   addPass(createAtomicExpandPass());
873 
874 
875   addPass(createAMDGPULowerIntrinsicsPass());
876 
877   // Function calls are not supported, so make sure we inline everything.
878   addPass(createAMDGPUAlwaysInlinePass());
879   addPass(createAlwaysInlinerLegacyPass());
880   // We need to add the barrier noop pass, otherwise adding the function
881   // inlining pass will cause all of the PassConfigs passes to be run
882   // one function at a time, which means if we have a nodule with two
883   // functions, then we will generate code for the first function
884   // without ever running any passes on the second.
885   addPass(createBarrierNoopPass());
886 
887   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
888   if (TM.getTargetTriple().getArch() == Triple::r600)
889     addPass(createR600OpenCLImageTypeLoweringPass());
890 
891   // Replace OpenCL enqueued block function pointers with global variables.
892   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
893 
894   // Can increase LDS used by kernel so runs before PromoteAlloca
895   if (EnableLowerModuleLDS)
896     addPass(createAMDGPULowerModuleLDSPass());
897 
898   if (TM.getOptLevel() > CodeGenOpt::None) {
899     addPass(createInferAddressSpacesPass());
900     addPass(createAMDGPUPromoteAlloca());
901 
902     if (EnableSROA)
903       addPass(createSROAPass());
904 
905     if (EnableScalarIRPasses)
906       addStraightLineScalarOptimizationPasses();
907 
908     if (EnableAMDGPUAliasAnalysis) {
909       addPass(createAMDGPUAAWrapperPass());
910       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
911                                              AAResults &AAR) {
912         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
913           AAR.addAAResult(WrapperPass->getResult());
914         }));
915     }
916   }
917 
918   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
919     // TODO: May want to move later or split into an early and late one.
920     addPass(createAMDGPUCodeGenPreparePass());
921   }
922 
923   TargetPassConfig::addIRPasses();
924 
925   // EarlyCSE is not always strong enough to clean up what LSR produces. For
926   // example, GVN can combine
927   //
928   //   %0 = add %a, %b
929   //   %1 = add %b, %a
930   //
931   // and
932   //
933   //   %0 = shl nsw %a, 2
934   //   %1 = shl %a, 2
935   //
936   // but EarlyCSE can do neither of them.
937   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
938     addEarlyCSEOrGVNPass();
939 }
940 
941 void AMDGPUPassConfig::addCodeGenPrepare() {
942   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
943     addPass(createAMDGPUAnnotateKernelFeaturesPass());
944 
945   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
946       EnableLowerKernelArguments)
947     addPass(createAMDGPULowerKernelArgumentsPass());
948 
949   addPass(&AMDGPUPerfHintAnalysisID);
950 
951   TargetPassConfig::addCodeGenPrepare();
952 
953   if (EnableLoadStoreVectorizer)
954     addPass(createLoadStoreVectorizerPass());
955 
956   // LowerSwitch pass may introduce unreachable blocks that can
957   // cause unexpected behavior for subsequent passes. Placing it
958   // here seems better that these blocks would get cleaned up by
959   // UnreachableBlockElim inserted next in the pass flow.
960   addPass(createLowerSwitchPass());
961 }
962 
963 bool AMDGPUPassConfig::addPreISel() {
964   addPass(createFlattenCFGPass());
965   return false;
966 }
967 
968 bool AMDGPUPassConfig::addInstSelector() {
969   // Defer the verifier until FinalizeISel.
970   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
971   return false;
972 }
973 
974 bool AMDGPUPassConfig::addGCPasses() {
975   // Do nothing. GC is not supported.
976   return false;
977 }
978 
979 //===----------------------------------------------------------------------===//
980 // R600 Pass Setup
981 //===----------------------------------------------------------------------===//
982 
983 bool R600PassConfig::addPreISel() {
984   AMDGPUPassConfig::addPreISel();
985 
986   if (EnableR600StructurizeCFG)
987     addPass(createStructurizeCFGPass());
988   return false;
989 }
990 
991 bool R600PassConfig::addInstSelector() {
992   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
993   return false;
994 }
995 
996 void R600PassConfig::addPreRegAlloc() {
997   addPass(createR600VectorRegMerger());
998 }
999 
1000 void R600PassConfig::addPreSched2() {
1001   addPass(createR600EmitClauseMarkers(), false);
1002   if (EnableR600IfConvert)
1003     addPass(&IfConverterID, false);
1004   addPass(createR600ClauseMergePass(), false);
1005 }
1006 
1007 void R600PassConfig::addPreEmitPass() {
1008   addPass(createAMDGPUCFGStructurizerPass(), false);
1009   addPass(createR600ExpandSpecialInstrsPass(), false);
1010   addPass(&FinalizeMachineBundlesID, false);
1011   addPass(createR600Packetizer(), false);
1012   addPass(createR600ControlFlowFinalizer(), false);
1013 }
1014 
1015 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
1016   return new R600PassConfig(*this, PM);
1017 }
1018 
1019 //===----------------------------------------------------------------------===//
1020 // GCN Pass Setup
1021 //===----------------------------------------------------------------------===//
1022 
1023 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1024   MachineSchedContext *C) const {
1025   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1026   if (ST.enableSIScheduler())
1027     return createSIMachineScheduler(C);
1028   return createGCNMaxOccupancyMachineScheduler(C);
1029 }
1030 
1031 bool GCNPassConfig::addPreISel() {
1032   AMDGPUPassConfig::addPreISel();
1033 
1034   addPass(createAMDGPULateCodeGenPreparePass());
1035   if (EnableAtomicOptimizations) {
1036     addPass(createAMDGPUAtomicOptimizerPass());
1037   }
1038 
1039   // FIXME: We need to run a pass to propagate the attributes when calls are
1040   // supported.
1041 
1042   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1043   // regions formed by them.
1044   addPass(&AMDGPUUnifyDivergentExitNodesID);
1045   if (!LateCFGStructurize) {
1046     if (EnableStructurizerWorkarounds) {
1047       addPass(createFixIrreduciblePass());
1048       addPass(createUnifyLoopExitsPass());
1049     }
1050     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1051   }
1052   addPass(createSinkingPass());
1053   addPass(createAMDGPUAnnotateUniformValues());
1054   if (!LateCFGStructurize) {
1055     addPass(createSIAnnotateControlFlowPass());
1056   }
1057   addPass(createLCSSAPass());
1058 
1059   return false;
1060 }
1061 
1062 void GCNPassConfig::addMachineSSAOptimization() {
1063   TargetPassConfig::addMachineSSAOptimization();
1064 
1065   // We want to fold operands after PeepholeOptimizer has run (or as part of
1066   // it), because it will eliminate extra copies making it easier to fold the
1067   // real source operand. We want to eliminate dead instructions after, so that
1068   // we see fewer uses of the copies. We then need to clean up the dead
1069   // instructions leftover after the operands are folded as well.
1070   //
1071   // XXX - Can we get away without running DeadMachineInstructionElim again?
1072   addPass(&SIFoldOperandsID);
1073   if (EnableDPPCombine)
1074     addPass(&GCNDPPCombineID);
1075   addPass(&SILoadStoreOptimizerID);
1076   if (EnableSDWAPeephole) {
1077     addPass(&SIPeepholeSDWAID);
1078     addPass(&EarlyMachineLICMID);
1079     addPass(&MachineCSEID);
1080     addPass(&SIFoldOperandsID);
1081   }
1082   addPass(&DeadMachineInstructionElimID);
1083   addPass(createSIShrinkInstructionsPass());
1084 }
1085 
1086 bool GCNPassConfig::addILPOpts() {
1087   if (EnableEarlyIfConversion)
1088     addPass(&EarlyIfConverterID);
1089 
1090   TargetPassConfig::addILPOpts();
1091   return false;
1092 }
1093 
1094 bool GCNPassConfig::addInstSelector() {
1095   AMDGPUPassConfig::addInstSelector();
1096   addPass(&SIFixSGPRCopiesID);
1097   addPass(createSILowerI1CopiesPass());
1098   return false;
1099 }
1100 
1101 bool GCNPassConfig::addIRTranslator() {
1102   addPass(new IRTranslator(getOptLevel()));
1103   return false;
1104 }
1105 
1106 void GCNPassConfig::addPreLegalizeMachineIR() {
1107   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1108   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1109   addPass(new Localizer());
1110 }
1111 
1112 bool GCNPassConfig::addLegalizeMachineIR() {
1113   addPass(new Legalizer());
1114   return false;
1115 }
1116 
1117 void GCNPassConfig::addPreRegBankSelect() {
1118   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1119   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1120 }
1121 
1122 bool GCNPassConfig::addRegBankSelect() {
1123   addPass(new RegBankSelect());
1124   return false;
1125 }
1126 
1127 void GCNPassConfig::addPreGlobalInstructionSelect() {
1128   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1129   addPass(createAMDGPURegBankCombiner(IsOptNone));
1130 }
1131 
1132 bool GCNPassConfig::addGlobalInstructionSelect() {
1133   addPass(new InstructionSelect(getOptLevel()));
1134   return false;
1135 }
1136 
1137 void GCNPassConfig::addPreRegAlloc() {
1138   if (LateCFGStructurize) {
1139     addPass(createAMDGPUMachineCFGStructurizerPass());
1140   }
1141 }
1142 
1143 void GCNPassConfig::addFastRegAlloc() {
1144   // FIXME: We have to disable the verifier here because of PHIElimination +
1145   // TwoAddressInstructions disabling it.
1146 
1147   // This must be run immediately after phi elimination and before
1148   // TwoAddressInstructions, otherwise the processing of the tied operand of
1149   // SI_ELSE will introduce a copy of the tied operand source after the else.
1150   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1151 
1152   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1153   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1154 
1155   TargetPassConfig::addFastRegAlloc();
1156 }
1157 
1158 void GCNPassConfig::addOptimizedRegAlloc() {
1159   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1160   // instructions that cause scheduling barriers.
1161   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1162   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1163 
1164   if (OptExecMaskPreRA)
1165     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1166   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1167 
1168   // This must be run immediately after phi elimination and before
1169   // TwoAddressInstructions, otherwise the processing of the tied operand of
1170   // SI_ELSE will introduce a copy of the tied operand source after the else.
1171   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1172 
1173   if (EnableDCEInRA)
1174     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1175 
1176   TargetPassConfig::addOptimizedRegAlloc();
1177 }
1178 
1179 bool GCNPassConfig::addPreRewrite() {
1180   if (EnableRegReassign) {
1181     addPass(&GCNNSAReassignID);
1182     addPass(createGCNRegBankReassignPass(AMDGPU::RM_BOTH));
1183   }
1184   return true;
1185 }
1186 
1187 void GCNPassConfig::addPostRegAlloc() {
1188   addPass(&SIFixVGPRCopiesID);
1189   if (getOptLevel() > CodeGenOpt::None)
1190     addPass(&SIOptimizeExecMaskingID);
1191   TargetPassConfig::addPostRegAlloc();
1192 
1193   // Equivalent of PEI for SGPRs.
1194   addPass(&SILowerSGPRSpillsID);
1195 }
1196 
1197 void GCNPassConfig::addPreSched2() {
1198   addPass(&SIPostRABundlerID);
1199 }
1200 
1201 void GCNPassConfig::addPreEmitPass() {
1202   addPass(createSIMemoryLegalizerPass());
1203   addPass(createSIInsertWaitcntsPass());
1204   addPass(createSIShrinkInstructionsPass());
1205   addPass(createSIModeRegisterPass());
1206 
1207   if (getOptLevel() > CodeGenOpt::None)
1208     addPass(&SIInsertHardClausesID);
1209 
1210   addPass(&SILateBranchLoweringPassID);
1211   if (getOptLevel() > CodeGenOpt::None)
1212     addPass(&SIPreEmitPeepholeID);
1213   // The hazard recognizer that runs as part of the post-ra scheduler does not
1214   // guarantee to be able handle all hazards correctly. This is because if there
1215   // are multiple scheduling regions in a basic block, the regions are scheduled
1216   // bottom up, so when we begin to schedule a region we don't know what
1217   // instructions were emitted directly before it.
1218   //
1219   // Here we add a stand-alone hazard recognizer pass which can handle all
1220   // cases.
1221   addPass(&PostRAHazardRecognizerID);
1222   addPass(&BranchRelaxationPassID);
1223 }
1224 
1225 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1226   return new GCNPassConfig(*this, PM);
1227 }
1228 
1229 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1230   return new yaml::SIMachineFunctionInfo();
1231 }
1232 
1233 yaml::MachineFunctionInfo *
1234 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1235   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1236   return new yaml::SIMachineFunctionInfo(*MFI,
1237                                          *MF.getSubtarget().getRegisterInfo());
1238 }
1239 
1240 bool GCNTargetMachine::parseMachineFunctionInfo(
1241     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1242     SMDiagnostic &Error, SMRange &SourceRange) const {
1243   const yaml::SIMachineFunctionInfo &YamlMFI =
1244       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1245   MachineFunction &MF = PFS.MF;
1246   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1247 
1248   MFI->initializeBaseYamlFields(YamlMFI);
1249 
1250   if (MFI->Occupancy == 0) {
1251     // Fixup the subtarget dependent default value.
1252     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1253     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1254   }
1255 
1256   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1257     Register TempReg;
1258     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1259       SourceRange = RegName.SourceRange;
1260       return true;
1261     }
1262     RegVal = TempReg;
1263 
1264     return false;
1265   };
1266 
1267   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1268     // Create a diagnostic for a the register string literal.
1269     const MemoryBuffer &Buffer =
1270         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1271     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1272                          RegName.Value.size(), SourceMgr::DK_Error,
1273                          "incorrect register class for field", RegName.Value,
1274                          None, None);
1275     SourceRange = RegName.SourceRange;
1276     return true;
1277   };
1278 
1279   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1280       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1281       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1282     return true;
1283 
1284   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1285       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1286     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1287   }
1288 
1289   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1290       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1291     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1292   }
1293 
1294   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1295       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1296     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1297   }
1298 
1299   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1300                                    const TargetRegisterClass &RC,
1301                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1302                                    unsigned SystemSGPRs) {
1303     // Skip parsing if it's not present.
1304     if (!A)
1305       return false;
1306 
1307     if (A->IsRegister) {
1308       Register Reg;
1309       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1310         SourceRange = A->RegisterName.SourceRange;
1311         return true;
1312       }
1313       if (!RC.contains(Reg))
1314         return diagnoseRegisterClass(A->RegisterName);
1315       Arg = ArgDescriptor::createRegister(Reg);
1316     } else
1317       Arg = ArgDescriptor::createStack(A->StackOffset);
1318     // Check and apply the optional mask.
1319     if (A->Mask)
1320       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1321 
1322     MFI->NumUserSGPRs += UserSGPRs;
1323     MFI->NumSystemSGPRs += SystemSGPRs;
1324     return false;
1325   };
1326 
1327   if (YamlMFI.ArgInfo &&
1328       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1329                              AMDGPU::SGPR_128RegClass,
1330                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1331        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1332                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1333                              2, 0) ||
1334        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1335                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1336        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1337                              AMDGPU::SReg_64RegClass,
1338                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1339        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1340                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1341                              2, 0) ||
1342        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1343                              AMDGPU::SReg_64RegClass,
1344                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1345        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1346                              AMDGPU::SGPR_32RegClass,
1347                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1348        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1349                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1350                              0, 1) ||
1351        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1352                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1353                              0, 1) ||
1354        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1355                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1356                              0, 1) ||
1357        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1358                              AMDGPU::SGPR_32RegClass,
1359                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1360        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1361                              AMDGPU::SGPR_32RegClass,
1362                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1363        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1364                              AMDGPU::SReg_64RegClass,
1365                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1366        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1367                              AMDGPU::SReg_64RegClass,
1368                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1369        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1370                              AMDGPU::VGPR_32RegClass,
1371                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1372        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1373                              AMDGPU::VGPR_32RegClass,
1374                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1375        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1376                              AMDGPU::VGPR_32RegClass,
1377                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1378     return true;
1379 
1380   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1381   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1382   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1383   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1384   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1385   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1386 
1387   return false;
1388 }
1389