1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110   cl::desc("Enable AMDGPU Alias Analysis"),
111   cl::init(true));
112 
113 // Option to enable new waitcnt insertion pass.
114 static cl::opt<bool> EnableSIInsertWaitcntsPass(
115   "enable-si-insert-waitcnts",
116   cl::desc("Use new waitcnt insertion pass"),
117   cl::init(true));
118 
119 // Option to run late CFG structurizer
120 static cl::opt<bool> LateCFGStructurize(
121   "amdgpu-late-structurize",
122   cl::desc("Enable late CFG structurization"),
123   cl::init(false),
124   cl::Hidden);
125 
126 static cl::opt<bool> EnableAMDGPUFunctionCalls(
127   "amdgpu-function-calls",
128   cl::Hidden,
129   cl::desc("Enable AMDGPU function call support"),
130   cl::init(false));
131 
132 // Enable lib calls simplifications
133 static cl::opt<bool> EnableLibCallSimplify(
134   "amdgpu-simplify-libcall",
135   cl::desc("Enable mdgpu library simplifications"),
136   cl::init(true),
137   cl::Hidden);
138 
139 extern "C" void LLVMInitializeAMDGPUTarget() {
140   // Register the target
141   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
142   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
143 
144   PassRegistry *PR = PassRegistry::getPassRegistry();
145   initializeR600ClauseMergePassPass(*PR);
146   initializeR600ControlFlowFinalizerPass(*PR);
147   initializeR600PacketizerPass(*PR);
148   initializeR600ExpandSpecialInstrsPassPass(*PR);
149   initializeR600VectorRegMergerPass(*PR);
150   initializeAMDGPUDAGToDAGISelPass(*PR);
151   initializeSILowerI1CopiesPass(*PR);
152   initializeSIFixSGPRCopiesPass(*PR);
153   initializeSIFixVGPRCopiesPass(*PR);
154   initializeSIFoldOperandsPass(*PR);
155   initializeSIPeepholeSDWAPass(*PR);
156   initializeSIShrinkInstructionsPass(*PR);
157   initializeSIOptimizeExecMaskingPreRAPass(*PR);
158   initializeSILoadStoreOptimizerPass(*PR);
159   initializeAMDGPUAlwaysInlinePass(*PR);
160   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
161   initializeAMDGPUAnnotateUniformValuesPass(*PR);
162   initializeAMDGPUArgumentUsageInfoPass(*PR);
163   initializeAMDGPULowerIntrinsicsPass(*PR);
164   initializeAMDGPUPromoteAllocaPass(*PR);
165   initializeAMDGPUCodeGenPreparePass(*PR);
166   initializeAMDGPURewriteOutArgumentsPass(*PR);
167   initializeAMDGPUUnifyMetadataPass(*PR);
168   initializeSIAnnotateControlFlowPass(*PR);
169   initializeSIInsertWaitsPass(*PR);
170   initializeSIInsertWaitcntsPass(*PR);
171   initializeSIWholeQuadModePass(*PR);
172   initializeSILowerControlFlowPass(*PR);
173   initializeSIInsertSkipsPass(*PR);
174   initializeSIMemoryLegalizerPass(*PR);
175   initializeSIDebuggerInsertNopsPass(*PR);
176   initializeSIOptimizeExecMaskingPass(*PR);
177   initializeSIFixWWMLivenessPass(*PR);
178   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
179   initializeAMDGPUAAWrapperPassPass(*PR);
180   initializeAMDGPUUseNativeCallsPass(*PR);
181   initializeAMDGPUSimplifyLibCallsPass(*PR);
182   initializeAMDGPUInlinerPass(*PR);
183 }
184 
185 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
186   return llvm::make_unique<AMDGPUTargetObjectFile>();
187 }
188 
189 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
190   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
191 }
192 
193 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
194   return new SIScheduleDAGMI(C);
195 }
196 
197 static ScheduleDAGInstrs *
198 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
199   ScheduleDAGMILive *DAG =
200     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
201   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
202   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
203   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
204   return DAG;
205 }
206 
207 static ScheduleDAGInstrs *
208 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
209   auto DAG = new GCNIterativeScheduler(C,
210     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
211   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
212   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
213   return DAG;
214 }
215 
216 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
217   return new GCNIterativeScheduler(C,
218     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
219 }
220 
221 static MachineSchedRegistry
222 R600SchedRegistry("r600", "Run R600's custom scheduler",
223                    createR600MachineScheduler);
224 
225 static MachineSchedRegistry
226 SISchedRegistry("si", "Run SI's custom scheduler",
227                 createSIMachineScheduler);
228 
229 static MachineSchedRegistry
230 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
231                              "Run GCN scheduler to maximize occupancy",
232                              createGCNMaxOccupancyMachineScheduler);
233 
234 static MachineSchedRegistry
235 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
236   "Run GCN scheduler to maximize occupancy (experimental)",
237   createIterativeGCNMaxOccupancyMachineScheduler);
238 
239 static MachineSchedRegistry
240 GCNMinRegSchedRegistry("gcn-minreg",
241   "Run GCN iterative scheduler for minimal register usage (experimental)",
242   createMinRegScheduler);
243 
244 static StringRef computeDataLayout(const Triple &TT) {
245   if (TT.getArch() == Triple::r600) {
246     // 32-bit pointers.
247     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
248             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
249   }
250 
251   // 32-bit private, local, and region pointers. 64-bit global, constant and
252   // flat.
253   if (TT.getEnvironmentName() == "amdgiz" ||
254       TT.getEnvironmentName() == "amdgizcl")
255     return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
256          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
257          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
258   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
259       "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
260       "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
261 }
262 
263 LLVM_READNONE
264 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
265   if (!GPU.empty())
266     return GPU;
267 
268   if (TT.getArch() == Triple::amdgcn)
269     return "generic";
270 
271   return "r600";
272 }
273 
274 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
275   // The AMDGPU toolchain only supports generating shared objects, so we
276   // must always use PIC.
277   return Reloc::PIC_;
278 }
279 
280 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
281   if (CM)
282     return *CM;
283   return CodeModel::Small;
284 }
285 
286 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
287                                          StringRef CPU, StringRef FS,
288                                          TargetOptions Options,
289                                          Optional<Reloc::Model> RM,
290                                          Optional<CodeModel::Model> CM,
291                                          CodeGenOpt::Level OptLevel)
292     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
293                         FS, Options, getEffectiveRelocModel(RM),
294                         getEffectiveCodeModel(CM), OptLevel),
295       TLOF(createTLOF(getTargetTriple())) {
296   AS = AMDGPU::getAMDGPUAS(TT);
297   initAsmInfo();
298 }
299 
300 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
301 
302 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
303   Attribute GPUAttr = F.getFnAttribute("target-cpu");
304   return GPUAttr.hasAttribute(Attribute::None) ?
305     getTargetCPU() : GPUAttr.getValueAsString();
306 }
307 
308 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
309   Attribute FSAttr = F.getFnAttribute("target-features");
310 
311   return FSAttr.hasAttribute(Attribute::None) ?
312     getTargetFeatureString() :
313     FSAttr.getValueAsString();
314 }
315 
316 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
317   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
318       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
319         AAR.addAAResult(WrapperPass->getResult());
320       });
321 }
322 
323 /// Predicate for Internalize pass.
324 bool mustPreserveGV(const GlobalValue &GV) {
325   if (const Function *F = dyn_cast<Function>(&GV))
326     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
327 
328   return !GV.use_empty();
329 }
330 
331 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
332   Builder.DivergentTarget = true;
333 
334   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
335   bool Internalize = InternalizeSymbols;
336   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
337   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
338   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
339 
340   if (EnableAMDGPUFunctionCalls) {
341     delete Builder.Inliner;
342     Builder.Inliner = createAMDGPUFunctionInliningPass();
343   }
344 
345   if (Internalize) {
346     // If we're generating code, we always have the whole program available. The
347     // relocations expected for externally visible functions aren't supported,
348     // so make sure every non-entry function is hidden.
349     Builder.addExtension(
350       PassManagerBuilder::EP_EnabledOnOptLevel0,
351       [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
352         PM.add(createInternalizePass(mustPreserveGV));
353       });
354   }
355 
356   Builder.addExtension(
357     PassManagerBuilder::EP_ModuleOptimizerEarly,
358     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
359                                          legacy::PassManagerBase &PM) {
360       if (AMDGPUAA) {
361         PM.add(createAMDGPUAAWrapperPass());
362         PM.add(createAMDGPUExternalAAWrapperPass());
363       }
364       PM.add(createAMDGPUUnifyMetadataPass());
365       if (Internalize) {
366         PM.add(createInternalizePass(mustPreserveGV));
367         PM.add(createGlobalDCEPass());
368       }
369       if (EarlyInline)
370         PM.add(createAMDGPUAlwaysInlinePass(false));
371   });
372 
373   Builder.addExtension(
374     PassManagerBuilder::EP_EarlyAsPossible,
375     [AMDGPUAA, LibCallSimplify](const PassManagerBuilder &,
376                                 legacy::PassManagerBase &PM) {
377       if (AMDGPUAA) {
378         PM.add(createAMDGPUAAWrapperPass());
379         PM.add(createAMDGPUExternalAAWrapperPass());
380       }
381       PM.add(llvm::createAMDGPUUseNativeCallsPass());
382       if (LibCallSimplify)
383         PM.add(llvm::createAMDGPUSimplifyLibCallsPass());
384   });
385 
386   Builder.addExtension(
387     PassManagerBuilder::EP_CGSCCOptimizerLate,
388     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
389       // Add infer address spaces pass to the opt pipeline after inlining
390       // but before SROA to increase SROA opportunities.
391       PM.add(createInferAddressSpacesPass());
392   });
393 }
394 
395 //===----------------------------------------------------------------------===//
396 // R600 Target Machine (R600 -> Cayman)
397 //===----------------------------------------------------------------------===//
398 
399 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
400                                      StringRef CPU, StringRef FS,
401                                      TargetOptions Options,
402                                      Optional<Reloc::Model> RM,
403                                      Optional<CodeModel::Model> CM,
404                                      CodeGenOpt::Level OL, bool JIT)
405     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
406   setRequiresStructuredCFG(true);
407 }
408 
409 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
410   const Function &F) const {
411   StringRef GPU = getGPUName(F);
412   StringRef FS = getFeatureString(F);
413 
414   SmallString<128> SubtargetKey(GPU);
415   SubtargetKey.append(FS);
416 
417   auto &I = SubtargetMap[SubtargetKey];
418   if (!I) {
419     // This needs to be done before we create a new subtarget since any
420     // creation will depend on the TM and the code generation flags on the
421     // function that reside in TargetOptions.
422     resetTargetOptions(F);
423     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
424   }
425 
426   return I.get();
427 }
428 
429 //===----------------------------------------------------------------------===//
430 // GCN Target Machine (SI+)
431 //===----------------------------------------------------------------------===//
432 
433 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
434                                    StringRef CPU, StringRef FS,
435                                    TargetOptions Options,
436                                    Optional<Reloc::Model> RM,
437                                    Optional<CodeModel::Model> CM,
438                                    CodeGenOpt::Level OL, bool JIT)
439     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
440 
441 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
442   StringRef GPU = getGPUName(F);
443   StringRef FS = getFeatureString(F);
444 
445   SmallString<128> SubtargetKey(GPU);
446   SubtargetKey.append(FS);
447 
448   auto &I = SubtargetMap[SubtargetKey];
449   if (!I) {
450     // This needs to be done before we create a new subtarget since any
451     // creation will depend on the TM and the code generation flags on the
452     // function that reside in TargetOptions.
453     resetTargetOptions(F);
454     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
455   }
456 
457   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
458 
459   return I.get();
460 }
461 
462 //===----------------------------------------------------------------------===//
463 // AMDGPU Pass Setup
464 //===----------------------------------------------------------------------===//
465 
466 namespace {
467 
468 class AMDGPUPassConfig : public TargetPassConfig {
469 public:
470   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
471     : TargetPassConfig(TM, PM) {
472     // Exceptions and StackMaps are not supported, so these passes will never do
473     // anything.
474     disablePass(&StackMapLivenessID);
475     disablePass(&FuncletLayoutID);
476   }
477 
478   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
479     return getTM<AMDGPUTargetMachine>();
480   }
481 
482   ScheduleDAGInstrs *
483   createMachineScheduler(MachineSchedContext *C) const override {
484     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
485     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
486     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
487     return DAG;
488   }
489 
490   void addEarlyCSEOrGVNPass();
491   void addStraightLineScalarOptimizationPasses();
492   void addIRPasses() override;
493   void addCodeGenPrepare() override;
494   bool addPreISel() override;
495   bool addInstSelector() override;
496   bool addGCPasses() override;
497 };
498 
499 class R600PassConfig final : public AMDGPUPassConfig {
500 public:
501   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
502     : AMDGPUPassConfig(TM, PM) {}
503 
504   ScheduleDAGInstrs *createMachineScheduler(
505     MachineSchedContext *C) const override {
506     return createR600MachineScheduler(C);
507   }
508 
509   bool addPreISel() override;
510   bool addInstSelector() override;
511   void addPreRegAlloc() override;
512   void addPreSched2() override;
513   void addPreEmitPass() override;
514 };
515 
516 class GCNPassConfig final : public AMDGPUPassConfig {
517 public:
518   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
519     : AMDGPUPassConfig(TM, PM) {
520     // It is necessary to know the register usage of the entire call graph.  We
521     // allow calls without EnableAMDGPUFunctionCalls if they are marked
522     // noinline, so this is always required.
523     setRequiresCodeGenSCCOrder(true);
524   }
525 
526   GCNTargetMachine &getGCNTargetMachine() const {
527     return getTM<GCNTargetMachine>();
528   }
529 
530   ScheduleDAGInstrs *
531   createMachineScheduler(MachineSchedContext *C) const override;
532 
533   bool addPreISel() override;
534   void addMachineSSAOptimization() override;
535   bool addILPOpts() override;
536   bool addInstSelector() override;
537   bool addIRTranslator() override;
538   bool addLegalizeMachineIR() override;
539   bool addRegBankSelect() override;
540   bool addGlobalInstructionSelect() override;
541   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
542   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
543   void addPreRegAlloc() override;
544   void addPostRegAlloc() override;
545   void addPreSched2() override;
546   void addPreEmitPass() override;
547 };
548 
549 } // end anonymous namespace
550 
551 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
552   return TargetIRAnalysis([this](const Function &F) {
553     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
554   });
555 }
556 
557 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
558   if (getOptLevel() == CodeGenOpt::Aggressive)
559     addPass(createGVNPass());
560   else
561     addPass(createEarlyCSEPass());
562 }
563 
564 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
565   addPass(createSeparateConstOffsetFromGEPPass());
566   addPass(createSpeculativeExecutionPass());
567   // ReassociateGEPs exposes more opportunites for SLSR. See
568   // the example in reassociate-geps-and-slsr.ll.
569   addPass(createStraightLineStrengthReducePass());
570   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
571   // EarlyCSE can reuse.
572   addEarlyCSEOrGVNPass();
573   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
574   addPass(createNaryReassociatePass());
575   // NaryReassociate on GEPs creates redundant common expressions, so run
576   // EarlyCSE after it.
577   addPass(createEarlyCSEPass());
578 }
579 
580 void AMDGPUPassConfig::addIRPasses() {
581   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
582 
583   // There is no reason to run these.
584   disablePass(&StackMapLivenessID);
585   disablePass(&FuncletLayoutID);
586   disablePass(&PatchableFunctionID);
587 
588   addPass(createAMDGPULowerIntrinsicsPass());
589 
590   if (TM.getTargetTriple().getArch() == Triple::r600 ||
591       !EnableAMDGPUFunctionCalls) {
592     // Function calls are not supported, so make sure we inline everything.
593     addPass(createAMDGPUAlwaysInlinePass());
594     addPass(createAlwaysInlinerLegacyPass());
595     // We need to add the barrier noop pass, otherwise adding the function
596     // inlining pass will cause all of the PassConfigs passes to be run
597     // one function at a time, which means if we have a nodule with two
598     // functions, then we will generate code for the first function
599     // without ever running any passes on the second.
600     addPass(createBarrierNoopPass());
601   }
602 
603   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
604     // TODO: May want to move later or split into an early and late one.
605 
606     addPass(createAMDGPUCodeGenPreparePass());
607   }
608 
609   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
610   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
611 
612   if (TM.getOptLevel() > CodeGenOpt::None) {
613     addPass(createInferAddressSpacesPass());
614     addPass(createAMDGPUPromoteAlloca());
615 
616     if (EnableSROA)
617       addPass(createSROAPass());
618 
619     addStraightLineScalarOptimizationPasses();
620 
621     if (EnableAMDGPUAliasAnalysis) {
622       addPass(createAMDGPUAAWrapperPass());
623       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
624                                              AAResults &AAR) {
625         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
626           AAR.addAAResult(WrapperPass->getResult());
627         }));
628     }
629   }
630 
631   TargetPassConfig::addIRPasses();
632 
633   // EarlyCSE is not always strong enough to clean up what LSR produces. For
634   // example, GVN can combine
635   //
636   //   %0 = add %a, %b
637   //   %1 = add %b, %a
638   //
639   // and
640   //
641   //   %0 = shl nsw %a, 2
642   //   %1 = shl %a, 2
643   //
644   // but EarlyCSE can do neither of them.
645   if (getOptLevel() != CodeGenOpt::None)
646     addEarlyCSEOrGVNPass();
647 }
648 
649 void AMDGPUPassConfig::addCodeGenPrepare() {
650   TargetPassConfig::addCodeGenPrepare();
651 
652   if (EnableLoadStoreVectorizer)
653     addPass(createLoadStoreVectorizerPass());
654 }
655 
656 bool AMDGPUPassConfig::addPreISel() {
657   addPass(createFlattenCFGPass());
658   return false;
659 }
660 
661 bool AMDGPUPassConfig::addInstSelector() {
662   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
663   return false;
664 }
665 
666 bool AMDGPUPassConfig::addGCPasses() {
667   // Do nothing. GC is not supported.
668   return false;
669 }
670 
671 //===----------------------------------------------------------------------===//
672 // R600 Pass Setup
673 //===----------------------------------------------------------------------===//
674 
675 bool R600PassConfig::addPreISel() {
676   AMDGPUPassConfig::addPreISel();
677 
678   if (EnableR600StructurizeCFG)
679     addPass(createStructurizeCFGPass());
680   return false;
681 }
682 
683 bool R600PassConfig::addInstSelector() {
684   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
685   return false;
686 }
687 
688 void R600PassConfig::addPreRegAlloc() {
689   addPass(createR600VectorRegMerger());
690 }
691 
692 void R600PassConfig::addPreSched2() {
693   addPass(createR600EmitClauseMarkers(), false);
694   if (EnableR600IfConvert)
695     addPass(&IfConverterID, false);
696   addPass(createR600ClauseMergePass(), false);
697 }
698 
699 void R600PassConfig::addPreEmitPass() {
700   addPass(createAMDGPUCFGStructurizerPass(), false);
701   addPass(createR600ExpandSpecialInstrsPass(), false);
702   addPass(&FinalizeMachineBundlesID, false);
703   addPass(createR600Packetizer(), false);
704   addPass(createR600ControlFlowFinalizer(), false);
705 }
706 
707 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
708   return new R600PassConfig(*this, PM);
709 }
710 
711 //===----------------------------------------------------------------------===//
712 // GCN Pass Setup
713 //===----------------------------------------------------------------------===//
714 
715 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
716   MachineSchedContext *C) const {
717   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
718   if (ST.enableSIScheduler())
719     return createSIMachineScheduler(C);
720   return createGCNMaxOccupancyMachineScheduler(C);
721 }
722 
723 bool GCNPassConfig::addPreISel() {
724   AMDGPUPassConfig::addPreISel();
725 
726   // FIXME: We need to run a pass to propagate the attributes when calls are
727   // supported.
728   addPass(createAMDGPUAnnotateKernelFeaturesPass());
729 
730   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
731   // regions formed by them.
732   addPass(&AMDGPUUnifyDivergentExitNodesID);
733   if (!LateCFGStructurize) {
734     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
735   }
736   addPass(createSinkingPass());
737   addPass(createAMDGPUAnnotateUniformValues());
738   if (!LateCFGStructurize) {
739     addPass(createSIAnnotateControlFlowPass());
740   }
741 
742   return false;
743 }
744 
745 void GCNPassConfig::addMachineSSAOptimization() {
746   TargetPassConfig::addMachineSSAOptimization();
747 
748   // We want to fold operands after PeepholeOptimizer has run (or as part of
749   // it), because it will eliminate extra copies making it easier to fold the
750   // real source operand. We want to eliminate dead instructions after, so that
751   // we see fewer uses of the copies. We then need to clean up the dead
752   // instructions leftover after the operands are folded as well.
753   //
754   // XXX - Can we get away without running DeadMachineInstructionElim again?
755   addPass(&SIFoldOperandsID);
756   addPass(&DeadMachineInstructionElimID);
757   addPass(&SILoadStoreOptimizerID);
758   if (EnableSDWAPeephole) {
759     addPass(&SIPeepholeSDWAID);
760     addPass(&MachineLICMID);
761     addPass(&MachineCSEID);
762     addPass(&SIFoldOperandsID);
763     addPass(&DeadMachineInstructionElimID);
764   }
765   addPass(createSIShrinkInstructionsPass());
766 }
767 
768 bool GCNPassConfig::addILPOpts() {
769   if (EnableEarlyIfConversion)
770     addPass(&EarlyIfConverterID);
771 
772   TargetPassConfig::addILPOpts();
773   return false;
774 }
775 
776 bool GCNPassConfig::addInstSelector() {
777   AMDGPUPassConfig::addInstSelector();
778   addPass(createSILowerI1CopiesPass());
779   addPass(&SIFixSGPRCopiesID);
780   return false;
781 }
782 
783 bool GCNPassConfig::addIRTranslator() {
784   addPass(new IRTranslator());
785   return false;
786 }
787 
788 bool GCNPassConfig::addLegalizeMachineIR() {
789   addPass(new Legalizer());
790   return false;
791 }
792 
793 bool GCNPassConfig::addRegBankSelect() {
794   addPass(new RegBankSelect());
795   return false;
796 }
797 
798 bool GCNPassConfig::addGlobalInstructionSelect() {
799   addPass(new InstructionSelect());
800   return false;
801 }
802 
803 void GCNPassConfig::addPreRegAlloc() {
804   if (LateCFGStructurize) {
805     addPass(createAMDGPUMachineCFGStructurizerPass());
806   }
807   addPass(createSIWholeQuadModePass());
808 }
809 
810 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
811   // FIXME: We have to disable the verifier here because of PHIElimination +
812   // TwoAddressInstructions disabling it.
813 
814   // This must be run immediately after phi elimination and before
815   // TwoAddressInstructions, otherwise the processing of the tied operand of
816   // SI_ELSE will introduce a copy of the tied operand source after the else.
817   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
818 
819   // This must be run after SILowerControlFlow, since it needs to use the
820   // machine-level CFG, but before register allocation.
821   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
822 
823   TargetPassConfig::addFastRegAlloc(RegAllocPass);
824 }
825 
826 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
827   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
828 
829   // This must be run immediately after phi elimination and before
830   // TwoAddressInstructions, otherwise the processing of the tied operand of
831   // SI_ELSE will introduce a copy of the tied operand source after the else.
832   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
833 
834   // This must be run after SILowerControlFlow, since it needs to use the
835   // machine-level CFG, but before register allocation.
836   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
837 
838   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
839 }
840 
841 void GCNPassConfig::addPostRegAlloc() {
842   addPass(&SIFixVGPRCopiesID);
843   addPass(&SIOptimizeExecMaskingID);
844   TargetPassConfig::addPostRegAlloc();
845 }
846 
847 void GCNPassConfig::addPreSched2() {
848 }
849 
850 void GCNPassConfig::addPreEmitPass() {
851   // The hazard recognizer that runs as part of the post-ra scheduler does not
852   // guarantee to be able handle all hazards correctly. This is because if there
853   // are multiple scheduling regions in a basic block, the regions are scheduled
854   // bottom up, so when we begin to schedule a region we don't know what
855   // instructions were emitted directly before it.
856   //
857   // Here we add a stand-alone hazard recognizer pass which can handle all
858   // cases.
859   addPass(&PostRAHazardRecognizerID);
860 
861   if (EnableSIInsertWaitcntsPass)
862     addPass(createSIInsertWaitcntsPass());
863   else
864     addPass(createSIInsertWaitsPass());
865   addPass(createSIShrinkInstructionsPass());
866   addPass(&SIInsertSkipsPassID);
867   addPass(createSIMemoryLegalizerPass());
868   addPass(createSIDebuggerInsertNopsPass());
869   addPass(&BranchRelaxationPassID);
870 }
871 
872 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
873   return new GCNPassConfig(*this, PM);
874 }
875 
876