1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPUTargetObjectFile.h"
18 #include "AMDGPU.h"
19 #include "AMDGPUTargetTransformInfo.h"
20 #include "R600ISelLowering.h"
21 #include "R600InstrInfo.h"
22 #include "R600MachineScheduler.h"
23 #include "SIISelLowering.h"
24 #include "SIInstrInfo.h"
25 #include "llvm/Analysis/Passes.h"
26 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/IR/Verifier.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/IR/LegacyPassManager.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/TargetRegistry.h"
35 #include "llvm/Support/raw_os_ostream.h"
36 #include "llvm/Transforms/IPO.h"
37 #include "llvm/Transforms/Scalar.h"
38 #include <llvm/CodeGen/Passes.h>
39 
40 using namespace llvm;
41 
42 extern "C" void LLVMInitializeAMDGPUTarget() {
43   // Register the target
44   RegisterTargetMachine<R600TargetMachine> X(TheAMDGPUTarget);
45   RegisterTargetMachine<GCNTargetMachine> Y(TheGCNTarget);
46 
47   PassRegistry *PR = PassRegistry::getPassRegistry();
48   initializeSILowerI1CopiesPass(*PR);
49   initializeSIFixSGPRCopiesPass(*PR);
50   initializeSIFoldOperandsPass(*PR);
51   initializeSIFixSGPRLiveRangesPass(*PR);
52   initializeSIFixControlFlowLiveIntervalsPass(*PR);
53   initializeSILoadStoreOptimizerPass(*PR);
54   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
55   initializeAMDGPUAnnotateUniformValuesPass(*PR);
56   initializeAMDGPUPromoteAllocaPass(*PR);
57   initializeSIAnnotateControlFlowPass(*PR);
58   initializeSIInsertNopsPass(*PR);
59   initializeSIInsertWaitsPass(*PR);
60   initializeSILowerControlFlowPass(*PR);
61 }
62 
63 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
64   if (TT.getOS() == Triple::AMDHSA)
65     return make_unique<AMDGPUHSATargetObjectFile>();
66 
67   return make_unique<AMDGPUTargetObjectFile>();
68 }
69 
70 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
71   return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
72 }
73 
74 static MachineSchedRegistry
75 R600SchedRegistry("r600", "Run R600's custom scheduler",
76                    createR600MachineScheduler);
77 
78 static MachineSchedRegistry
79 SISchedRegistry("si", "Run SI's custom scheduler",
80                 createSIMachineScheduler);
81 
82 static std::string computeDataLayout(const Triple &TT) {
83   std::string Ret = "e-p:32:32";
84 
85   if (TT.getArch() == Triple::amdgcn) {
86     // 32-bit private, local, and region pointers. 64-bit global and constant.
87     Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
88   }
89 
90   Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
91          "-v512:512-v1024:1024-v2048:2048-n32:64";
92 
93   return Ret;
94 }
95 
96 LLVM_READNONE
97 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
98   if (!GPU.empty())
99     return GPU;
100 
101   // HSA only supports CI+, so change the default GPU to a CI for HSA.
102   if (TT.getArch() == Triple::amdgcn)
103     return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
104 
105   return "";
106 }
107 
108 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
109                                          StringRef CPU, StringRef FS,
110                                          TargetOptions Options, Reloc::Model RM,
111                                          CodeModel::Model CM,
112                                          CodeGenOpt::Level OptLevel)
113     : LLVMTargetMachine(T, computeDataLayout(TT), TT,
114                         getGPUOrDefault(TT, CPU), FS, Options, RM, CM,
115                         OptLevel),
116       TLOF(createTLOF(getTargetTriple())),
117       Subtarget(TT, getTargetCPU(), FS, *this),
118       IntrinsicInfo() {
119   setRequiresStructuredCFG(true);
120   initAsmInfo();
121 }
122 
123 AMDGPUTargetMachine::~AMDGPUTargetMachine() { }
124 
125 //===----------------------------------------------------------------------===//
126 // R600 Target Machine (R600 -> Cayman)
127 //===----------------------------------------------------------------------===//
128 
129 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
130                                      StringRef CPU, StringRef FS,
131                                      TargetOptions Options, Reloc::Model RM,
132                                      CodeModel::Model CM, CodeGenOpt::Level OL)
133     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
134 
135 //===----------------------------------------------------------------------===//
136 // GCN Target Machine (SI+)
137 //===----------------------------------------------------------------------===//
138 
139 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
140                                    StringRef CPU, StringRef FS,
141                                    TargetOptions Options, Reloc::Model RM,
142                                    CodeModel::Model CM, CodeGenOpt::Level OL)
143     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
144 
145 //===----------------------------------------------------------------------===//
146 // AMDGPU Pass Setup
147 //===----------------------------------------------------------------------===//
148 
149 namespace {
150 
151 cl::opt<bool> InsertNops(
152   "amdgpu-insert-nops",
153   cl::desc("Insert two nop instructions for each high level source statement"),
154   cl::init(false));
155 
156 class AMDGPUPassConfig : public TargetPassConfig {
157 public:
158   AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
159     : TargetPassConfig(TM, PM) {
160 
161     // Exceptions and StackMaps are not supported, so these passes will never do
162     // anything.
163     disablePass(&StackMapLivenessID);
164     disablePass(&FuncletLayoutID);
165   }
166 
167   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
168     return getTM<AMDGPUTargetMachine>();
169   }
170 
171   ScheduleDAGInstrs *
172   createMachineScheduler(MachineSchedContext *C) const override {
173     const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
174     if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
175       return createR600MachineScheduler(C);
176     else if (ST.enableSIScheduler())
177       return createSIMachineScheduler(C);
178     return nullptr;
179   }
180 
181   void addIRPasses() override;
182   void addCodeGenPrepare() override;
183   bool addPreISel() override;
184   bool addInstSelector() override;
185   bool addGCPasses() override;
186 };
187 
188 class R600PassConfig : public AMDGPUPassConfig {
189 public:
190   R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
191     : AMDGPUPassConfig(TM, PM) { }
192 
193   bool addPreISel() override;
194   void addPreRegAlloc() override;
195   void addPreSched2() override;
196   void addPreEmitPass() override;
197 };
198 
199 class GCNPassConfig : public AMDGPUPassConfig {
200 public:
201   GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
202     : AMDGPUPassConfig(TM, PM) { }
203   bool addPreISel() override;
204   bool addInstSelector() override;
205   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
206   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
207   void addPreRegAlloc() override;
208   void addPostRegAlloc() override;
209   void addPreSched2() override;
210   void addPreEmitPass() override;
211 };
212 
213 } // End of anonymous namespace
214 
215 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
216   return TargetIRAnalysis([this](const Function &F) {
217     return TargetTransformInfo(
218         AMDGPUTTIImpl(this, F.getParent()->getDataLayout()));
219   });
220 }
221 
222 void AMDGPUPassConfig::addIRPasses() {
223   // Function calls are not supported, so make sure we inline everything.
224   addPass(createAMDGPUAlwaysInlinePass());
225   addPass(createAlwaysInlinerPass());
226   // We need to add the barrier noop pass, otherwise adding the function
227   // inlining pass will cause all of the PassConfigs passes to be run
228   // one function at a time, which means if we have a nodule with two
229   // functions, then we will generate code for the first function
230   // without ever running any passes on the second.
231   addPass(createBarrierNoopPass());
232 
233   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
234   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
235 
236   TargetPassConfig::addIRPasses();
237 }
238 
239 void AMDGPUPassConfig::addCodeGenPrepare() {
240   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
241   const AMDGPUSubtarget &ST = *TM.getSubtargetImpl();
242   if (TM.getOptLevel() > CodeGenOpt::None && ST.isPromoteAllocaEnabled()) {
243     addPass(createAMDGPUPromoteAlloca(&TM));
244     addPass(createSROAPass());
245   }
246   TargetPassConfig::addCodeGenPrepare();
247 }
248 
249 bool
250 AMDGPUPassConfig::addPreISel() {
251   addPass(createFlattenCFGPass());
252   return false;
253 }
254 
255 bool AMDGPUPassConfig::addInstSelector() {
256   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
257   return false;
258 }
259 
260 bool AMDGPUPassConfig::addGCPasses() {
261   // Do nothing. GC is not supported.
262   return false;
263 }
264 
265 //===----------------------------------------------------------------------===//
266 // R600 Pass Setup
267 //===----------------------------------------------------------------------===//
268 
269 bool R600PassConfig::addPreISel() {
270   AMDGPUPassConfig::addPreISel();
271   const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
272   if (ST.IsIRStructurizerEnabled())
273     addPass(createStructurizeCFGPass());
274   addPass(createR600TextureIntrinsicsReplacer());
275   return false;
276 }
277 
278 void R600PassConfig::addPreRegAlloc() {
279   addPass(createR600VectorRegMerger(*TM));
280 }
281 
282 void R600PassConfig::addPreSched2() {
283   const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
284   addPass(createR600EmitClauseMarkers(), false);
285   if (ST.isIfCvtEnabled())
286     addPass(&IfConverterID, false);
287   addPass(createR600ClauseMergePass(*TM), false);
288 }
289 
290 void R600PassConfig::addPreEmitPass() {
291   addPass(createAMDGPUCFGStructurizerPass(), false);
292   addPass(createR600ExpandSpecialInstrsPass(*TM), false);
293   addPass(&FinalizeMachineBundlesID, false);
294   addPass(createR600Packetizer(*TM), false);
295   addPass(createR600ControlFlowFinalizer(*TM), false);
296 }
297 
298 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
299   return new R600PassConfig(this, PM);
300 }
301 
302 //===----------------------------------------------------------------------===//
303 // GCN Pass Setup
304 //===----------------------------------------------------------------------===//
305 
306 bool GCNPassConfig::addPreISel() {
307   AMDGPUPassConfig::addPreISel();
308 
309   // FIXME: We need to run a pass to propagate the attributes when calls are
310   // supported.
311   addPass(&AMDGPUAnnotateKernelFeaturesID);
312   addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
313   addPass(createSinkingPass());
314   addPass(createSITypeRewriter());
315   addPass(createAMDGPUAnnotateUniformValues());
316   addPass(createSIAnnotateControlFlowPass());
317 
318   return false;
319 }
320 
321 bool GCNPassConfig::addInstSelector() {
322   AMDGPUPassConfig::addInstSelector();
323   addPass(createSILowerI1CopiesPass());
324   addPass(&SIFixSGPRCopiesID);
325   addPass(createSIFoldOperandsPass());
326   return false;
327 }
328 
329 void GCNPassConfig::addPreRegAlloc() {
330   const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
331 
332   // This needs to be run directly before register allocation because
333   // earlier passes might recompute live intervals.
334   // TODO: handle CodeGenOpt::None; fast RA ignores spill weights set by the pass
335   if (getOptLevel() > CodeGenOpt::None) {
336     insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
337   }
338 
339   if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {
340     // Don't do this with no optimizations since it throws away debug info by
341     // merging nonadjacent loads.
342 
343     // This should be run after scheduling, but before register allocation. It
344     // also need extra copies to the address operand to be eliminated.
345     insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
346     insertPass(&MachineSchedulerID, &RegisterCoalescerID);
347   }
348   addPass(createSIShrinkInstructionsPass(), false);
349 }
350 
351 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
352   addPass(&SIFixSGPRLiveRangesID);
353   TargetPassConfig::addFastRegAlloc(RegAllocPass);
354 }
355 
356 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
357   // We want to run this after LiveVariables is computed to avoid computing them
358   // twice.
359   // FIXME: We shouldn't disable the verifier here. r249087 introduced a failure
360   // that needs to be fixed.
361   insertPass(&LiveVariablesID, &SIFixSGPRLiveRangesID, /*VerifyAfter=*/false);
362   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
363 }
364 
365 void GCNPassConfig::addPostRegAlloc() {
366   addPass(createSIShrinkInstructionsPass(), false);
367 }
368 
369 void GCNPassConfig::addPreSched2() {
370 }
371 
372 void GCNPassConfig::addPreEmitPass() {
373   addPass(createSIInsertWaitsPass(), false);
374   addPass(createSILowerControlFlowPass(), false);
375   if (InsertNops) {
376     addPass(createSIInsertNopsPass(), false);
377   }
378 }
379 
380 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
381   return new GCNPassConfig(this, PM);
382 }
383