1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600MachineScheduler.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIMachineScheduler.h"
27 #include "TargetInfo/AMDGPUTargetInfo.h"
28 #include "llvm/Analysis/CGSCCPassManager.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/Localizer.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MIRParser/MIParser.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/LegacyPassManager.h"
37 #include "llvm/IR/PassManager.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/Passes/PassBuilder.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Transforms/IPO.h"
42 #include "llvm/Transforms/IPO/AlwaysInliner.h"
43 #include "llvm/Transforms/IPO/GlobalDCE.h"
44 #include "llvm/Transforms/IPO/Internalize.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
49 #include "llvm/Transforms/Utils.h"
50 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
51 #include "llvm/Transforms/Vectorize.h"
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73             cl::desc("Run pre-RA exec mask optimizations"),
74             cl::init(true));
75 
76 static cl::opt<bool> EnableR600IfConvert(
77   "r600-if-convert",
78   cl::desc("Use if conversion pass"),
79   cl::ReallyHidden,
80   cl::init(true));
81 
82 // Option to disable vectorizer for tests.
83 static cl::opt<bool> EnableLoadStoreVectorizer(
84   "amdgpu-load-store-vectorizer",
85   cl::desc("Enable load store vectorizer"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to control global loads scalarization
90 static cl::opt<bool> ScalarizeGlobal(
91   "amdgpu-scalarize-global-loads",
92   cl::desc("Enable global load scalarization"),
93   cl::init(true),
94   cl::Hidden);
95 
96 // Option to run internalize pass.
97 static cl::opt<bool> InternalizeSymbols(
98   "amdgpu-internalize-symbols",
99   cl::desc("Enable elimination of non-kernel functions and unused globals"),
100   cl::init(false),
101   cl::Hidden);
102 
103 // Option to inline all early.
104 static cl::opt<bool> EarlyInlineAll(
105   "amdgpu-early-inline-all",
106   cl::desc("Inline all functions early"),
107   cl::init(false),
108   cl::Hidden);
109 
110 static cl::opt<bool> EnableSDWAPeephole(
111   "amdgpu-sdwa-peephole",
112   cl::desc("Enable SDWA peepholer"),
113   cl::init(true));
114 
115 static cl::opt<bool> EnableDPPCombine(
116   "amdgpu-dpp-combine",
117   cl::desc("Enable DPP combiner"),
118   cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122   cl::desc("Enable AMDGPU Alias Analysis"),
123   cl::init(true));
124 
125 // Option to run late CFG structurizer
126 static cl::opt<bool, true> LateCFGStructurize(
127   "amdgpu-late-structurize",
128   cl::desc("Enable late CFG structurization"),
129   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
130   cl::Hidden);
131 
132 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
133   "amdgpu-function-calls",
134   cl::desc("Enable AMDGPU function call support"),
135   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
136   cl::init(true),
137   cl::Hidden);
138 
139 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
140   "amdgpu-fixed-function-abi",
141   cl::desc("Enable all implicit function arguments"),
142   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
143   cl::init(false),
144   cl::Hidden);
145 
146 // Enable lib calls simplifications
147 static cl::opt<bool> EnableLibCallSimplify(
148   "amdgpu-simplify-libcall",
149   cl::desc("Enable amdgpu library simplifications"),
150   cl::init(true),
151   cl::Hidden);
152 
153 static cl::opt<bool> EnableLowerKernelArguments(
154   "amdgpu-ir-lower-kernel-arguments",
155   cl::desc("Lower kernel argument loads in IR pass"),
156   cl::init(true),
157   cl::Hidden);
158 
159 static cl::opt<bool> EnableRegReassign(
160   "amdgpu-reassign-regs",
161   cl::desc("Enable register reassign optimizations on gfx10+"),
162   cl::init(true),
163   cl::Hidden);
164 
165 // Enable atomic optimization
166 static cl::opt<bool> EnableAtomicOptimizations(
167   "amdgpu-atomic-optimizations",
168   cl::desc("Enable atomic optimizations"),
169   cl::init(false),
170   cl::Hidden);
171 
172 // Enable Mode register optimization
173 static cl::opt<bool> EnableSIModeRegisterPass(
174   "amdgpu-mode-register",
175   cl::desc("Enable mode register pass"),
176   cl::init(true),
177   cl::Hidden);
178 
179 // Option is used in lit tests to prevent deadcoding of patterns inspected.
180 static cl::opt<bool>
181 EnableDCEInRA("amdgpu-dce-in-ra",
182     cl::init(true), cl::Hidden,
183     cl::desc("Enable machine DCE inside regalloc"));
184 
185 static cl::opt<bool> EnableScalarIRPasses(
186   "amdgpu-scalar-ir-passes",
187   cl::desc("Enable scalar IR passes"),
188   cl::init(true),
189   cl::Hidden);
190 
191 static cl::opt<bool> EnableStructurizerWorkarounds(
192     "amdgpu-enable-structurizer-workarounds",
193     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
194     cl::Hidden);
195 
196 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
197   // Register the target
198   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
199   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
200 
201   PassRegistry *PR = PassRegistry::getPassRegistry();
202   initializeR600ClauseMergePassPass(*PR);
203   initializeR600ControlFlowFinalizerPass(*PR);
204   initializeR600PacketizerPass(*PR);
205   initializeR600ExpandSpecialInstrsPassPass(*PR);
206   initializeR600VectorRegMergerPass(*PR);
207   initializeGlobalISel(*PR);
208   initializeAMDGPUDAGToDAGISelPass(*PR);
209   initializeGCNDPPCombinePass(*PR);
210   initializeSILowerI1CopiesPass(*PR);
211   initializeSILowerSGPRSpillsPass(*PR);
212   initializeSIFixSGPRCopiesPass(*PR);
213   initializeSIFixVGPRCopiesPass(*PR);
214   initializeSIFoldOperandsPass(*PR);
215   initializeSIPeepholeSDWAPass(*PR);
216   initializeSIShrinkInstructionsPass(*PR);
217   initializeSIOptimizeExecMaskingPreRAPass(*PR);
218   initializeSILoadStoreOptimizerPass(*PR);
219   initializeAMDGPUFixFunctionBitcastsPass(*PR);
220   initializeAMDGPUAlwaysInlinePass(*PR);
221   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
222   initializeAMDGPUAnnotateUniformValuesPass(*PR);
223   initializeAMDGPUArgumentUsageInfoPass(*PR);
224   initializeAMDGPUAtomicOptimizerPass(*PR);
225   initializeAMDGPULowerKernelArgumentsPass(*PR);
226   initializeAMDGPULowerKernelAttributesPass(*PR);
227   initializeAMDGPULowerIntrinsicsPass(*PR);
228   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
229   initializeAMDGPUPostLegalizerCombinerPass(*PR);
230   initializeAMDGPUPreLegalizerCombinerPass(*PR);
231   initializeAMDGPUPromoteAllocaPass(*PR);
232   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
233   initializeAMDGPUCodeGenPreparePass(*PR);
234   initializeAMDGPULateCodeGenPreparePass(*PR);
235   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
236   initializeAMDGPUPropagateAttributesLatePass(*PR);
237   initializeAMDGPURewriteOutArgumentsPass(*PR);
238   initializeAMDGPUUnifyMetadataPass(*PR);
239   initializeSIAnnotateControlFlowPass(*PR);
240   initializeSIInsertHardClausesPass(*PR);
241   initializeSIInsertWaitcntsPass(*PR);
242   initializeSIModeRegisterPass(*PR);
243   initializeSIWholeQuadModePass(*PR);
244   initializeSILowerControlFlowPass(*PR);
245   initializeSIRemoveShortExecBranchesPass(*PR);
246   initializeSIPreEmitPeepholePass(*PR);
247   initializeSIInsertSkipsPass(*PR);
248   initializeSIMemoryLegalizerPass(*PR);
249   initializeSIOptimizeExecMaskingPass(*PR);
250   initializeSIPreAllocateWWMRegsPass(*PR);
251   initializeSIFormMemoryClausesPass(*PR);
252   initializeSIPostRABundlerPass(*PR);
253   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
254   initializeAMDGPUAAWrapperPassPass(*PR);
255   initializeAMDGPUExternalAAWrapperPass(*PR);
256   initializeAMDGPUUseNativeCallsPass(*PR);
257   initializeAMDGPUSimplifyLibCallsPass(*PR);
258   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
259   initializeGCNRegBankReassignPass(*PR);
260   initializeGCNNSAReassignPass(*PR);
261   initializeSIAddIMGInitPass(*PR);
262 }
263 
264 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
265   return std::make_unique<AMDGPUTargetObjectFile>();
266 }
267 
268 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
269   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
270 }
271 
272 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
273   return new SIScheduleDAGMI(C);
274 }
275 
276 static ScheduleDAGInstrs *
277 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
278   ScheduleDAGMILive *DAG =
279     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
280   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
281   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
282   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
283   return DAG;
284 }
285 
286 static ScheduleDAGInstrs *
287 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
288   auto DAG = new GCNIterativeScheduler(C,
289     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
290   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
291   return DAG;
292 }
293 
294 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
295   return new GCNIterativeScheduler(C,
296     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
297 }
298 
299 static ScheduleDAGInstrs *
300 createIterativeILPMachineScheduler(MachineSchedContext *C) {
301   auto DAG = new GCNIterativeScheduler(C,
302     GCNIterativeScheduler::SCHEDULE_ILP);
303   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
304   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
305   return DAG;
306 }
307 
308 static MachineSchedRegistry
309 R600SchedRegistry("r600", "Run R600's custom scheduler",
310                    createR600MachineScheduler);
311 
312 static MachineSchedRegistry
313 SISchedRegistry("si", "Run SI's custom scheduler",
314                 createSIMachineScheduler);
315 
316 static MachineSchedRegistry
317 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
318                              "Run GCN scheduler to maximize occupancy",
319                              createGCNMaxOccupancyMachineScheduler);
320 
321 static MachineSchedRegistry
322 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
323   "Run GCN scheduler to maximize occupancy (experimental)",
324   createIterativeGCNMaxOccupancyMachineScheduler);
325 
326 static MachineSchedRegistry
327 GCNMinRegSchedRegistry("gcn-minreg",
328   "Run GCN iterative scheduler for minimal register usage (experimental)",
329   createMinRegScheduler);
330 
331 static MachineSchedRegistry
332 GCNILPSchedRegistry("gcn-ilp",
333   "Run GCN iterative scheduler for ILP scheduling (experimental)",
334   createIterativeILPMachineScheduler);
335 
336 static StringRef computeDataLayout(const Triple &TT) {
337   if (TT.getArch() == Triple::r600) {
338     // 32-bit pointers.
339     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
340            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
341   }
342 
343   // 32-bit private, local, and region pointers. 64-bit global, constant and
344   // flat, non-integral buffer fat pointers.
345   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
346          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
347          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
348          "-ni:7";
349 }
350 
351 LLVM_READNONE
352 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
353   if (!GPU.empty())
354     return GPU;
355 
356   // Need to default to a target with flat support for HSA.
357   if (TT.getArch() == Triple::amdgcn)
358     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
359 
360   return "r600";
361 }
362 
363 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
364   // The AMDGPU toolchain only supports generating shared objects, so we
365   // must always use PIC.
366   return Reloc::PIC_;
367 }
368 
369 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
370                                          StringRef CPU, StringRef FS,
371                                          TargetOptions Options,
372                                          Optional<Reloc::Model> RM,
373                                          Optional<CodeModel::Model> CM,
374                                          CodeGenOpt::Level OptLevel)
375     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
376                         FS, Options, getEffectiveRelocModel(RM),
377                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
378       TLOF(createTLOF(getTargetTriple())) {
379   initAsmInfo();
380   if (TT.getArch() == Triple::amdgcn) {
381     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
382       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
383     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
384       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
385   }
386 }
387 
388 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
389 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
390 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
391 
392 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
393 
394 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
395   Attribute GPUAttr = F.getFnAttribute("target-cpu");
396   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
397 }
398 
399 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
400   Attribute FSAttr = F.getFnAttribute("target-features");
401 
402   return FSAttr.isValid() ? FSAttr.getValueAsString()
403                           : getTargetFeatureString();
404 }
405 
406 /// Predicate for Internalize pass.
407 static bool mustPreserveGV(const GlobalValue &GV) {
408   if (const Function *F = dyn_cast<Function>(&GV))
409     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
410 
411   return !GV.use_empty();
412 }
413 
414 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
415   Builder.DivergentTarget = true;
416 
417   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
418   bool Internalize = InternalizeSymbols;
419   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
420   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
421   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
422 
423   if (EnableFunctionCalls) {
424     delete Builder.Inliner;
425     Builder.Inliner = createFunctionInliningPass();
426   }
427 
428   Builder.addExtension(
429     PassManagerBuilder::EP_ModuleOptimizerEarly,
430     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
431                                                legacy::PassManagerBase &PM) {
432       if (AMDGPUAA) {
433         PM.add(createAMDGPUAAWrapperPass());
434         PM.add(createAMDGPUExternalAAWrapperPass());
435       }
436       PM.add(createAMDGPUUnifyMetadataPass());
437       PM.add(createAMDGPUPrintfRuntimeBinding());
438       if (Internalize)
439         PM.add(createInternalizePass(mustPreserveGV));
440       PM.add(createAMDGPUPropagateAttributesLatePass(this));
441       if (Internalize)
442         PM.add(createGlobalDCEPass());
443       if (EarlyInline)
444         PM.add(createAMDGPUAlwaysInlinePass(false));
445   });
446 
447   Builder.addExtension(
448     PassManagerBuilder::EP_EarlyAsPossible,
449     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
450                                       legacy::PassManagerBase &PM) {
451       if (AMDGPUAA) {
452         PM.add(createAMDGPUAAWrapperPass());
453         PM.add(createAMDGPUExternalAAWrapperPass());
454       }
455       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
456       PM.add(llvm::createAMDGPUUseNativeCallsPass());
457       if (LibCallSimplify)
458         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
459   });
460 
461   Builder.addExtension(
462     PassManagerBuilder::EP_CGSCCOptimizerLate,
463     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
464       // Add infer address spaces pass to the opt pipeline after inlining
465       // but before SROA to increase SROA opportunities.
466       PM.add(createInferAddressSpacesPass());
467 
468       // This should run after inlining to have any chance of doing anything,
469       // and before other cleanup optimizations.
470       PM.add(createAMDGPULowerKernelAttributesPass());
471 
472       // Promote alloca to vector before SROA and loop unroll. If we manage
473       // to eliminate allocas before unroll we may choose to unroll less.
474       if (EnableOpt)
475         PM.add(createAMDGPUPromoteAllocaToVector());
476   });
477 }
478 
479 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
480   AAM.registerFunctionAnalysis<AMDGPUAA>();
481 }
482 
483 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
484                                                        bool DebugPassManager) {
485   PB.registerPipelineParsingCallback(
486       [this](StringRef PassName, ModulePassManager &PM,
487              ArrayRef<PassBuilder::PipelineElement>) {
488         if (PassName == "amdgpu-propagate-attributes-late") {
489           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
490           return true;
491         }
492         if (PassName == "amdgpu-unify-metadata") {
493           PM.addPass(AMDGPUUnifyMetadataPass());
494           return true;
495         }
496         if (PassName == "amdgpu-printf-runtime-binding") {
497           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
498           return true;
499         }
500         if (PassName == "amdgpu-always-inline") {
501           PM.addPass(AMDGPUAlwaysInlinePass());
502           return true;
503         }
504         return false;
505       });
506   PB.registerPipelineParsingCallback(
507       [this](StringRef PassName, FunctionPassManager &PM,
508              ArrayRef<PassBuilder::PipelineElement>) {
509         if (PassName == "amdgpu-simplifylib") {
510           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
511           return true;
512         }
513         if (PassName == "amdgpu-usenative") {
514           PM.addPass(AMDGPUUseNativeCallsPass());
515           return true;
516         }
517         if (PassName == "amdgpu-promote-alloca") {
518           PM.addPass(AMDGPUPromoteAllocaPass(*this));
519           return true;
520         }
521         if (PassName == "amdgpu-promote-alloca-to-vector") {
522           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
523           return true;
524         }
525         if (PassName == "amdgpu-lower-kernel-attributes") {
526           PM.addPass(AMDGPULowerKernelAttributesPass());
527           return true;
528         }
529         if (PassName == "amdgpu-propagate-attributes-early") {
530           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
531           return true;
532         }
533 
534         return false;
535       });
536 
537   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
538     FAM.registerPass([&] { return AMDGPUAA(); });
539   });
540 
541   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
542     if (AAName == "amdgpu-aa") {
543       AAM.registerFunctionAnalysis<AMDGPUAA>();
544       return true;
545     }
546     return false;
547   });
548 
549   PB.registerPipelineStartEPCallback([this, DebugPassManager](
550                                          ModulePassManager &PM,
551                                          PassBuilder::OptimizationLevel Level) {
552     FunctionPassManager FPM(DebugPassManager);
553     FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
554     FPM.addPass(AMDGPUUseNativeCallsPass());
555     if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
556       FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
557     PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
558   });
559 
560   PB.registerPipelineEarlySimplificationEPCallback(
561       [this](ModulePassManager &PM, PassBuilder::OptimizationLevel Level) {
562         if (Level == PassBuilder::OptimizationLevel::O0)
563           return;
564 
565         PM.addPass(AMDGPUUnifyMetadataPass());
566         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
567 
568         if (InternalizeSymbols) {
569           PM.addPass(InternalizePass(mustPreserveGV));
570         }
571         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
572         if (InternalizeSymbols) {
573           PM.addPass(GlobalDCEPass());
574         }
575         if (EarlyInlineAll && !EnableFunctionCalls)
576           PM.addPass(AMDGPUAlwaysInlinePass());
577       });
578 
579   PB.registerCGSCCOptimizerLateEPCallback(
580       [this, DebugPassManager](CGSCCPassManager &PM,
581                                PassBuilder::OptimizationLevel Level) {
582           FunctionPassManager FPM(DebugPassManager);
583 
584           // Add infer address spaces pass to the opt pipeline after inlining
585           // but before SROA to increase SROA opportunities.
586           FPM.addPass(InferAddressSpacesPass());
587 
588           // This should run after inlining to have any chance of doing
589           // anything, and before other cleanup optimizations.
590           FPM.addPass(AMDGPULowerKernelAttributesPass());
591 
592           if (Level != PassBuilder::OptimizationLevel::O0) {
593             // Promote alloca to vector before SROA and loop unroll. If we
594             // manage to eliminate allocas before unroll we may choose to unroll
595             // less.
596             FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
597           }
598 
599           PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
600       });
601 }
602 
603 //===----------------------------------------------------------------------===//
604 // R600 Target Machine (R600 -> Cayman)
605 //===----------------------------------------------------------------------===//
606 
607 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
608                                      StringRef CPU, StringRef FS,
609                                      TargetOptions Options,
610                                      Optional<Reloc::Model> RM,
611                                      Optional<CodeModel::Model> CM,
612                                      CodeGenOpt::Level OL, bool JIT)
613     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
614   setRequiresStructuredCFG(true);
615 
616   // Override the default since calls aren't supported for r600.
617   if (EnableFunctionCalls &&
618       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
619     EnableFunctionCalls = false;
620 }
621 
622 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
623   const Function &F) const {
624   StringRef GPU = getGPUName(F);
625   StringRef FS = getFeatureString(F);
626 
627   SmallString<128> SubtargetKey(GPU);
628   SubtargetKey.append(FS);
629 
630   auto &I = SubtargetMap[SubtargetKey];
631   if (!I) {
632     // This needs to be done before we create a new subtarget since any
633     // creation will depend on the TM and the code generation flags on the
634     // function that reside in TargetOptions.
635     resetTargetOptions(F);
636     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
637   }
638 
639   return I.get();
640 }
641 
642 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
643   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
644           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
645           AddrSpace == AMDGPUAS::REGION_ADDRESS)
646              ? -1
647              : 0;
648 }
649 
650 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
651                                               unsigned DestAS) const {
652   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
653          AMDGPU::isFlatGlobalAddrSpace(DestAS);
654 }
655 
656 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
657   const auto *LD = dyn_cast<LoadInst>(V);
658   if (!LD)
659     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
660 
661   // It must be a generic pointer loaded.
662   assert(V->getType()->isPointerTy() &&
663          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
664 
665   const auto *Ptr = LD->getPointerOperand();
666   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
667     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
668   // For a generic pointer loaded from the constant memory, it could be assumed
669   // as a global pointer since the constant memory is only populated on the
670   // host side. As implied by the offload programming model, only global
671   // pointers could be referenced on the host side.
672   return AMDGPUAS::GLOBAL_ADDRESS;
673 }
674 
675 TargetTransformInfo
676 R600TargetMachine::getTargetTransformInfo(const Function &F) {
677   return TargetTransformInfo(R600TTIImpl(this, F));
678 }
679 
680 //===----------------------------------------------------------------------===//
681 // GCN Target Machine (SI+)
682 //===----------------------------------------------------------------------===//
683 
684 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
685                                    StringRef CPU, StringRef FS,
686                                    TargetOptions Options,
687                                    Optional<Reloc::Model> RM,
688                                    Optional<CodeModel::Model> CM,
689                                    CodeGenOpt::Level OL, bool JIT)
690     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
691 
692 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
693   StringRef GPU = getGPUName(F);
694   StringRef FS = getFeatureString(F);
695 
696   SmallString<128> SubtargetKey(GPU);
697   SubtargetKey.append(FS);
698 
699   auto &I = SubtargetMap[SubtargetKey];
700   if (!I) {
701     // This needs to be done before we create a new subtarget since any
702     // creation will depend on the TM and the code generation flags on the
703     // function that reside in TargetOptions.
704     resetTargetOptions(F);
705     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
706   }
707 
708   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
709 
710   return I.get();
711 }
712 
713 TargetTransformInfo
714 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
715   return TargetTransformInfo(GCNTTIImpl(this, F));
716 }
717 
718 //===----------------------------------------------------------------------===//
719 // AMDGPU Pass Setup
720 //===----------------------------------------------------------------------===//
721 
722 namespace {
723 
724 class AMDGPUPassConfig : public TargetPassConfig {
725 public:
726   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
727     : TargetPassConfig(TM, PM) {
728     // Exceptions and StackMaps are not supported, so these passes will never do
729     // anything.
730     disablePass(&StackMapLivenessID);
731     disablePass(&FuncletLayoutID);
732   }
733 
734   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
735     return getTM<AMDGPUTargetMachine>();
736   }
737 
738   ScheduleDAGInstrs *
739   createMachineScheduler(MachineSchedContext *C) const override {
740     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
741     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
742     return DAG;
743   }
744 
745   void addEarlyCSEOrGVNPass();
746   void addStraightLineScalarOptimizationPasses();
747   void addIRPasses() override;
748   void addCodeGenPrepare() override;
749   bool addPreISel() override;
750   bool addInstSelector() override;
751   bool addGCPasses() override;
752 
753   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
754 };
755 
756 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
757   return getStandardCSEConfigForOpt(TM->getOptLevel());
758 }
759 
760 class R600PassConfig final : public AMDGPUPassConfig {
761 public:
762   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
763     : AMDGPUPassConfig(TM, PM) {}
764 
765   ScheduleDAGInstrs *createMachineScheduler(
766     MachineSchedContext *C) const override {
767     return createR600MachineScheduler(C);
768   }
769 
770   bool addPreISel() override;
771   bool addInstSelector() override;
772   void addPreRegAlloc() override;
773   void addPreSched2() override;
774   void addPreEmitPass() override;
775 };
776 
777 class GCNPassConfig final : public AMDGPUPassConfig {
778 public:
779   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
780     : AMDGPUPassConfig(TM, PM) {
781     // It is necessary to know the register usage of the entire call graph.  We
782     // allow calls without EnableAMDGPUFunctionCalls if they are marked
783     // noinline, so this is always required.
784     setRequiresCodeGenSCCOrder(true);
785   }
786 
787   GCNTargetMachine &getGCNTargetMachine() const {
788     return getTM<GCNTargetMachine>();
789   }
790 
791   ScheduleDAGInstrs *
792   createMachineScheduler(MachineSchedContext *C) const override;
793 
794   bool addPreISel() override;
795   void addMachineSSAOptimization() override;
796   bool addILPOpts() override;
797   bool addInstSelector() override;
798   bool addIRTranslator() override;
799   void addPreLegalizeMachineIR() override;
800   bool addLegalizeMachineIR() override;
801   void addPreRegBankSelect() override;
802   bool addRegBankSelect() override;
803   bool addGlobalInstructionSelect() override;
804   void addFastRegAlloc() override;
805   void addOptimizedRegAlloc() override;
806   void addPreRegAlloc() override;
807   bool addPreRewrite() override;
808   void addPostRegAlloc() override;
809   void addPreSched2() override;
810   void addPreEmitPass() override;
811 };
812 
813 } // end anonymous namespace
814 
815 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
816   if (getOptLevel() == CodeGenOpt::Aggressive)
817     addPass(createGVNPass());
818   else
819     addPass(createEarlyCSEPass());
820 }
821 
822 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
823   addPass(createLICMPass());
824   addPass(createSeparateConstOffsetFromGEPPass());
825   addPass(createSpeculativeExecutionPass());
826   // ReassociateGEPs exposes more opportunites for SLSR. See
827   // the example in reassociate-geps-and-slsr.ll.
828   addPass(createStraightLineStrengthReducePass());
829   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
830   // EarlyCSE can reuse.
831   addEarlyCSEOrGVNPass();
832   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
833   addPass(createNaryReassociatePass());
834   // NaryReassociate on GEPs creates redundant common expressions, so run
835   // EarlyCSE after it.
836   addPass(createEarlyCSEPass());
837 }
838 
839 void AMDGPUPassConfig::addIRPasses() {
840   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
841 
842   // There is no reason to run these.
843   disablePass(&StackMapLivenessID);
844   disablePass(&FuncletLayoutID);
845   disablePass(&PatchableFunctionID);
846 
847   addPass(createAMDGPUPrintfRuntimeBinding());
848 
849   // This must occur before inlining, as the inliner will not look through
850   // bitcast calls.
851   addPass(createAMDGPUFixFunctionBitcastsPass());
852 
853   // A call to propagate attributes pass in the backend in case opt was not run.
854   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
855 
856   addPass(createAtomicExpandPass());
857 
858 
859   addPass(createAMDGPULowerIntrinsicsPass());
860 
861   // Function calls are not supported, so make sure we inline everything.
862   addPass(createAMDGPUAlwaysInlinePass());
863   addPass(createAlwaysInlinerLegacyPass());
864   // We need to add the barrier noop pass, otherwise adding the function
865   // inlining pass will cause all of the PassConfigs passes to be run
866   // one function at a time, which means if we have a nodule with two
867   // functions, then we will generate code for the first function
868   // without ever running any passes on the second.
869   addPass(createBarrierNoopPass());
870 
871   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
872   if (TM.getTargetTriple().getArch() == Triple::r600)
873     addPass(createR600OpenCLImageTypeLoweringPass());
874 
875   // Replace OpenCL enqueued block function pointers with global variables.
876   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
877 
878   if (TM.getOptLevel() > CodeGenOpt::None) {
879     addPass(createInferAddressSpacesPass());
880     addPass(createAMDGPUPromoteAlloca());
881 
882     if (EnableSROA)
883       addPass(createSROAPass());
884 
885     if (EnableScalarIRPasses)
886       addStraightLineScalarOptimizationPasses();
887 
888     if (EnableAMDGPUAliasAnalysis) {
889       addPass(createAMDGPUAAWrapperPass());
890       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
891                                              AAResults &AAR) {
892         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
893           AAR.addAAResult(WrapperPass->getResult());
894         }));
895     }
896   }
897 
898   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
899     // TODO: May want to move later or split into an early and late one.
900     addPass(createAMDGPUCodeGenPreparePass());
901   }
902 
903   TargetPassConfig::addIRPasses();
904 
905   // EarlyCSE is not always strong enough to clean up what LSR produces. For
906   // example, GVN can combine
907   //
908   //   %0 = add %a, %b
909   //   %1 = add %b, %a
910   //
911   // and
912   //
913   //   %0 = shl nsw %a, 2
914   //   %1 = shl %a, 2
915   //
916   // but EarlyCSE can do neither of them.
917   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
918     addEarlyCSEOrGVNPass();
919 }
920 
921 void AMDGPUPassConfig::addCodeGenPrepare() {
922   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
923     addPass(createAMDGPUAnnotateKernelFeaturesPass());
924 
925   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
926       EnableLowerKernelArguments)
927     addPass(createAMDGPULowerKernelArgumentsPass());
928 
929   addPass(&AMDGPUPerfHintAnalysisID);
930 
931   TargetPassConfig::addCodeGenPrepare();
932 
933   if (EnableLoadStoreVectorizer)
934     addPass(createLoadStoreVectorizerPass());
935 
936   // LowerSwitch pass may introduce unreachable blocks that can
937   // cause unexpected behavior for subsequent passes. Placing it
938   // here seems better that these blocks would get cleaned up by
939   // UnreachableBlockElim inserted next in the pass flow.
940   addPass(createLowerSwitchPass());
941 }
942 
943 bool AMDGPUPassConfig::addPreISel() {
944   addPass(createFlattenCFGPass());
945   return false;
946 }
947 
948 bool AMDGPUPassConfig::addInstSelector() {
949   // Defer the verifier until FinalizeISel.
950   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
951   return false;
952 }
953 
954 bool AMDGPUPassConfig::addGCPasses() {
955   // Do nothing. GC is not supported.
956   return false;
957 }
958 
959 //===----------------------------------------------------------------------===//
960 // R600 Pass Setup
961 //===----------------------------------------------------------------------===//
962 
963 bool R600PassConfig::addPreISel() {
964   AMDGPUPassConfig::addPreISel();
965 
966   if (EnableR600StructurizeCFG)
967     addPass(createStructurizeCFGPass());
968   return false;
969 }
970 
971 bool R600PassConfig::addInstSelector() {
972   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
973   return false;
974 }
975 
976 void R600PassConfig::addPreRegAlloc() {
977   addPass(createR600VectorRegMerger());
978 }
979 
980 void R600PassConfig::addPreSched2() {
981   addPass(createR600EmitClauseMarkers(), false);
982   if (EnableR600IfConvert)
983     addPass(&IfConverterID, false);
984   addPass(createR600ClauseMergePass(), false);
985 }
986 
987 void R600PassConfig::addPreEmitPass() {
988   addPass(createAMDGPUCFGStructurizerPass(), false);
989   addPass(createR600ExpandSpecialInstrsPass(), false);
990   addPass(&FinalizeMachineBundlesID, false);
991   addPass(createR600Packetizer(), false);
992   addPass(createR600ControlFlowFinalizer(), false);
993 }
994 
995 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
996   return new R600PassConfig(*this, PM);
997 }
998 
999 //===----------------------------------------------------------------------===//
1000 // GCN Pass Setup
1001 //===----------------------------------------------------------------------===//
1002 
1003 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1004   MachineSchedContext *C) const {
1005   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1006   if (ST.enableSIScheduler())
1007     return createSIMachineScheduler(C);
1008   return createGCNMaxOccupancyMachineScheduler(C);
1009 }
1010 
1011 bool GCNPassConfig::addPreISel() {
1012   AMDGPUPassConfig::addPreISel();
1013 
1014   addPass(createAMDGPULateCodeGenPreparePass());
1015   if (EnableAtomicOptimizations) {
1016     addPass(createAMDGPUAtomicOptimizerPass());
1017   }
1018 
1019   // FIXME: We need to run a pass to propagate the attributes when calls are
1020   // supported.
1021 
1022   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1023   // regions formed by them.
1024   addPass(&AMDGPUUnifyDivergentExitNodesID);
1025   if (!LateCFGStructurize) {
1026     if (EnableStructurizerWorkarounds) {
1027       addPass(createFixIrreduciblePass());
1028       addPass(createUnifyLoopExitsPass());
1029     }
1030     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1031   }
1032   addPass(createSinkingPass());
1033   addPass(createAMDGPUAnnotateUniformValues());
1034   if (!LateCFGStructurize) {
1035     addPass(createSIAnnotateControlFlowPass());
1036   }
1037   addPass(createLCSSAPass());
1038 
1039   return false;
1040 }
1041 
1042 void GCNPassConfig::addMachineSSAOptimization() {
1043   TargetPassConfig::addMachineSSAOptimization();
1044 
1045   // We want to fold operands after PeepholeOptimizer has run (or as part of
1046   // it), because it will eliminate extra copies making it easier to fold the
1047   // real source operand. We want to eliminate dead instructions after, so that
1048   // we see fewer uses of the copies. We then need to clean up the dead
1049   // instructions leftover after the operands are folded as well.
1050   //
1051   // XXX - Can we get away without running DeadMachineInstructionElim again?
1052   addPass(&SIFoldOperandsID);
1053   if (EnableDPPCombine)
1054     addPass(&GCNDPPCombineID);
1055   addPass(&DeadMachineInstructionElimID);
1056   addPass(&SILoadStoreOptimizerID);
1057   if (EnableSDWAPeephole) {
1058     addPass(&SIPeepholeSDWAID);
1059     addPass(&EarlyMachineLICMID);
1060     addPass(&MachineCSEID);
1061     addPass(&SIFoldOperandsID);
1062     addPass(&DeadMachineInstructionElimID);
1063   }
1064   addPass(createSIShrinkInstructionsPass());
1065 }
1066 
1067 bool GCNPassConfig::addILPOpts() {
1068   if (EnableEarlyIfConversion)
1069     addPass(&EarlyIfConverterID);
1070 
1071   TargetPassConfig::addILPOpts();
1072   return false;
1073 }
1074 
1075 bool GCNPassConfig::addInstSelector() {
1076   AMDGPUPassConfig::addInstSelector();
1077   addPass(&SIFixSGPRCopiesID);
1078   addPass(createSILowerI1CopiesPass());
1079   addPass(createSIAddIMGInitPass());
1080   return false;
1081 }
1082 
1083 bool GCNPassConfig::addIRTranslator() {
1084   addPass(new IRTranslator(getOptLevel()));
1085   return false;
1086 }
1087 
1088 void GCNPassConfig::addPreLegalizeMachineIR() {
1089   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1090   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1091   addPass(new Localizer());
1092 }
1093 
1094 bool GCNPassConfig::addLegalizeMachineIR() {
1095   addPass(new Legalizer());
1096   return false;
1097 }
1098 
1099 void GCNPassConfig::addPreRegBankSelect() {
1100   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1101   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1102 }
1103 
1104 bool GCNPassConfig::addRegBankSelect() {
1105   addPass(new RegBankSelect());
1106   return false;
1107 }
1108 
1109 bool GCNPassConfig::addGlobalInstructionSelect() {
1110   addPass(new InstructionSelect());
1111   // TODO: Fix instruction selection to do the right thing for image
1112   // instructions with tfe or lwe in the first place, instead of running a
1113   // separate pass to fix them up?
1114   addPass(createSIAddIMGInitPass());
1115   return false;
1116 }
1117 
1118 void GCNPassConfig::addPreRegAlloc() {
1119   if (LateCFGStructurize) {
1120     addPass(createAMDGPUMachineCFGStructurizerPass());
1121   }
1122 }
1123 
1124 void GCNPassConfig::addFastRegAlloc() {
1125   // FIXME: We have to disable the verifier here because of PHIElimination +
1126   // TwoAddressInstructions disabling it.
1127 
1128   // This must be run immediately after phi elimination and before
1129   // TwoAddressInstructions, otherwise the processing of the tied operand of
1130   // SI_ELSE will introduce a copy of the tied operand source after the else.
1131   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1132 
1133   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1134   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1135 
1136   TargetPassConfig::addFastRegAlloc();
1137 }
1138 
1139 void GCNPassConfig::addOptimizedRegAlloc() {
1140   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1141   // instructions that cause scheduling barriers.
1142   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1143   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1144 
1145   if (OptExecMaskPreRA)
1146     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1147   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1148 
1149   // This must be run immediately after phi elimination and before
1150   // TwoAddressInstructions, otherwise the processing of the tied operand of
1151   // SI_ELSE will introduce a copy of the tied operand source after the else.
1152   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1153 
1154   if (EnableDCEInRA)
1155     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1156 
1157   TargetPassConfig::addOptimizedRegAlloc();
1158 }
1159 
1160 bool GCNPassConfig::addPreRewrite() {
1161   if (EnableRegReassign) {
1162     addPass(&GCNNSAReassignID);
1163     addPass(&GCNRegBankReassignID);
1164   }
1165   return true;
1166 }
1167 
1168 void GCNPassConfig::addPostRegAlloc() {
1169   addPass(&SIFixVGPRCopiesID);
1170   if (getOptLevel() > CodeGenOpt::None)
1171     addPass(&SIOptimizeExecMaskingID);
1172   TargetPassConfig::addPostRegAlloc();
1173 
1174   // Equivalent of PEI for SGPRs.
1175   addPass(&SILowerSGPRSpillsID);
1176 }
1177 
1178 void GCNPassConfig::addPreSched2() {
1179   addPass(&SIPostRABundlerID);
1180 }
1181 
1182 void GCNPassConfig::addPreEmitPass() {
1183   addPass(createSIMemoryLegalizerPass());
1184   addPass(createSIInsertWaitcntsPass());
1185   addPass(createSIShrinkInstructionsPass());
1186   addPass(createSIModeRegisterPass());
1187 
1188   if (getOptLevel() > CodeGenOpt::None)
1189     addPass(&SIInsertHardClausesID);
1190 
1191   addPass(&SIRemoveShortExecBranchesID);
1192   addPass(&SIInsertSkipsPassID);
1193   addPass(&SIPreEmitPeepholeID);
1194   // The hazard recognizer that runs as part of the post-ra scheduler does not
1195   // guarantee to be able handle all hazards correctly. This is because if there
1196   // are multiple scheduling regions in a basic block, the regions are scheduled
1197   // bottom up, so when we begin to schedule a region we don't know what
1198   // instructions were emitted directly before it.
1199   //
1200   // Here we add a stand-alone hazard recognizer pass which can handle all
1201   // cases.
1202   addPass(&PostRAHazardRecognizerID);
1203   addPass(&BranchRelaxationPassID);
1204 }
1205 
1206 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1207   return new GCNPassConfig(*this, PM);
1208 }
1209 
1210 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1211   return new yaml::SIMachineFunctionInfo();
1212 }
1213 
1214 yaml::MachineFunctionInfo *
1215 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1216   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1217   return new yaml::SIMachineFunctionInfo(*MFI,
1218                                          *MF.getSubtarget().getRegisterInfo());
1219 }
1220 
1221 bool GCNTargetMachine::parseMachineFunctionInfo(
1222     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1223     SMDiagnostic &Error, SMRange &SourceRange) const {
1224   const yaml::SIMachineFunctionInfo &YamlMFI =
1225       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1226   MachineFunction &MF = PFS.MF;
1227   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1228 
1229   MFI->initializeBaseYamlFields(YamlMFI);
1230 
1231   if (MFI->Occupancy == 0) {
1232     // Fixup the subtarget dependent default value.
1233     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1234     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1235   }
1236 
1237   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1238     Register TempReg;
1239     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1240       SourceRange = RegName.SourceRange;
1241       return true;
1242     }
1243     RegVal = TempReg;
1244 
1245     return false;
1246   };
1247 
1248   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1249     // Create a diagnostic for a the register string literal.
1250     const MemoryBuffer &Buffer =
1251         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1252     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1253                          RegName.Value.size(), SourceMgr::DK_Error,
1254                          "incorrect register class for field", RegName.Value,
1255                          None, None);
1256     SourceRange = RegName.SourceRange;
1257     return true;
1258   };
1259 
1260   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1261       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1262       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1263     return true;
1264 
1265   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1266       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1267     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1268   }
1269 
1270   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1271       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1272     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1273   }
1274 
1275   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1276       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1277     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1278   }
1279 
1280   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1281                                    const TargetRegisterClass &RC,
1282                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1283                                    unsigned SystemSGPRs) {
1284     // Skip parsing if it's not present.
1285     if (!A)
1286       return false;
1287 
1288     if (A->IsRegister) {
1289       Register Reg;
1290       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1291         SourceRange = A->RegisterName.SourceRange;
1292         return true;
1293       }
1294       if (!RC.contains(Reg))
1295         return diagnoseRegisterClass(A->RegisterName);
1296       Arg = ArgDescriptor::createRegister(Reg);
1297     } else
1298       Arg = ArgDescriptor::createStack(A->StackOffset);
1299     // Check and apply the optional mask.
1300     if (A->Mask)
1301       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1302 
1303     MFI->NumUserSGPRs += UserSGPRs;
1304     MFI->NumSystemSGPRs += SystemSGPRs;
1305     return false;
1306   };
1307 
1308   if (YamlMFI.ArgInfo &&
1309       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1310                              AMDGPU::SGPR_128RegClass,
1311                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1312        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1313                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1314                              2, 0) ||
1315        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1316                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1317        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1318                              AMDGPU::SReg_64RegClass,
1319                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1320        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1321                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1322                              2, 0) ||
1323        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1324                              AMDGPU::SReg_64RegClass,
1325                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1326        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1327                              AMDGPU::SGPR_32RegClass,
1328                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1329        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1330                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1331                              0, 1) ||
1332        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1333                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1334                              0, 1) ||
1335        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1336                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1337                              0, 1) ||
1338        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1339                              AMDGPU::SGPR_32RegClass,
1340                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1341        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1342                              AMDGPU::SGPR_32RegClass,
1343                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1344        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1345                              AMDGPU::SReg_64RegClass,
1346                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1347        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1348                              AMDGPU::SReg_64RegClass,
1349                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1350        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1351                              AMDGPU::VGPR_32RegClass,
1352                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1353        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1354                              AMDGPU::VGPR_32RegClass,
1355                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1356        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1357                              AMDGPU::VGPR_32RegClass,
1358                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1359     return true;
1360 
1361   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1362   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1363   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1364   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1365   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1366   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1367 
1368   return false;
1369 }
1370