1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for SI+ GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600.h"
25 #include "R600TargetMachine.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIMachineScheduler.h"
28 #include "TargetInfo/AMDGPUTargetInfo.h"
29 #include "llvm/Analysis/CGSCCPassManager.h"
30 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
31 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
32 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
33 #include "llvm/CodeGen/GlobalISel/Localizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MIRParser/MIParser.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/RegAllocRegistry.h"
38 #include "llvm/CodeGen/TargetPassConfig.h"
39 #include "llvm/IR/IntrinsicsAMDGPU.h"
40 #include "llvm/IR/LegacyPassManager.h"
41 #include "llvm/IR/PassManager.h"
42 #include "llvm/IR/PatternMatch.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/MC/TargetRegistry.h"
45 #include "llvm/Passes/PassBuilder.h"
46 #include "llvm/Transforms/IPO.h"
47 #include "llvm/Transforms/IPO/AlwaysInliner.h"
48 #include "llvm/Transforms/IPO/GlobalDCE.h"
49 #include "llvm/Transforms/IPO/Internalize.h"
50 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
51 #include "llvm/Transforms/Scalar.h"
52 #include "llvm/Transforms/Scalar/GVN.h"
53 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
54 #include "llvm/Transforms/Utils.h"
55 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
56 #include "llvm/Transforms/Vectorize.h"
57 
58 using namespace llvm;
59 
60 namespace {
61 class SGPRRegisterRegAlloc : public RegisterRegAllocBase<SGPRRegisterRegAlloc> {
62 public:
63   SGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
64     : RegisterRegAllocBase(N, D, C) {}
65 };
66 
67 class VGPRRegisterRegAlloc : public RegisterRegAllocBase<VGPRRegisterRegAlloc> {
68 public:
69   VGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
70     : RegisterRegAllocBase(N, D, C) {}
71 };
72 
73 static bool onlyAllocateSGPRs(const TargetRegisterInfo &TRI,
74                               const TargetRegisterClass &RC) {
75   return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
76 }
77 
78 static bool onlyAllocateVGPRs(const TargetRegisterInfo &TRI,
79                               const TargetRegisterClass &RC) {
80   return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
81 }
82 
83 
84 /// -{sgpr|vgpr}-regalloc=... command line option.
85 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
86 
87 /// A dummy default pass factory indicates whether the register allocator is
88 /// overridden on the command line.
89 static llvm::once_flag InitializeDefaultSGPRRegisterAllocatorFlag;
90 static llvm::once_flag InitializeDefaultVGPRRegisterAllocatorFlag;
91 
92 static SGPRRegisterRegAlloc
93 defaultSGPRRegAlloc("default",
94                     "pick SGPR register allocator based on -O option",
95                     useDefaultRegisterAllocator);
96 
97 static cl::opt<SGPRRegisterRegAlloc::FunctionPassCtor, false,
98                RegisterPassParser<SGPRRegisterRegAlloc>>
99 SGPRRegAlloc("sgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
100              cl::desc("Register allocator to use for SGPRs"));
101 
102 static cl::opt<VGPRRegisterRegAlloc::FunctionPassCtor, false,
103                RegisterPassParser<VGPRRegisterRegAlloc>>
104 VGPRRegAlloc("vgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
105              cl::desc("Register allocator to use for VGPRs"));
106 
107 
108 static void initializeDefaultSGPRRegisterAllocatorOnce() {
109   RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
110 
111   if (!Ctor) {
112     Ctor = SGPRRegAlloc;
113     SGPRRegisterRegAlloc::setDefault(SGPRRegAlloc);
114   }
115 }
116 
117 static void initializeDefaultVGPRRegisterAllocatorOnce() {
118   RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
119 
120   if (!Ctor) {
121     Ctor = VGPRRegAlloc;
122     VGPRRegisterRegAlloc::setDefault(VGPRRegAlloc);
123   }
124 }
125 
126 static FunctionPass *createBasicSGPRRegisterAllocator() {
127   return createBasicRegisterAllocator(onlyAllocateSGPRs);
128 }
129 
130 static FunctionPass *createGreedySGPRRegisterAllocator() {
131   return createGreedyRegisterAllocator(onlyAllocateSGPRs);
132 }
133 
134 static FunctionPass *createFastSGPRRegisterAllocator() {
135   return createFastRegisterAllocator(onlyAllocateSGPRs, false);
136 }
137 
138 static FunctionPass *createBasicVGPRRegisterAllocator() {
139   return createBasicRegisterAllocator(onlyAllocateVGPRs);
140 }
141 
142 static FunctionPass *createGreedyVGPRRegisterAllocator() {
143   return createGreedyRegisterAllocator(onlyAllocateVGPRs);
144 }
145 
146 static FunctionPass *createFastVGPRRegisterAllocator() {
147   return createFastRegisterAllocator(onlyAllocateVGPRs, true);
148 }
149 
150 static SGPRRegisterRegAlloc basicRegAllocSGPR(
151   "basic", "basic register allocator", createBasicSGPRRegisterAllocator);
152 static SGPRRegisterRegAlloc greedyRegAllocSGPR(
153   "greedy", "greedy register allocator", createGreedySGPRRegisterAllocator);
154 
155 static SGPRRegisterRegAlloc fastRegAllocSGPR(
156   "fast", "fast register allocator", createFastSGPRRegisterAllocator);
157 
158 
159 static VGPRRegisterRegAlloc basicRegAllocVGPR(
160   "basic", "basic register allocator", createBasicVGPRRegisterAllocator);
161 static VGPRRegisterRegAlloc greedyRegAllocVGPR(
162   "greedy", "greedy register allocator", createGreedyVGPRRegisterAllocator);
163 
164 static VGPRRegisterRegAlloc fastRegAllocVGPR(
165   "fast", "fast register allocator", createFastVGPRRegisterAllocator);
166 }
167 
168 static cl::opt<bool> EnableSROA(
169   "amdgpu-sroa",
170   cl::desc("Run SROA after promote alloca pass"),
171   cl::ReallyHidden,
172   cl::init(true));
173 
174 static cl::opt<bool>
175 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
176                         cl::desc("Run early if-conversion"),
177                         cl::init(false));
178 
179 static cl::opt<bool>
180 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
181             cl::desc("Run pre-RA exec mask optimizations"),
182             cl::init(true));
183 
184 // Option to disable vectorizer for tests.
185 static cl::opt<bool> EnableLoadStoreVectorizer(
186   "amdgpu-load-store-vectorizer",
187   cl::desc("Enable load store vectorizer"),
188   cl::init(true),
189   cl::Hidden);
190 
191 // Option to control global loads scalarization
192 static cl::opt<bool> ScalarizeGlobal(
193   "amdgpu-scalarize-global-loads",
194   cl::desc("Enable global load scalarization"),
195   cl::init(true),
196   cl::Hidden);
197 
198 // Option to run internalize pass.
199 static cl::opt<bool> InternalizeSymbols(
200   "amdgpu-internalize-symbols",
201   cl::desc("Enable elimination of non-kernel functions and unused globals"),
202   cl::init(false),
203   cl::Hidden);
204 
205 // Option to inline all early.
206 static cl::opt<bool> EarlyInlineAll(
207   "amdgpu-early-inline-all",
208   cl::desc("Inline all functions early"),
209   cl::init(false),
210   cl::Hidden);
211 
212 static cl::opt<bool> EnableSDWAPeephole(
213   "amdgpu-sdwa-peephole",
214   cl::desc("Enable SDWA peepholer"),
215   cl::init(true));
216 
217 static cl::opt<bool> EnableDPPCombine(
218   "amdgpu-dpp-combine",
219   cl::desc("Enable DPP combiner"),
220   cl::init(true));
221 
222 // Enable address space based alias analysis
223 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
224   cl::desc("Enable AMDGPU Alias Analysis"),
225   cl::init(true));
226 
227 // Option to run late CFG structurizer
228 static cl::opt<bool, true> LateCFGStructurize(
229   "amdgpu-late-structurize",
230   cl::desc("Enable late CFG structurization"),
231   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
232   cl::Hidden);
233 
234 // Enable lib calls simplifications
235 static cl::opt<bool> EnableLibCallSimplify(
236   "amdgpu-simplify-libcall",
237   cl::desc("Enable amdgpu library simplifications"),
238   cl::init(true),
239   cl::Hidden);
240 
241 static cl::opt<bool> EnableLowerKernelArguments(
242   "amdgpu-ir-lower-kernel-arguments",
243   cl::desc("Lower kernel argument loads in IR pass"),
244   cl::init(true),
245   cl::Hidden);
246 
247 static cl::opt<bool> EnableRegReassign(
248   "amdgpu-reassign-regs",
249   cl::desc("Enable register reassign optimizations on gfx10+"),
250   cl::init(true),
251   cl::Hidden);
252 
253 static cl::opt<bool> OptVGPRLiveRange(
254     "amdgpu-opt-vgpr-liverange",
255     cl::desc("Enable VGPR liverange optimizations for if-else structure"),
256     cl::init(true), cl::Hidden);
257 
258 // Enable atomic optimization
259 static cl::opt<bool> EnableAtomicOptimizations(
260   "amdgpu-atomic-optimizations",
261   cl::desc("Enable atomic optimizations"),
262   cl::init(false),
263   cl::Hidden);
264 
265 // Enable Mode register optimization
266 static cl::opt<bool> EnableSIModeRegisterPass(
267   "amdgpu-mode-register",
268   cl::desc("Enable mode register pass"),
269   cl::init(true),
270   cl::Hidden);
271 
272 // Option is used in lit tests to prevent deadcoding of patterns inspected.
273 static cl::opt<bool>
274 EnableDCEInRA("amdgpu-dce-in-ra",
275     cl::init(true), cl::Hidden,
276     cl::desc("Enable machine DCE inside regalloc"));
277 
278 static cl::opt<bool> EnableScalarIRPasses(
279   "amdgpu-scalar-ir-passes",
280   cl::desc("Enable scalar IR passes"),
281   cl::init(true),
282   cl::Hidden);
283 
284 static cl::opt<bool> EnableStructurizerWorkarounds(
285     "amdgpu-enable-structurizer-workarounds",
286     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
287     cl::Hidden);
288 
289 static cl::opt<bool> EnableLDSReplaceWithPointer(
290     "amdgpu-enable-lds-replace-with-pointer",
291     cl::desc("Enable LDS replace with pointer pass"), cl::init(false),
292     cl::Hidden);
293 
294 static cl::opt<bool, true> EnableLowerModuleLDS(
295     "amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"),
296     cl::location(AMDGPUTargetMachine::EnableLowerModuleLDS), cl::init(true),
297     cl::Hidden);
298 
299 static cl::opt<bool> EnablePreRAOptimizations(
300     "amdgpu-enable-pre-ra-optimizations",
301     cl::desc("Enable Pre-RA optimizations pass"), cl::init(true),
302     cl::Hidden);
303 
304 static cl::opt<bool> EnablePromoteKernelArguments(
305     "amdgpu-enable-promote-kernel-arguments",
306     cl::desc("Enable promotion of flat kernel pointer arguments to global"),
307     cl::Hidden, cl::init(true));
308 
309 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
310   // Register the target
311   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
312   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
313 
314   PassRegistry *PR = PassRegistry::getPassRegistry();
315   initializeR600ClauseMergePassPass(*PR);
316   initializeR600ControlFlowFinalizerPass(*PR);
317   initializeR600PacketizerPass(*PR);
318   initializeR600ExpandSpecialInstrsPassPass(*PR);
319   initializeR600VectorRegMergerPass(*PR);
320   initializeGlobalISel(*PR);
321   initializeAMDGPUDAGToDAGISelPass(*PR);
322   initializeGCNDPPCombinePass(*PR);
323   initializeSILowerI1CopiesPass(*PR);
324   initializeSILowerSGPRSpillsPass(*PR);
325   initializeSIFixSGPRCopiesPass(*PR);
326   initializeSIFixVGPRCopiesPass(*PR);
327   initializeSIFoldOperandsPass(*PR);
328   initializeSIPeepholeSDWAPass(*PR);
329   initializeSIShrinkInstructionsPass(*PR);
330   initializeSIOptimizeExecMaskingPreRAPass(*PR);
331   initializeSIOptimizeVGPRLiveRangePass(*PR);
332   initializeSILoadStoreOptimizerPass(*PR);
333   initializeAMDGPUCtorDtorLoweringPass(*PR);
334   initializeAMDGPUAlwaysInlinePass(*PR);
335   initializeAMDGPUAttributorPass(*PR);
336   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
337   initializeAMDGPUAnnotateUniformValuesPass(*PR);
338   initializeAMDGPUArgumentUsageInfoPass(*PR);
339   initializeAMDGPUAtomicOptimizerPass(*PR);
340   initializeAMDGPULowerKernelArgumentsPass(*PR);
341   initializeAMDGPUPromoteKernelArgumentsPass(*PR);
342   initializeAMDGPULowerKernelAttributesPass(*PR);
343   initializeAMDGPULowerIntrinsicsPass(*PR);
344   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
345   initializeAMDGPUPostLegalizerCombinerPass(*PR);
346   initializeAMDGPUPreLegalizerCombinerPass(*PR);
347   initializeAMDGPURegBankCombinerPass(*PR);
348   initializeAMDGPUPromoteAllocaPass(*PR);
349   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
350   initializeAMDGPUCodeGenPreparePass(*PR);
351   initializeAMDGPULateCodeGenPreparePass(*PR);
352   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
353   initializeAMDGPUPropagateAttributesLatePass(*PR);
354   initializeAMDGPUReplaceLDSUseWithPointerPass(*PR);
355   initializeAMDGPULowerModuleLDSPass(*PR);
356   initializeAMDGPURewriteOutArgumentsPass(*PR);
357   initializeAMDGPUUnifyMetadataPass(*PR);
358   initializeSIAnnotateControlFlowPass(*PR);
359   initializeSIInsertHardClausesPass(*PR);
360   initializeSIInsertWaitcntsPass(*PR);
361   initializeSIModeRegisterPass(*PR);
362   initializeSIWholeQuadModePass(*PR);
363   initializeSILowerControlFlowPass(*PR);
364   initializeSIPreEmitPeepholePass(*PR);
365   initializeSILateBranchLoweringPass(*PR);
366   initializeSIMemoryLegalizerPass(*PR);
367   initializeSIOptimizeExecMaskingPass(*PR);
368   initializeSIPreAllocateWWMRegsPass(*PR);
369   initializeSIFormMemoryClausesPass(*PR);
370   initializeSIPostRABundlerPass(*PR);
371   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
372   initializeAMDGPUAAWrapperPassPass(*PR);
373   initializeAMDGPUExternalAAWrapperPass(*PR);
374   initializeAMDGPUUseNativeCallsPass(*PR);
375   initializeAMDGPUSimplifyLibCallsPass(*PR);
376   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
377   initializeAMDGPUResourceUsageAnalysisPass(*PR);
378   initializeGCNNSAReassignPass(*PR);
379   initializeGCNPreRAOptimizationsPass(*PR);
380 }
381 
382 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
383   return std::make_unique<AMDGPUTargetObjectFile>();
384 }
385 
386 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
387   return new SIScheduleDAGMI(C);
388 }
389 
390 static ScheduleDAGInstrs *
391 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
392   ScheduleDAGMILive *DAG =
393     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
394   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
395   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
396   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
397   return DAG;
398 }
399 
400 static ScheduleDAGInstrs *
401 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
402   auto DAG = new GCNIterativeScheduler(C,
403     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
404   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
405   return DAG;
406 }
407 
408 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
409   return new GCNIterativeScheduler(C,
410     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
411 }
412 
413 static ScheduleDAGInstrs *
414 createIterativeILPMachineScheduler(MachineSchedContext *C) {
415   auto DAG = new GCNIterativeScheduler(C,
416     GCNIterativeScheduler::SCHEDULE_ILP);
417   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
418   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
419   return DAG;
420 }
421 
422 static MachineSchedRegistry
423 SISchedRegistry("si", "Run SI's custom scheduler",
424                 createSIMachineScheduler);
425 
426 static MachineSchedRegistry
427 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
428                              "Run GCN scheduler to maximize occupancy",
429                              createGCNMaxOccupancyMachineScheduler);
430 
431 static MachineSchedRegistry
432 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
433   "Run GCN scheduler to maximize occupancy (experimental)",
434   createIterativeGCNMaxOccupancyMachineScheduler);
435 
436 static MachineSchedRegistry
437 GCNMinRegSchedRegistry("gcn-minreg",
438   "Run GCN iterative scheduler for minimal register usage (experimental)",
439   createMinRegScheduler);
440 
441 static MachineSchedRegistry
442 GCNILPSchedRegistry("gcn-ilp",
443   "Run GCN iterative scheduler for ILP scheduling (experimental)",
444   createIterativeILPMachineScheduler);
445 
446 static StringRef computeDataLayout(const Triple &TT) {
447   if (TT.getArch() == Triple::r600) {
448     // 32-bit pointers.
449     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
450            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
451   }
452 
453   // 32-bit private, local, and region pointers. 64-bit global, constant and
454   // flat, non-integral buffer fat pointers.
455   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
456          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
457          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
458          "-ni:7";
459 }
460 
461 LLVM_READNONE
462 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
463   if (!GPU.empty())
464     return GPU;
465 
466   // Need to default to a target with flat support for HSA.
467   if (TT.getArch() == Triple::amdgcn)
468     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
469 
470   return "r600";
471 }
472 
473 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
474   // The AMDGPU toolchain only supports generating shared objects, so we
475   // must always use PIC.
476   return Reloc::PIC_;
477 }
478 
479 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
480                                          StringRef CPU, StringRef FS,
481                                          TargetOptions Options,
482                                          Optional<Reloc::Model> RM,
483                                          Optional<CodeModel::Model> CM,
484                                          CodeGenOpt::Level OptLevel)
485     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
486                         FS, Options, getEffectiveRelocModel(RM),
487                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
488       TLOF(createTLOF(getTargetTriple())) {
489   initAsmInfo();
490   if (TT.getArch() == Triple::amdgcn) {
491     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
492       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
493     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
494       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
495   }
496 }
497 
498 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
499 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
500 bool AMDGPUTargetMachine::EnableLowerModuleLDS = true;
501 
502 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
503 
504 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
505   Attribute GPUAttr = F.getFnAttribute("target-cpu");
506   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
507 }
508 
509 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
510   Attribute FSAttr = F.getFnAttribute("target-features");
511 
512   return FSAttr.isValid() ? FSAttr.getValueAsString()
513                           : getTargetFeatureString();
514 }
515 
516 /// Predicate for Internalize pass.
517 static bool mustPreserveGV(const GlobalValue &GV) {
518   if (const Function *F = dyn_cast<Function>(&GV))
519     return F->isDeclaration() || F->getName().startswith("__asan_") ||
520            F->getName().startswith("__sanitizer_") ||
521            AMDGPU::isEntryFunctionCC(F->getCallingConv());
522 
523   GV.removeDeadConstantUsers();
524   return !GV.use_empty();
525 }
526 
527 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
528   Builder.DivergentTarget = true;
529 
530   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
531   bool Internalize = InternalizeSymbols;
532   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
533   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
534   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
535   bool PromoteKernelArguments =
536       EnablePromoteKernelArguments && getOptLevel() > CodeGenOpt::Less;
537 
538   if (EnableFunctionCalls) {
539     delete Builder.Inliner;
540     Builder.Inliner = createFunctionInliningPass();
541   }
542 
543   Builder.addExtension(
544     PassManagerBuilder::EP_ModuleOptimizerEarly,
545     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
546                                                legacy::PassManagerBase &PM) {
547       if (AMDGPUAA) {
548         PM.add(createAMDGPUAAWrapperPass());
549         PM.add(createAMDGPUExternalAAWrapperPass());
550       }
551       PM.add(createAMDGPUUnifyMetadataPass());
552       PM.add(createAMDGPUPrintfRuntimeBinding());
553       if (Internalize)
554         PM.add(createInternalizePass(mustPreserveGV));
555       PM.add(createAMDGPUPropagateAttributesLatePass(this));
556       if (Internalize)
557         PM.add(createGlobalDCEPass());
558       if (EarlyInline)
559         PM.add(createAMDGPUAlwaysInlinePass(false));
560   });
561 
562   Builder.addExtension(
563     PassManagerBuilder::EP_EarlyAsPossible,
564     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
565                                       legacy::PassManagerBase &PM) {
566       if (AMDGPUAA) {
567         PM.add(createAMDGPUAAWrapperPass());
568         PM.add(createAMDGPUExternalAAWrapperPass());
569       }
570       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
571       PM.add(llvm::createAMDGPUUseNativeCallsPass());
572       if (LibCallSimplify)
573         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
574   });
575 
576   Builder.addExtension(
577     PassManagerBuilder::EP_CGSCCOptimizerLate,
578     [EnableOpt, PromoteKernelArguments](const PassManagerBuilder &,
579                                         legacy::PassManagerBase &PM) {
580       // Add promote kernel arguments pass to the opt pipeline right before
581       // infer address spaces which is needed to do actual address space
582       // rewriting.
583       if (PromoteKernelArguments)
584         PM.add(createAMDGPUPromoteKernelArgumentsPass());
585 
586       // Add infer address spaces pass to the opt pipeline after inlining
587       // but before SROA to increase SROA opportunities.
588       PM.add(createInferAddressSpacesPass());
589 
590       // This should run after inlining to have any chance of doing anything,
591       // and before other cleanup optimizations.
592       PM.add(createAMDGPULowerKernelAttributesPass());
593 
594       // Promote alloca to vector before SROA and loop unroll. If we manage
595       // to eliminate allocas before unroll we may choose to unroll less.
596       if (EnableOpt)
597         PM.add(createAMDGPUPromoteAllocaToVector());
598   });
599 }
600 
601 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
602   AAM.registerFunctionAnalysis<AMDGPUAA>();
603 }
604 
605 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
606   PB.registerPipelineParsingCallback(
607       [this](StringRef PassName, ModulePassManager &PM,
608              ArrayRef<PassBuilder::PipelineElement>) {
609         if (PassName == "amdgpu-propagate-attributes-late") {
610           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
611           return true;
612         }
613         if (PassName == "amdgpu-unify-metadata") {
614           PM.addPass(AMDGPUUnifyMetadataPass());
615           return true;
616         }
617         if (PassName == "amdgpu-printf-runtime-binding") {
618           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
619           return true;
620         }
621         if (PassName == "amdgpu-always-inline") {
622           PM.addPass(AMDGPUAlwaysInlinePass());
623           return true;
624         }
625         if (PassName == "amdgpu-replace-lds-use-with-pointer") {
626           PM.addPass(AMDGPUReplaceLDSUseWithPointerPass());
627           return true;
628         }
629         if (PassName == "amdgpu-lower-module-lds") {
630           PM.addPass(AMDGPULowerModuleLDSPass());
631           return true;
632         }
633         return false;
634       });
635   PB.registerPipelineParsingCallback(
636       [this](StringRef PassName, FunctionPassManager &PM,
637              ArrayRef<PassBuilder::PipelineElement>) {
638         if (PassName == "amdgpu-simplifylib") {
639           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
640           return true;
641         }
642         if (PassName == "amdgpu-usenative") {
643           PM.addPass(AMDGPUUseNativeCallsPass());
644           return true;
645         }
646         if (PassName == "amdgpu-promote-alloca") {
647           PM.addPass(AMDGPUPromoteAllocaPass(*this));
648           return true;
649         }
650         if (PassName == "amdgpu-promote-alloca-to-vector") {
651           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
652           return true;
653         }
654         if (PassName == "amdgpu-lower-kernel-attributes") {
655           PM.addPass(AMDGPULowerKernelAttributesPass());
656           return true;
657         }
658         if (PassName == "amdgpu-propagate-attributes-early") {
659           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
660           return true;
661         }
662         if (PassName == "amdgpu-promote-kernel-arguments") {
663           PM.addPass(AMDGPUPromoteKernelArgumentsPass());
664           return true;
665         }
666         return false;
667       });
668 
669   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
670     FAM.registerPass([&] { return AMDGPUAA(); });
671   });
672 
673   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
674     if (AAName == "amdgpu-aa") {
675       AAM.registerFunctionAnalysis<AMDGPUAA>();
676       return true;
677     }
678     return false;
679   });
680 
681   PB.registerPipelineStartEPCallback(
682       [this](ModulePassManager &PM, OptimizationLevel Level) {
683         FunctionPassManager FPM;
684         FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
685         FPM.addPass(AMDGPUUseNativeCallsPass());
686         if (EnableLibCallSimplify && Level != OptimizationLevel::O0)
687           FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
688         PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
689       });
690 
691   PB.registerPipelineEarlySimplificationEPCallback(
692       [this](ModulePassManager &PM, OptimizationLevel Level) {
693         if (Level == OptimizationLevel::O0)
694           return;
695 
696         PM.addPass(AMDGPUUnifyMetadataPass());
697         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
698 
699         if (InternalizeSymbols) {
700           PM.addPass(InternalizePass(mustPreserveGV));
701         }
702         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
703         if (InternalizeSymbols) {
704           PM.addPass(GlobalDCEPass());
705         }
706         if (EarlyInlineAll && !EnableFunctionCalls)
707           PM.addPass(AMDGPUAlwaysInlinePass());
708       });
709 
710   PB.registerCGSCCOptimizerLateEPCallback(
711       [this](CGSCCPassManager &PM, OptimizationLevel Level) {
712         if (Level == OptimizationLevel::O0)
713           return;
714 
715         FunctionPassManager FPM;
716 
717         // Add promote kernel arguments pass to the opt pipeline right before
718         // infer address spaces which is needed to do actual address space
719         // rewriting.
720         if (Level.getSpeedupLevel() > OptimizationLevel::O1.getSpeedupLevel() &&
721             EnablePromoteKernelArguments)
722           FPM.addPass(AMDGPUPromoteKernelArgumentsPass());
723 
724         // Add infer address spaces pass to the opt pipeline after inlining
725         // but before SROA to increase SROA opportunities.
726         FPM.addPass(InferAddressSpacesPass());
727 
728         // This should run after inlining to have any chance of doing
729         // anything, and before other cleanup optimizations.
730         FPM.addPass(AMDGPULowerKernelAttributesPass());
731 
732         if (Level != OptimizationLevel::O0) {
733           // Promote alloca to vector before SROA and loop unroll. If we
734           // manage to eliminate allocas before unroll we may choose to unroll
735           // less.
736           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
737         }
738 
739         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
740       });
741 }
742 
743 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
744   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
745           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
746           AddrSpace == AMDGPUAS::REGION_ADDRESS)
747              ? -1
748              : 0;
749 }
750 
751 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
752                                               unsigned DestAS) const {
753   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
754          AMDGPU::isFlatGlobalAddrSpace(DestAS);
755 }
756 
757 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
758   const auto *LD = dyn_cast<LoadInst>(V);
759   if (!LD)
760     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
761 
762   // It must be a generic pointer loaded.
763   assert(V->getType()->isPointerTy() &&
764          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
765 
766   const auto *Ptr = LD->getPointerOperand();
767   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
768     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
769   // For a generic pointer loaded from the constant memory, it could be assumed
770   // as a global pointer since the constant memory is only populated on the
771   // host side. As implied by the offload programming model, only global
772   // pointers could be referenced on the host side.
773   return AMDGPUAS::GLOBAL_ADDRESS;
774 }
775 
776 std::pair<const Value *, unsigned>
777 AMDGPUTargetMachine::getPredicatedAddrSpace(const Value *V) const {
778   if (auto *II = dyn_cast<IntrinsicInst>(V)) {
779     switch (II->getIntrinsicID()) {
780     case Intrinsic::amdgcn_is_shared:
781       return std::make_pair(II->getArgOperand(0), AMDGPUAS::LOCAL_ADDRESS);
782     case Intrinsic::amdgcn_is_private:
783       return std::make_pair(II->getArgOperand(0), AMDGPUAS::PRIVATE_ADDRESS);
784     default:
785       break;
786     }
787     return std::make_pair(nullptr, -1);
788   }
789   // Check the global pointer predication based on
790   // (!is_share(p) && !is_private(p)). Note that logic 'and' is commutative and
791   // the order of 'is_shared' and 'is_private' is not significant.
792   Value *Ptr;
793   if (match(
794           const_cast<Value *>(V),
795           m_c_And(m_Not(m_Intrinsic<Intrinsic::amdgcn_is_shared>(m_Value(Ptr))),
796                   m_Not(m_Intrinsic<Intrinsic::amdgcn_is_private>(
797                       m_Deferred(Ptr))))))
798     return std::make_pair(Ptr, AMDGPUAS::GLOBAL_ADDRESS);
799 
800   return std::make_pair(nullptr, -1);
801 }
802 
803 //===----------------------------------------------------------------------===//
804 // GCN Target Machine (SI+)
805 //===----------------------------------------------------------------------===//
806 
807 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
808                                    StringRef CPU, StringRef FS,
809                                    TargetOptions Options,
810                                    Optional<Reloc::Model> RM,
811                                    Optional<CodeModel::Model> CM,
812                                    CodeGenOpt::Level OL, bool JIT)
813     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
814 
815 const TargetSubtargetInfo *
816 GCNTargetMachine::getSubtargetImpl(const Function &F) const {
817   StringRef GPU = getGPUName(F);
818   StringRef FS = getFeatureString(F);
819 
820   SmallString<128> SubtargetKey(GPU);
821   SubtargetKey.append(FS);
822 
823   auto &I = SubtargetMap[SubtargetKey];
824   if (!I) {
825     // This needs to be done before we create a new subtarget since any
826     // creation will depend on the TM and the code generation flags on the
827     // function that reside in TargetOptions.
828     resetTargetOptions(F);
829     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
830   }
831 
832   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
833 
834   return I.get();
835 }
836 
837 TargetTransformInfo
838 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
839   return TargetTransformInfo(GCNTTIImpl(this, F));
840 }
841 
842 //===----------------------------------------------------------------------===//
843 // AMDGPU Pass Setup
844 //===----------------------------------------------------------------------===//
845 
846 std::unique_ptr<CSEConfigBase> llvm::AMDGPUPassConfig::getCSEConfig() const {
847   return getStandardCSEConfigForOpt(TM->getOptLevel());
848 }
849 
850 namespace {
851 
852 class GCNPassConfig final : public AMDGPUPassConfig {
853 public:
854   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
855     : AMDGPUPassConfig(TM, PM) {
856     // It is necessary to know the register usage of the entire call graph.  We
857     // allow calls without EnableAMDGPUFunctionCalls if they are marked
858     // noinline, so this is always required.
859     setRequiresCodeGenSCCOrder(true);
860     substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
861   }
862 
863   GCNTargetMachine &getGCNTargetMachine() const {
864     return getTM<GCNTargetMachine>();
865   }
866 
867   ScheduleDAGInstrs *
868   createMachineScheduler(MachineSchedContext *C) const override;
869 
870   ScheduleDAGInstrs *
871   createPostMachineScheduler(MachineSchedContext *C) const override {
872     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
873     const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
874     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
875     DAG->addMutation(ST.createFillMFMAShadowMutation(DAG->TII));
876     return DAG;
877   }
878 
879   bool addPreISel() override;
880   void addMachineSSAOptimization() override;
881   bool addILPOpts() override;
882   bool addInstSelector() override;
883   bool addIRTranslator() override;
884   void addPreLegalizeMachineIR() override;
885   bool addLegalizeMachineIR() override;
886   void addPreRegBankSelect() override;
887   bool addRegBankSelect() override;
888   void addPreGlobalInstructionSelect() override;
889   bool addGlobalInstructionSelect() override;
890   void addFastRegAlloc() override;
891   void addOptimizedRegAlloc() override;
892 
893   FunctionPass *createSGPRAllocPass(bool Optimized);
894   FunctionPass *createVGPRAllocPass(bool Optimized);
895   FunctionPass *createRegAllocPass(bool Optimized) override;
896 
897   bool addRegAssignAndRewriteFast() override;
898   bool addRegAssignAndRewriteOptimized() override;
899 
900   void addPreRegAlloc() override;
901   bool addPreRewrite() override;
902   void addPostRegAlloc() override;
903   void addPreSched2() override;
904   void addPreEmitPass() override;
905 };
906 
907 } // end anonymous namespace
908 
909 AMDGPUPassConfig::AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
910     : TargetPassConfig(TM, PM) {
911   // Exceptions and StackMaps are not supported, so these passes will never do
912   // anything.
913   disablePass(&StackMapLivenessID);
914   disablePass(&FuncletLayoutID);
915   // Garbage collection is not supported.
916   disablePass(&GCLoweringID);
917   disablePass(&ShadowStackGCLoweringID);
918 }
919 
920 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
921   if (getOptLevel() == CodeGenOpt::Aggressive)
922     addPass(createGVNPass());
923   else
924     addPass(createEarlyCSEPass());
925 }
926 
927 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
928   addPass(createLICMPass());
929   addPass(createSeparateConstOffsetFromGEPPass());
930   addPass(createSpeculativeExecutionPass());
931   // ReassociateGEPs exposes more opportunities for SLSR. See
932   // the example in reassociate-geps-and-slsr.ll.
933   addPass(createStraightLineStrengthReducePass());
934   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
935   // EarlyCSE can reuse.
936   addEarlyCSEOrGVNPass();
937   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
938   addPass(createNaryReassociatePass());
939   // NaryReassociate on GEPs creates redundant common expressions, so run
940   // EarlyCSE after it.
941   addPass(createEarlyCSEPass());
942 }
943 
944 void AMDGPUPassConfig::addIRPasses() {
945   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
946 
947   // There is no reason to run these.
948   disablePass(&StackMapLivenessID);
949   disablePass(&FuncletLayoutID);
950   disablePass(&PatchableFunctionID);
951 
952   addPass(createAMDGPUPrintfRuntimeBinding());
953   addPass(createAMDGPUCtorDtorLoweringPass());
954 
955   // A call to propagate attributes pass in the backend in case opt was not run.
956   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
957 
958   addPass(createAMDGPULowerIntrinsicsPass());
959 
960   // Function calls are not supported, so make sure we inline everything.
961   addPass(createAMDGPUAlwaysInlinePass());
962   addPass(createAlwaysInlinerLegacyPass());
963   // We need to add the barrier noop pass, otherwise adding the function
964   // inlining pass will cause all of the PassConfigs passes to be run
965   // one function at a time, which means if we have a nodule with two
966   // functions, then we will generate code for the first function
967   // without ever running any passes on the second.
968   addPass(createBarrierNoopPass());
969 
970   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
971   if (TM.getTargetTriple().getArch() == Triple::r600)
972     addPass(createR600OpenCLImageTypeLoweringPass());
973 
974   // Replace OpenCL enqueued block function pointers with global variables.
975   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
976 
977   // Can increase LDS used by kernel so runs before PromoteAlloca
978   if (EnableLowerModuleLDS) {
979     // The pass "amdgpu-replace-lds-use-with-pointer" need to be run before the
980     // pass "amdgpu-lower-module-lds", and also it required to be run only if
981     // "amdgpu-lower-module-lds" pass is enabled.
982     if (EnableLDSReplaceWithPointer)
983       addPass(createAMDGPUReplaceLDSUseWithPointerPass());
984 
985     addPass(createAMDGPULowerModuleLDSPass());
986   }
987 
988   if (TM.getOptLevel() > CodeGenOpt::None)
989     addPass(createInferAddressSpacesPass());
990 
991   addPass(createAtomicExpandPass());
992 
993   if (TM.getOptLevel() > CodeGenOpt::None) {
994     addPass(createAMDGPUPromoteAlloca());
995 
996     if (EnableSROA)
997       addPass(createSROAPass());
998     if (isPassEnabled(EnableScalarIRPasses))
999       addStraightLineScalarOptimizationPasses();
1000 
1001     if (EnableAMDGPUAliasAnalysis) {
1002       addPass(createAMDGPUAAWrapperPass());
1003       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
1004                                              AAResults &AAR) {
1005         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
1006           AAR.addAAResult(WrapperPass->getResult());
1007         }));
1008     }
1009 
1010     if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
1011       // TODO: May want to move later or split into an early and late one.
1012       addPass(createAMDGPUCodeGenPreparePass());
1013     }
1014   }
1015 
1016   TargetPassConfig::addIRPasses();
1017 
1018   // EarlyCSE is not always strong enough to clean up what LSR produces. For
1019   // example, GVN can combine
1020   //
1021   //   %0 = add %a, %b
1022   //   %1 = add %b, %a
1023   //
1024   // and
1025   //
1026   //   %0 = shl nsw %a, 2
1027   //   %1 = shl %a, 2
1028   //
1029   // but EarlyCSE can do neither of them.
1030   if (isPassEnabled(EnableScalarIRPasses))
1031     addEarlyCSEOrGVNPass();
1032 }
1033 
1034 void AMDGPUPassConfig::addCodeGenPrepare() {
1035   if (TM->getTargetTriple().getArch() == Triple::amdgcn) {
1036     addPass(createAMDGPUAttributorPass());
1037 
1038     // FIXME: This pass adds 2 hacky attributes that can be replaced with an
1039     // analysis, and should be removed.
1040     addPass(createAMDGPUAnnotateKernelFeaturesPass());
1041   }
1042 
1043   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
1044       EnableLowerKernelArguments)
1045     addPass(createAMDGPULowerKernelArgumentsPass());
1046 
1047   TargetPassConfig::addCodeGenPrepare();
1048 
1049   if (isPassEnabled(EnableLoadStoreVectorizer))
1050     addPass(createLoadStoreVectorizerPass());
1051 
1052   // LowerSwitch pass may introduce unreachable blocks that can
1053   // cause unexpected behavior for subsequent passes. Placing it
1054   // here seems better that these blocks would get cleaned up by
1055   // UnreachableBlockElim inserted next in the pass flow.
1056   addPass(createLowerSwitchPass());
1057 }
1058 
1059 bool AMDGPUPassConfig::addPreISel() {
1060   if (TM->getOptLevel() > CodeGenOpt::None)
1061     addPass(createFlattenCFGPass());
1062   return false;
1063 }
1064 
1065 bool AMDGPUPassConfig::addInstSelector() {
1066   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
1067   return false;
1068 }
1069 
1070 bool AMDGPUPassConfig::addGCPasses() {
1071   // Do nothing. GC is not supported.
1072   return false;
1073 }
1074 
1075 llvm::ScheduleDAGInstrs *
1076 AMDGPUPassConfig::createMachineScheduler(MachineSchedContext *C) const {
1077   ScheduleDAGMILive *DAG = createGenericSchedLive(C);
1078   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1079   return DAG;
1080 }
1081 
1082 //===----------------------------------------------------------------------===//
1083 // GCN Pass Setup
1084 //===----------------------------------------------------------------------===//
1085 
1086 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1087   MachineSchedContext *C) const {
1088   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1089   if (ST.enableSIScheduler())
1090     return createSIMachineScheduler(C);
1091   return createGCNMaxOccupancyMachineScheduler(C);
1092 }
1093 
1094 bool GCNPassConfig::addPreISel() {
1095   AMDGPUPassConfig::addPreISel();
1096 
1097   if (TM->getOptLevel() > CodeGenOpt::None)
1098     addPass(createAMDGPULateCodeGenPreparePass());
1099 
1100   if (isPassEnabled(EnableAtomicOptimizations, CodeGenOpt::Less)) {
1101     addPass(createAMDGPUAtomicOptimizerPass());
1102   }
1103 
1104   if (TM->getOptLevel() > CodeGenOpt::None)
1105     addPass(createSinkingPass());
1106 
1107   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1108   // regions formed by them.
1109   addPass(&AMDGPUUnifyDivergentExitNodesID);
1110   if (!LateCFGStructurize) {
1111     if (EnableStructurizerWorkarounds) {
1112       addPass(createFixIrreduciblePass());
1113       addPass(createUnifyLoopExitsPass());
1114     }
1115     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1116   }
1117   addPass(createAMDGPUAnnotateUniformValues());
1118   if (!LateCFGStructurize) {
1119     addPass(createSIAnnotateControlFlowPass());
1120   }
1121   addPass(createLCSSAPass());
1122 
1123   if (TM->getOptLevel() > CodeGenOpt::Less)
1124     addPass(&AMDGPUPerfHintAnalysisID);
1125 
1126   return false;
1127 }
1128 
1129 void GCNPassConfig::addMachineSSAOptimization() {
1130   TargetPassConfig::addMachineSSAOptimization();
1131 
1132   // We want to fold operands after PeepholeOptimizer has run (or as part of
1133   // it), because it will eliminate extra copies making it easier to fold the
1134   // real source operand. We want to eliminate dead instructions after, so that
1135   // we see fewer uses of the copies. We then need to clean up the dead
1136   // instructions leftover after the operands are folded as well.
1137   //
1138   // XXX - Can we get away without running DeadMachineInstructionElim again?
1139   addPass(&SIFoldOperandsID);
1140   if (EnableDPPCombine)
1141     addPass(&GCNDPPCombineID);
1142   addPass(&SILoadStoreOptimizerID);
1143   if (isPassEnabled(EnableSDWAPeephole)) {
1144     addPass(&SIPeepholeSDWAID);
1145     addPass(&EarlyMachineLICMID);
1146     addPass(&MachineCSEID);
1147     addPass(&SIFoldOperandsID);
1148   }
1149   addPass(&DeadMachineInstructionElimID);
1150   addPass(createSIShrinkInstructionsPass());
1151 }
1152 
1153 bool GCNPassConfig::addILPOpts() {
1154   if (EnableEarlyIfConversion)
1155     addPass(&EarlyIfConverterID);
1156 
1157   TargetPassConfig::addILPOpts();
1158   return false;
1159 }
1160 
1161 bool GCNPassConfig::addInstSelector() {
1162   AMDGPUPassConfig::addInstSelector();
1163   addPass(&SIFixSGPRCopiesID);
1164   addPass(createSILowerI1CopiesPass());
1165   return false;
1166 }
1167 
1168 bool GCNPassConfig::addIRTranslator() {
1169   addPass(new IRTranslator(getOptLevel()));
1170   return false;
1171 }
1172 
1173 void GCNPassConfig::addPreLegalizeMachineIR() {
1174   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1175   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1176   addPass(new Localizer());
1177 }
1178 
1179 bool GCNPassConfig::addLegalizeMachineIR() {
1180   addPass(new Legalizer());
1181   return false;
1182 }
1183 
1184 void GCNPassConfig::addPreRegBankSelect() {
1185   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1186   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1187 }
1188 
1189 bool GCNPassConfig::addRegBankSelect() {
1190   addPass(new RegBankSelect());
1191   return false;
1192 }
1193 
1194 void GCNPassConfig::addPreGlobalInstructionSelect() {
1195   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1196   addPass(createAMDGPURegBankCombiner(IsOptNone));
1197 }
1198 
1199 bool GCNPassConfig::addGlobalInstructionSelect() {
1200   addPass(new InstructionSelect(getOptLevel()));
1201   return false;
1202 }
1203 
1204 void GCNPassConfig::addPreRegAlloc() {
1205   if (LateCFGStructurize) {
1206     addPass(createAMDGPUMachineCFGStructurizerPass());
1207   }
1208 }
1209 
1210 void GCNPassConfig::addFastRegAlloc() {
1211   // FIXME: We have to disable the verifier here because of PHIElimination +
1212   // TwoAddressInstructions disabling it.
1213 
1214   // This must be run immediately after phi elimination and before
1215   // TwoAddressInstructions, otherwise the processing of the tied operand of
1216   // SI_ELSE will introduce a copy of the tied operand source after the else.
1217   insertPass(&PHIEliminationID, &SILowerControlFlowID);
1218 
1219   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1220   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1221 
1222   TargetPassConfig::addFastRegAlloc();
1223 }
1224 
1225 void GCNPassConfig::addOptimizedRegAlloc() {
1226   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1227   // instructions that cause scheduling barriers.
1228   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1229   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1230 
1231   if (OptExecMaskPreRA)
1232     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1233 
1234   if (isPassEnabled(EnablePreRAOptimizations))
1235     insertPass(&RenameIndependentSubregsID, &GCNPreRAOptimizationsID);
1236 
1237   // This is not an essential optimization and it has a noticeable impact on
1238   // compilation time, so we only enable it from O2.
1239   if (TM->getOptLevel() > CodeGenOpt::Less)
1240     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1241 
1242   // FIXME: when an instruction has a Killed operand, and the instruction is
1243   // inside a bundle, seems only the BUNDLE instruction appears as the Kills of
1244   // the register in LiveVariables, this would trigger a failure in verifier,
1245   // we should fix it and enable the verifier.
1246   if (OptVGPRLiveRange)
1247     insertPass(&LiveVariablesID, &SIOptimizeVGPRLiveRangeID);
1248   // This must be run immediately after phi elimination and before
1249   // TwoAddressInstructions, otherwise the processing of the tied operand of
1250   // SI_ELSE will introduce a copy of the tied operand source after the else.
1251   insertPass(&PHIEliminationID, &SILowerControlFlowID);
1252 
1253   if (EnableDCEInRA)
1254     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1255 
1256   TargetPassConfig::addOptimizedRegAlloc();
1257 }
1258 
1259 bool GCNPassConfig::addPreRewrite() {
1260   if (EnableRegReassign)
1261     addPass(&GCNNSAReassignID);
1262   return true;
1263 }
1264 
1265 FunctionPass *GCNPassConfig::createSGPRAllocPass(bool Optimized) {
1266   // Initialize the global default.
1267   llvm::call_once(InitializeDefaultSGPRRegisterAllocatorFlag,
1268                   initializeDefaultSGPRRegisterAllocatorOnce);
1269 
1270   RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
1271   if (Ctor != useDefaultRegisterAllocator)
1272     return Ctor();
1273 
1274   if (Optimized)
1275     return createGreedyRegisterAllocator(onlyAllocateSGPRs);
1276 
1277   return createFastRegisterAllocator(onlyAllocateSGPRs, false);
1278 }
1279 
1280 FunctionPass *GCNPassConfig::createVGPRAllocPass(bool Optimized) {
1281   // Initialize the global default.
1282   llvm::call_once(InitializeDefaultVGPRRegisterAllocatorFlag,
1283                   initializeDefaultVGPRRegisterAllocatorOnce);
1284 
1285   RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
1286   if (Ctor != useDefaultRegisterAllocator)
1287     return Ctor();
1288 
1289   if (Optimized)
1290     return createGreedyVGPRRegisterAllocator();
1291 
1292   return createFastVGPRRegisterAllocator();
1293 }
1294 
1295 FunctionPass *GCNPassConfig::createRegAllocPass(bool Optimized) {
1296   llvm_unreachable("should not be used");
1297 }
1298 
1299 static const char RegAllocOptNotSupportedMessage[] =
1300   "-regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc";
1301 
1302 bool GCNPassConfig::addRegAssignAndRewriteFast() {
1303   if (!usingDefaultRegAlloc())
1304     report_fatal_error(RegAllocOptNotSupportedMessage);
1305 
1306   addPass(createSGPRAllocPass(false));
1307 
1308   // Equivalent of PEI for SGPRs.
1309   addPass(&SILowerSGPRSpillsID);
1310 
1311   addPass(createVGPRAllocPass(false));
1312   return true;
1313 }
1314 
1315 bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
1316   if (!usingDefaultRegAlloc())
1317     report_fatal_error(RegAllocOptNotSupportedMessage);
1318 
1319   addPass(createSGPRAllocPass(true));
1320 
1321   // Commit allocated register changes. This is mostly necessary because too
1322   // many things rely on the use lists of the physical registers, such as the
1323   // verifier. This is only necessary with allocators which use LiveIntervals,
1324   // since FastRegAlloc does the replacements itself.
1325   addPass(createVirtRegRewriter(false));
1326 
1327   // Equivalent of PEI for SGPRs.
1328   addPass(&SILowerSGPRSpillsID);
1329 
1330   addPass(createVGPRAllocPass(true));
1331 
1332   addPreRewrite();
1333   addPass(&VirtRegRewriterID);
1334 
1335   return true;
1336 }
1337 
1338 void GCNPassConfig::addPostRegAlloc() {
1339   addPass(&SIFixVGPRCopiesID);
1340   if (getOptLevel() > CodeGenOpt::None)
1341     addPass(&SIOptimizeExecMaskingID);
1342   TargetPassConfig::addPostRegAlloc();
1343 }
1344 
1345 void GCNPassConfig::addPreSched2() {
1346   if (TM->getOptLevel() > CodeGenOpt::None)
1347     addPass(createSIShrinkInstructionsPass());
1348   addPass(&SIPostRABundlerID);
1349 }
1350 
1351 void GCNPassConfig::addPreEmitPass() {
1352   addPass(createSIMemoryLegalizerPass());
1353   addPass(createSIInsertWaitcntsPass());
1354 
1355   addPass(createSIModeRegisterPass());
1356 
1357   if (getOptLevel() > CodeGenOpt::None)
1358     addPass(&SIInsertHardClausesID);
1359 
1360   addPass(&SILateBranchLoweringPassID);
1361   if (getOptLevel() > CodeGenOpt::None)
1362     addPass(&SIPreEmitPeepholeID);
1363   // The hazard recognizer that runs as part of the post-ra scheduler does not
1364   // guarantee to be able handle all hazards correctly. This is because if there
1365   // are multiple scheduling regions in a basic block, the regions are scheduled
1366   // bottom up, so when we begin to schedule a region we don't know what
1367   // instructions were emitted directly before it.
1368   //
1369   // Here we add a stand-alone hazard recognizer pass which can handle all
1370   // cases.
1371   addPass(&PostRAHazardRecognizerID);
1372   addPass(&BranchRelaxationPassID);
1373 }
1374 
1375 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1376   return new GCNPassConfig(*this, PM);
1377 }
1378 
1379 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1380   return new yaml::SIMachineFunctionInfo();
1381 }
1382 
1383 yaml::MachineFunctionInfo *
1384 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1385   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1386   return new yaml::SIMachineFunctionInfo(
1387       *MFI, *MF.getSubtarget().getRegisterInfo(), MF);
1388 }
1389 
1390 bool GCNTargetMachine::parseMachineFunctionInfo(
1391     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1392     SMDiagnostic &Error, SMRange &SourceRange) const {
1393   const yaml::SIMachineFunctionInfo &YamlMFI =
1394       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1395   MachineFunction &MF = PFS.MF;
1396   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1397 
1398   if (MFI->initializeBaseYamlFields(YamlMFI, MF, PFS, Error, SourceRange))
1399     return true;
1400 
1401   if (MFI->Occupancy == 0) {
1402     // Fixup the subtarget dependent default value.
1403     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1404     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1405   }
1406 
1407   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1408     Register TempReg;
1409     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1410       SourceRange = RegName.SourceRange;
1411       return true;
1412     }
1413     RegVal = TempReg;
1414 
1415     return false;
1416   };
1417 
1418   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1419     // Create a diagnostic for a the register string literal.
1420     const MemoryBuffer &Buffer =
1421         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1422     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1423                          RegName.Value.size(), SourceMgr::DK_Error,
1424                          "incorrect register class for field", RegName.Value,
1425                          None, None);
1426     SourceRange = RegName.SourceRange;
1427     return true;
1428   };
1429 
1430   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1431       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1432       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1433     return true;
1434 
1435   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1436       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1437     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1438   }
1439 
1440   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1441       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1442     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1443   }
1444 
1445   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1446       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1447     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1448   }
1449 
1450   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1451                                    const TargetRegisterClass &RC,
1452                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1453                                    unsigned SystemSGPRs) {
1454     // Skip parsing if it's not present.
1455     if (!A)
1456       return false;
1457 
1458     if (A->IsRegister) {
1459       Register Reg;
1460       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1461         SourceRange = A->RegisterName.SourceRange;
1462         return true;
1463       }
1464       if (!RC.contains(Reg))
1465         return diagnoseRegisterClass(A->RegisterName);
1466       Arg = ArgDescriptor::createRegister(Reg);
1467     } else
1468       Arg = ArgDescriptor::createStack(A->StackOffset);
1469     // Check and apply the optional mask.
1470     if (A->Mask)
1471       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1472 
1473     MFI->NumUserSGPRs += UserSGPRs;
1474     MFI->NumSystemSGPRs += SystemSGPRs;
1475     return false;
1476   };
1477 
1478   if (YamlMFI.ArgInfo &&
1479       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1480                              AMDGPU::SGPR_128RegClass,
1481                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1482        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1483                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1484                              2, 0) ||
1485        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1486                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1487        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1488                              AMDGPU::SReg_64RegClass,
1489                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1490        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1491                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1492                              2, 0) ||
1493        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1494                              AMDGPU::SReg_64RegClass,
1495                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1496        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1497                              AMDGPU::SGPR_32RegClass,
1498                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1499        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1500                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1501                              0, 1) ||
1502        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1503                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1504                              0, 1) ||
1505        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1506                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1507                              0, 1) ||
1508        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1509                              AMDGPU::SGPR_32RegClass,
1510                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1511        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1512                              AMDGPU::SGPR_32RegClass,
1513                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1514        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1515                              AMDGPU::SReg_64RegClass,
1516                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1517        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1518                              AMDGPU::SReg_64RegClass,
1519                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1520        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1521                              AMDGPU::VGPR_32RegClass,
1522                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1523        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1524                              AMDGPU::VGPR_32RegClass,
1525                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1526        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1527                              AMDGPU::VGPR_32RegClass,
1528                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1529     return true;
1530 
1531   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1532   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1533   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1534   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1535   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1536   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1537 
1538   return false;
1539 }
1540