1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUExportClustering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
28 #include "R600MachineScheduler.h"
29 #include "SIMachineFunctionInfo.h"
30 #include "SIMachineScheduler.h"
31 #include "TargetInfo/AMDGPUTargetInfo.h"
32 #include "llvm/Analysis/CGSCCPassManager.h"
33 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
34 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
35 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
36 #include "llvm/CodeGen/GlobalISel/Localizer.h"
37 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
38 #include "llvm/CodeGen/MIRParser/MIParser.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/CodeGen/TargetPassConfig.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/LegacyPassManager.h"
44 #include "llvm/IR/PassManager.h"
45 #include "llvm/InitializePasses.h"
46 #include "llvm/Pass.h"
47 #include "llvm/Passes/PassBuilder.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/TargetRegistry.h"
51 #include "llvm/Target/TargetLoweringObjectFile.h"
52 #include "llvm/Transforms/IPO.h"
53 #include "llvm/Transforms/IPO/AlwaysInliner.h"
54 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
55 #include "llvm/Transforms/Scalar.h"
56 #include "llvm/Transforms/Scalar/GVN.h"
57 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
58 #include "llvm/Transforms/Utils.h"
59 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
60 #include "llvm/Transforms/Vectorize.h"
61 #include <memory>
62 
63 using namespace llvm;
64 
65 static cl::opt<bool> EnableR600StructurizeCFG(
66   "r600-ir-structurize",
67   cl::desc("Use StructurizeCFG IR pass"),
68   cl::init(true));
69 
70 static cl::opt<bool> EnableSROA(
71   "amdgpu-sroa",
72   cl::desc("Run SROA after promote alloca pass"),
73   cl::ReallyHidden,
74   cl::init(true));
75 
76 static cl::opt<bool>
77 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
78                         cl::desc("Run early if-conversion"),
79                         cl::init(false));
80 
81 static cl::opt<bool>
82 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
83             cl::desc("Run pre-RA exec mask optimizations"),
84             cl::init(true));
85 
86 static cl::opt<bool> EnableR600IfConvert(
87   "r600-if-convert",
88   cl::desc("Use if conversion pass"),
89   cl::ReallyHidden,
90   cl::init(true));
91 
92 // Option to disable vectorizer for tests.
93 static cl::opt<bool> EnableLoadStoreVectorizer(
94   "amdgpu-load-store-vectorizer",
95   cl::desc("Enable load store vectorizer"),
96   cl::init(true),
97   cl::Hidden);
98 
99 // Option to control global loads scalarization
100 static cl::opt<bool> ScalarizeGlobal(
101   "amdgpu-scalarize-global-loads",
102   cl::desc("Enable global load scalarization"),
103   cl::init(true),
104   cl::Hidden);
105 
106 // Option to run internalize pass.
107 static cl::opt<bool> InternalizeSymbols(
108   "amdgpu-internalize-symbols",
109   cl::desc("Enable elimination of non-kernel functions and unused globals"),
110   cl::init(false),
111   cl::Hidden);
112 
113 // Option to inline all early.
114 static cl::opt<bool> EarlyInlineAll(
115   "amdgpu-early-inline-all",
116   cl::desc("Inline all functions early"),
117   cl::init(false),
118   cl::Hidden);
119 
120 static cl::opt<bool> EnableSDWAPeephole(
121   "amdgpu-sdwa-peephole",
122   cl::desc("Enable SDWA peepholer"),
123   cl::init(true));
124 
125 static cl::opt<bool> EnableDPPCombine(
126   "amdgpu-dpp-combine",
127   cl::desc("Enable DPP combiner"),
128   cl::init(true));
129 
130 // Enable address space based alias analysis
131 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
132   cl::desc("Enable AMDGPU Alias Analysis"),
133   cl::init(true));
134 
135 // Option to run late CFG structurizer
136 static cl::opt<bool, true> LateCFGStructurize(
137   "amdgpu-late-structurize",
138   cl::desc("Enable late CFG structurization"),
139   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
140   cl::Hidden);
141 
142 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
143   "amdgpu-function-calls",
144   cl::desc("Enable AMDGPU function call support"),
145   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
146   cl::init(true),
147   cl::Hidden);
148 
149 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
150   "amdgpu-fixed-function-abi",
151   cl::desc("Enable all implicit function arguments"),
152   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
153   cl::init(false),
154   cl::Hidden);
155 
156 // Enable lib calls simplifications
157 static cl::opt<bool> EnableLibCallSimplify(
158   "amdgpu-simplify-libcall",
159   cl::desc("Enable amdgpu library simplifications"),
160   cl::init(true),
161   cl::Hidden);
162 
163 static cl::opt<bool> EnableLowerKernelArguments(
164   "amdgpu-ir-lower-kernel-arguments",
165   cl::desc("Lower kernel argument loads in IR pass"),
166   cl::init(true),
167   cl::Hidden);
168 
169 static cl::opt<bool> EnableRegReassign(
170   "amdgpu-reassign-regs",
171   cl::desc("Enable register reassign optimizations on gfx10+"),
172   cl::init(true),
173   cl::Hidden);
174 
175 // Enable atomic optimization
176 static cl::opt<bool> EnableAtomicOptimizations(
177   "amdgpu-atomic-optimizations",
178   cl::desc("Enable atomic optimizations"),
179   cl::init(false),
180   cl::Hidden);
181 
182 // Enable Mode register optimization
183 static cl::opt<bool> EnableSIModeRegisterPass(
184   "amdgpu-mode-register",
185   cl::desc("Enable mode register pass"),
186   cl::init(true),
187   cl::Hidden);
188 
189 // Option is used in lit tests to prevent deadcoding of patterns inspected.
190 static cl::opt<bool>
191 EnableDCEInRA("amdgpu-dce-in-ra",
192     cl::init(true), cl::Hidden,
193     cl::desc("Enable machine DCE inside regalloc"));
194 
195 static cl::opt<bool> EnableScalarIRPasses(
196   "amdgpu-scalar-ir-passes",
197   cl::desc("Enable scalar IR passes"),
198   cl::init(true),
199   cl::Hidden);
200 
201 static cl::opt<bool> EnableStructurizerWorkarounds(
202     "amdgpu-enable-structurizer-workarounds",
203     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
204     cl::Hidden);
205 
206 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
207   // Register the target
208   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
209   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
210 
211   PassRegistry *PR = PassRegistry::getPassRegistry();
212   initializeR600ClauseMergePassPass(*PR);
213   initializeR600ControlFlowFinalizerPass(*PR);
214   initializeR600PacketizerPass(*PR);
215   initializeR600ExpandSpecialInstrsPassPass(*PR);
216   initializeR600VectorRegMergerPass(*PR);
217   initializeGlobalISel(*PR);
218   initializeAMDGPUDAGToDAGISelPass(*PR);
219   initializeGCNDPPCombinePass(*PR);
220   initializeSILowerI1CopiesPass(*PR);
221   initializeSILowerSGPRSpillsPass(*PR);
222   initializeSIFixSGPRCopiesPass(*PR);
223   initializeSIFixVGPRCopiesPass(*PR);
224   initializeSIFoldOperandsPass(*PR);
225   initializeSIPeepholeSDWAPass(*PR);
226   initializeSIShrinkInstructionsPass(*PR);
227   initializeSIOptimizeExecMaskingPreRAPass(*PR);
228   initializeSILoadStoreOptimizerPass(*PR);
229   initializeAMDGPUFixFunctionBitcastsPass(*PR);
230   initializeAMDGPUAlwaysInlinePass(*PR);
231   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
232   initializeAMDGPUAnnotateUniformValuesPass(*PR);
233   initializeAMDGPUArgumentUsageInfoPass(*PR);
234   initializeAMDGPUAtomicOptimizerPass(*PR);
235   initializeAMDGPULowerKernelArgumentsPass(*PR);
236   initializeAMDGPULowerKernelAttributesPass(*PR);
237   initializeAMDGPULowerIntrinsicsPass(*PR);
238   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
239   initializeAMDGPUPostLegalizerCombinerPass(*PR);
240   initializeAMDGPUPreLegalizerCombinerPass(*PR);
241   initializeAMDGPUPromoteAllocaPass(*PR);
242   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
243   initializeAMDGPUCodeGenPreparePass(*PR);
244   initializeAMDGPULateCodeGenPreparePass(*PR);
245   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
246   initializeAMDGPUPropagateAttributesLatePass(*PR);
247   initializeAMDGPURewriteOutArgumentsPass(*PR);
248   initializeAMDGPUUnifyMetadataPass(*PR);
249   initializeSIAnnotateControlFlowPass(*PR);
250   initializeSIInsertHardClausesPass(*PR);
251   initializeSIInsertWaitcntsPass(*PR);
252   initializeSIModeRegisterPass(*PR);
253   initializeSIWholeQuadModePass(*PR);
254   initializeSILowerControlFlowPass(*PR);
255   initializeSIRemoveShortExecBranchesPass(*PR);
256   initializeSIPreEmitPeepholePass(*PR);
257   initializeSIInsertSkipsPass(*PR);
258   initializeSIMemoryLegalizerPass(*PR);
259   initializeSIOptimizeExecMaskingPass(*PR);
260   initializeSIPreAllocateWWMRegsPass(*PR);
261   initializeSIFormMemoryClausesPass(*PR);
262   initializeSIPostRABundlerPass(*PR);
263   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
264   initializeAMDGPUAAWrapperPassPass(*PR);
265   initializeAMDGPUExternalAAWrapperPass(*PR);
266   initializeAMDGPUUseNativeCallsPass(*PR);
267   initializeAMDGPUSimplifyLibCallsPass(*PR);
268   initializeAMDGPUInlinerPass(*PR);
269   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
270   initializeGCNRegBankReassignPass(*PR);
271   initializeGCNNSAReassignPass(*PR);
272   initializeSIAddIMGInitPass(*PR);
273 }
274 
275 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
276   return std::make_unique<AMDGPUTargetObjectFile>();
277 }
278 
279 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
280   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
281 }
282 
283 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
284   return new SIScheduleDAGMI(C);
285 }
286 
287 static ScheduleDAGInstrs *
288 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
289   ScheduleDAGMILive *DAG =
290     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
291   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
292   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
293   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
294   return DAG;
295 }
296 
297 static ScheduleDAGInstrs *
298 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
299   auto DAG = new GCNIterativeScheduler(C,
300     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
301   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
302   return DAG;
303 }
304 
305 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
306   return new GCNIterativeScheduler(C,
307     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
308 }
309 
310 static ScheduleDAGInstrs *
311 createIterativeILPMachineScheduler(MachineSchedContext *C) {
312   auto DAG = new GCNIterativeScheduler(C,
313     GCNIterativeScheduler::SCHEDULE_ILP);
314   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
315   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
316   return DAG;
317 }
318 
319 static MachineSchedRegistry
320 R600SchedRegistry("r600", "Run R600's custom scheduler",
321                    createR600MachineScheduler);
322 
323 static MachineSchedRegistry
324 SISchedRegistry("si", "Run SI's custom scheduler",
325                 createSIMachineScheduler);
326 
327 static MachineSchedRegistry
328 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
329                              "Run GCN scheduler to maximize occupancy",
330                              createGCNMaxOccupancyMachineScheduler);
331 
332 static MachineSchedRegistry
333 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
334   "Run GCN scheduler to maximize occupancy (experimental)",
335   createIterativeGCNMaxOccupancyMachineScheduler);
336 
337 static MachineSchedRegistry
338 GCNMinRegSchedRegistry("gcn-minreg",
339   "Run GCN iterative scheduler for minimal register usage (experimental)",
340   createMinRegScheduler);
341 
342 static MachineSchedRegistry
343 GCNILPSchedRegistry("gcn-ilp",
344   "Run GCN iterative scheduler for ILP scheduling (experimental)",
345   createIterativeILPMachineScheduler);
346 
347 static StringRef computeDataLayout(const Triple &TT) {
348   if (TT.getArch() == Triple::r600) {
349     // 32-bit pointers.
350     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
351            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
352   }
353 
354   // 32-bit private, local, and region pointers. 64-bit global, constant and
355   // flat, non-integral buffer fat pointers.
356   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
357          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
358          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
359          "-ni:7";
360 }
361 
362 LLVM_READNONE
363 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
364   if (!GPU.empty())
365     return GPU;
366 
367   // Need to default to a target with flat support for HSA.
368   if (TT.getArch() == Triple::amdgcn)
369     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
370 
371   return "r600";
372 }
373 
374 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
375   // The AMDGPU toolchain only supports generating shared objects, so we
376   // must always use PIC.
377   return Reloc::PIC_;
378 }
379 
380 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
381                                          StringRef CPU, StringRef FS,
382                                          TargetOptions Options,
383                                          Optional<Reloc::Model> RM,
384                                          Optional<CodeModel::Model> CM,
385                                          CodeGenOpt::Level OptLevel)
386     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
387                         FS, Options, getEffectiveRelocModel(RM),
388                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
389       TLOF(createTLOF(getTargetTriple())) {
390   initAsmInfo();
391   if (TT.getArch() == Triple::amdgcn) {
392     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
393       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
394     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
395       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
396   }
397 }
398 
399 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
400 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
401 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
402 
403 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
404 
405 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
406   Attribute GPUAttr = F.getFnAttribute("target-cpu");
407   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
408 }
409 
410 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
411   Attribute FSAttr = F.getFnAttribute("target-features");
412 
413   return FSAttr.isValid() ? FSAttr.getValueAsString()
414                           : getTargetFeatureString();
415 }
416 
417 /// Predicate for Internalize pass.
418 static bool mustPreserveGV(const GlobalValue &GV) {
419   if (const Function *F = dyn_cast<Function>(&GV))
420     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
421 
422   return !GV.use_empty();
423 }
424 
425 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
426   Builder.DivergentTarget = true;
427 
428   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
429   bool Internalize = InternalizeSymbols;
430   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
431   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
432   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
433 
434   if (EnableFunctionCalls) {
435     delete Builder.Inliner;
436     Builder.Inliner = createAMDGPUFunctionInliningPass();
437   }
438 
439   Builder.addExtension(
440     PassManagerBuilder::EP_ModuleOptimizerEarly,
441     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
442                                                legacy::PassManagerBase &PM) {
443       if (AMDGPUAA) {
444         PM.add(createAMDGPUAAWrapperPass());
445         PM.add(createAMDGPUExternalAAWrapperPass());
446       }
447       PM.add(createAMDGPUUnifyMetadataPass());
448       PM.add(createAMDGPUPrintfRuntimeBinding());
449       if (Internalize)
450         PM.add(createInternalizePass(mustPreserveGV));
451       PM.add(createAMDGPUPropagateAttributesLatePass(this));
452       if (Internalize)
453         PM.add(createGlobalDCEPass());
454       if (EarlyInline)
455         PM.add(createAMDGPUAlwaysInlinePass(false));
456   });
457 
458   Builder.addExtension(
459     PassManagerBuilder::EP_EarlyAsPossible,
460     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
461                                       legacy::PassManagerBase &PM) {
462       if (AMDGPUAA) {
463         PM.add(createAMDGPUAAWrapperPass());
464         PM.add(createAMDGPUExternalAAWrapperPass());
465       }
466       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
467       PM.add(llvm::createAMDGPUUseNativeCallsPass());
468       if (LibCallSimplify)
469         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
470   });
471 
472   Builder.addExtension(
473     PassManagerBuilder::EP_CGSCCOptimizerLate,
474     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
475       // Add infer address spaces pass to the opt pipeline after inlining
476       // but before SROA to increase SROA opportunities.
477       PM.add(createInferAddressSpacesPass());
478 
479       // This should run after inlining to have any chance of doing anything,
480       // and before other cleanup optimizations.
481       PM.add(createAMDGPULowerKernelAttributesPass());
482 
483       // Promote alloca to vector before SROA and loop unroll. If we manage
484       // to eliminate allocas before unroll we may choose to unroll less.
485       if (EnableOpt)
486         PM.add(createAMDGPUPromoteAllocaToVector());
487   });
488 }
489 
490 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
491                                                        bool DebugPassManager) {
492   PB.registerPipelineParsingCallback(
493       [this](StringRef PassName, FunctionPassManager &PM,
494              ArrayRef<PassBuilder::PipelineElement>) {
495         if (PassName == "amdgpu-simplifylib") {
496           PM.addPass(AMDGPUSimplifyLibCallsPass());
497           return true;
498         }
499         if (PassName == "amdgpu-usenative") {
500           PM.addPass(AMDGPUUseNativeCallsPass());
501           return true;
502         }
503         if (PassName == "amdgpu-promote-alloca") {
504           PM.addPass(AMDGPUPromoteAllocaPass(*this));
505           return true;
506         }
507         if (PassName == "amdgpu-promote-alloca-to-vector") {
508           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
509           return true;
510         }
511         if (PassName == "amdgpu-lower-kernel-attributes") {
512           PM.addPass(AMDGPULowerKernelAttributesPass());
513           return true;
514         }
515         return false;
516       });
517 
518   PB.registerPipelineStartEPCallback([DebugPassManager](
519                                          ModulePassManager &PM,
520                                          PassBuilder::OptimizationLevel Level) {
521     FunctionPassManager FPM(DebugPassManager);
522     FPM.addPass(AMDGPUUseNativeCallsPass());
523     if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
524       FPM.addPass(AMDGPUSimplifyLibCallsPass());
525     PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
526   });
527 
528   PB.registerCGSCCOptimizerLateEPCallback(
529       [this, DebugPassManager](CGSCCPassManager &PM,
530                                PassBuilder::OptimizationLevel Level) {
531           FunctionPassManager FPM(DebugPassManager);
532 
533           // Add infer address spaces pass to the opt pipeline after inlining
534           // but before SROA to increase SROA opportunities.
535           FPM.addPass(InferAddressSpacesPass());
536 
537           // This should run after inlining to have any chance of doing
538           // anything, and before other cleanup optimizations.
539           FPM.addPass(AMDGPULowerKernelAttributesPass());
540 
541           if (Level != PassBuilder::OptimizationLevel::O0) {
542             // Promote alloca to vector before SROA and loop unroll. If we
543             // manage to eliminate allocas before unroll we may choose to unroll
544             // less.
545             FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
546           }
547 
548           PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
549       });
550 }
551 
552 //===----------------------------------------------------------------------===//
553 // R600 Target Machine (R600 -> Cayman)
554 //===----------------------------------------------------------------------===//
555 
556 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
557                                      StringRef CPU, StringRef FS,
558                                      TargetOptions Options,
559                                      Optional<Reloc::Model> RM,
560                                      Optional<CodeModel::Model> CM,
561                                      CodeGenOpt::Level OL, bool JIT)
562     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
563   setRequiresStructuredCFG(true);
564 
565   // Override the default since calls aren't supported for r600.
566   if (EnableFunctionCalls &&
567       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
568     EnableFunctionCalls = false;
569 }
570 
571 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
572   const Function &F) const {
573   StringRef GPU = getGPUName(F);
574   StringRef FS = getFeatureString(F);
575 
576   SmallString<128> SubtargetKey(GPU);
577   SubtargetKey.append(FS);
578 
579   auto &I = SubtargetMap[SubtargetKey];
580   if (!I) {
581     // This needs to be done before we create a new subtarget since any
582     // creation will depend on the TM and the code generation flags on the
583     // function that reside in TargetOptions.
584     resetTargetOptions(F);
585     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
586   }
587 
588   return I.get();
589 }
590 
591 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
592                                               unsigned DestAS) const {
593   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
594          AMDGPU::isFlatGlobalAddrSpace(DestAS);
595 }
596 
597 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
598   const auto *LD = dyn_cast<LoadInst>(V);
599   if (!LD)
600     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
601 
602   // It must be a generic pointer loaded.
603   assert(V->getType()->isPointerTy() &&
604          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
605 
606   const auto *Ptr = LD->getPointerOperand();
607   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
608     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
609   // For a generic pointer loaded from the constant memory, it could be assumed
610   // as a global pointer since the constant memory is only populated on the
611   // host side. As implied by the offload programming model, only global
612   // pointers could be referenced on the host side.
613   return AMDGPUAS::GLOBAL_ADDRESS;
614 }
615 
616 TargetTransformInfo
617 R600TargetMachine::getTargetTransformInfo(const Function &F) {
618   return TargetTransformInfo(R600TTIImpl(this, F));
619 }
620 
621 //===----------------------------------------------------------------------===//
622 // GCN Target Machine (SI+)
623 //===----------------------------------------------------------------------===//
624 
625 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
626                                    StringRef CPU, StringRef FS,
627                                    TargetOptions Options,
628                                    Optional<Reloc::Model> RM,
629                                    Optional<CodeModel::Model> CM,
630                                    CodeGenOpt::Level OL, bool JIT)
631     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
632 
633 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
634   StringRef GPU = getGPUName(F);
635   StringRef FS = getFeatureString(F);
636 
637   SmallString<128> SubtargetKey(GPU);
638   SubtargetKey.append(FS);
639 
640   auto &I = SubtargetMap[SubtargetKey];
641   if (!I) {
642     // This needs to be done before we create a new subtarget since any
643     // creation will depend on the TM and the code generation flags on the
644     // function that reside in TargetOptions.
645     resetTargetOptions(F);
646     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
647   }
648 
649   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
650 
651   return I.get();
652 }
653 
654 TargetTransformInfo
655 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
656   return TargetTransformInfo(GCNTTIImpl(this, F));
657 }
658 
659 //===----------------------------------------------------------------------===//
660 // AMDGPU Pass Setup
661 //===----------------------------------------------------------------------===//
662 
663 namespace {
664 
665 class AMDGPUPassConfig : public TargetPassConfig {
666 public:
667   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
668     : TargetPassConfig(TM, PM) {
669     // Exceptions and StackMaps are not supported, so these passes will never do
670     // anything.
671     disablePass(&StackMapLivenessID);
672     disablePass(&FuncletLayoutID);
673   }
674 
675   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
676     return getTM<AMDGPUTargetMachine>();
677   }
678 
679   ScheduleDAGInstrs *
680   createMachineScheduler(MachineSchedContext *C) const override {
681     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
682     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
683     return DAG;
684   }
685 
686   void addEarlyCSEOrGVNPass();
687   void addStraightLineScalarOptimizationPasses();
688   void addIRPasses() override;
689   void addCodeGenPrepare() override;
690   bool addPreISel() override;
691   bool addInstSelector() override;
692   bool addGCPasses() override;
693 
694   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
695 };
696 
697 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
698   return getStandardCSEConfigForOpt(TM->getOptLevel());
699 }
700 
701 class R600PassConfig final : public AMDGPUPassConfig {
702 public:
703   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
704     : AMDGPUPassConfig(TM, PM) {}
705 
706   ScheduleDAGInstrs *createMachineScheduler(
707     MachineSchedContext *C) const override {
708     return createR600MachineScheduler(C);
709   }
710 
711   bool addPreISel() override;
712   bool addInstSelector() override;
713   void addPreRegAlloc() override;
714   void addPreSched2() override;
715   void addPreEmitPass() override;
716 };
717 
718 class GCNPassConfig final : public AMDGPUPassConfig {
719 public:
720   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
721     : AMDGPUPassConfig(TM, PM) {
722     // It is necessary to know the register usage of the entire call graph.  We
723     // allow calls without EnableAMDGPUFunctionCalls if they are marked
724     // noinline, so this is always required.
725     setRequiresCodeGenSCCOrder(true);
726   }
727 
728   GCNTargetMachine &getGCNTargetMachine() const {
729     return getTM<GCNTargetMachine>();
730   }
731 
732   ScheduleDAGInstrs *
733   createMachineScheduler(MachineSchedContext *C) const override;
734 
735   bool addPreISel() override;
736   void addMachineSSAOptimization() override;
737   bool addILPOpts() override;
738   bool addInstSelector() override;
739   bool addIRTranslator() override;
740   void addPreLegalizeMachineIR() override;
741   bool addLegalizeMachineIR() override;
742   void addPreRegBankSelect() override;
743   bool addRegBankSelect() override;
744   bool addGlobalInstructionSelect() override;
745   void addFastRegAlloc() override;
746   void addOptimizedRegAlloc() override;
747   void addPreRegAlloc() override;
748   bool addPreRewrite() override;
749   void addPostRegAlloc() override;
750   void addPreSched2() override;
751   void addPreEmitPass() override;
752 };
753 
754 } // end anonymous namespace
755 
756 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
757   if (getOptLevel() == CodeGenOpt::Aggressive)
758     addPass(createGVNPass());
759   else
760     addPass(createEarlyCSEPass());
761 }
762 
763 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
764   addPass(createLICMPass());
765   addPass(createSeparateConstOffsetFromGEPPass());
766   addPass(createSpeculativeExecutionPass());
767   // ReassociateGEPs exposes more opportunites for SLSR. See
768   // the example in reassociate-geps-and-slsr.ll.
769   addPass(createStraightLineStrengthReducePass());
770   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
771   // EarlyCSE can reuse.
772   addEarlyCSEOrGVNPass();
773   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
774   addPass(createNaryReassociatePass());
775   // NaryReassociate on GEPs creates redundant common expressions, so run
776   // EarlyCSE after it.
777   addPass(createEarlyCSEPass());
778 }
779 
780 void AMDGPUPassConfig::addIRPasses() {
781   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
782 
783   // There is no reason to run these.
784   disablePass(&StackMapLivenessID);
785   disablePass(&FuncletLayoutID);
786   disablePass(&PatchableFunctionID);
787 
788   addPass(createAMDGPUPrintfRuntimeBinding());
789 
790   // This must occur before inlining, as the inliner will not look through
791   // bitcast calls.
792   addPass(createAMDGPUFixFunctionBitcastsPass());
793 
794   // A call to propagate attributes pass in the backend in case opt was not run.
795   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
796 
797   addPass(createAtomicExpandPass());
798 
799 
800   addPass(createAMDGPULowerIntrinsicsPass());
801 
802   // Function calls are not supported, so make sure we inline everything.
803   addPass(createAMDGPUAlwaysInlinePass());
804   addPass(createAlwaysInlinerLegacyPass());
805   // We need to add the barrier noop pass, otherwise adding the function
806   // inlining pass will cause all of the PassConfigs passes to be run
807   // one function at a time, which means if we have a nodule with two
808   // functions, then we will generate code for the first function
809   // without ever running any passes on the second.
810   addPass(createBarrierNoopPass());
811 
812   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
813   if (TM.getTargetTriple().getArch() == Triple::r600)
814     addPass(createR600OpenCLImageTypeLoweringPass());
815 
816   // Replace OpenCL enqueued block function pointers with global variables.
817   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
818 
819   if (TM.getOptLevel() > CodeGenOpt::None) {
820     addPass(createInferAddressSpacesPass());
821     addPass(createAMDGPUPromoteAlloca());
822 
823     if (EnableSROA)
824       addPass(createSROAPass());
825 
826     if (EnableScalarIRPasses)
827       addStraightLineScalarOptimizationPasses();
828 
829     if (EnableAMDGPUAliasAnalysis) {
830       addPass(createAMDGPUAAWrapperPass());
831       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
832                                              AAResults &AAR) {
833         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
834           AAR.addAAResult(WrapperPass->getResult());
835         }));
836     }
837   }
838 
839   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
840     // TODO: May want to move later or split into an early and late one.
841     addPass(createAMDGPUCodeGenPreparePass());
842   }
843 
844   TargetPassConfig::addIRPasses();
845 
846   // EarlyCSE is not always strong enough to clean up what LSR produces. For
847   // example, GVN can combine
848   //
849   //   %0 = add %a, %b
850   //   %1 = add %b, %a
851   //
852   // and
853   //
854   //   %0 = shl nsw %a, 2
855   //   %1 = shl %a, 2
856   //
857   // but EarlyCSE can do neither of them.
858   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
859     addEarlyCSEOrGVNPass();
860 }
861 
862 void AMDGPUPassConfig::addCodeGenPrepare() {
863   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
864     addPass(createAMDGPUAnnotateKernelFeaturesPass());
865 
866   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
867       EnableLowerKernelArguments)
868     addPass(createAMDGPULowerKernelArgumentsPass());
869 
870   addPass(&AMDGPUPerfHintAnalysisID);
871 
872   TargetPassConfig::addCodeGenPrepare();
873 
874   if (EnableLoadStoreVectorizer)
875     addPass(createLoadStoreVectorizerPass());
876 
877   // LowerSwitch pass may introduce unreachable blocks that can
878   // cause unexpected behavior for subsequent passes. Placing it
879   // here seems better that these blocks would get cleaned up by
880   // UnreachableBlockElim inserted next in the pass flow.
881   addPass(createLowerSwitchPass());
882 }
883 
884 bool AMDGPUPassConfig::addPreISel() {
885   addPass(createFlattenCFGPass());
886   return false;
887 }
888 
889 bool AMDGPUPassConfig::addInstSelector() {
890   // Defer the verifier until FinalizeISel.
891   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
892   return false;
893 }
894 
895 bool AMDGPUPassConfig::addGCPasses() {
896   // Do nothing. GC is not supported.
897   return false;
898 }
899 
900 //===----------------------------------------------------------------------===//
901 // R600 Pass Setup
902 //===----------------------------------------------------------------------===//
903 
904 bool R600PassConfig::addPreISel() {
905   AMDGPUPassConfig::addPreISel();
906 
907   if (EnableR600StructurizeCFG)
908     addPass(createStructurizeCFGPass());
909   return false;
910 }
911 
912 bool R600PassConfig::addInstSelector() {
913   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
914   return false;
915 }
916 
917 void R600PassConfig::addPreRegAlloc() {
918   addPass(createR600VectorRegMerger());
919 }
920 
921 void R600PassConfig::addPreSched2() {
922   addPass(createR600EmitClauseMarkers(), false);
923   if (EnableR600IfConvert)
924     addPass(&IfConverterID, false);
925   addPass(createR600ClauseMergePass(), false);
926 }
927 
928 void R600PassConfig::addPreEmitPass() {
929   addPass(createAMDGPUCFGStructurizerPass(), false);
930   addPass(createR600ExpandSpecialInstrsPass(), false);
931   addPass(&FinalizeMachineBundlesID, false);
932   addPass(createR600Packetizer(), false);
933   addPass(createR600ControlFlowFinalizer(), false);
934 }
935 
936 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
937   return new R600PassConfig(*this, PM);
938 }
939 
940 //===----------------------------------------------------------------------===//
941 // GCN Pass Setup
942 //===----------------------------------------------------------------------===//
943 
944 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
945   MachineSchedContext *C) const {
946   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
947   if (ST.enableSIScheduler())
948     return createSIMachineScheduler(C);
949   return createGCNMaxOccupancyMachineScheduler(C);
950 }
951 
952 bool GCNPassConfig::addPreISel() {
953   AMDGPUPassConfig::addPreISel();
954 
955   addPass(createAMDGPULateCodeGenPreparePass());
956   if (EnableAtomicOptimizations) {
957     addPass(createAMDGPUAtomicOptimizerPass());
958   }
959 
960   // FIXME: We need to run a pass to propagate the attributes when calls are
961   // supported.
962 
963   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
964   // regions formed by them.
965   addPass(&AMDGPUUnifyDivergentExitNodesID);
966   if (!LateCFGStructurize) {
967     if (EnableStructurizerWorkarounds) {
968       addPass(createFixIrreduciblePass());
969       addPass(createUnifyLoopExitsPass());
970     }
971     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
972   }
973   addPass(createSinkingPass());
974   addPass(createAMDGPUAnnotateUniformValues());
975   if (!LateCFGStructurize) {
976     addPass(createSIAnnotateControlFlowPass());
977   }
978   addPass(createLCSSAPass());
979 
980   return false;
981 }
982 
983 void GCNPassConfig::addMachineSSAOptimization() {
984   TargetPassConfig::addMachineSSAOptimization();
985 
986   // We want to fold operands after PeepholeOptimizer has run (or as part of
987   // it), because it will eliminate extra copies making it easier to fold the
988   // real source operand. We want to eliminate dead instructions after, so that
989   // we see fewer uses of the copies. We then need to clean up the dead
990   // instructions leftover after the operands are folded as well.
991   //
992   // XXX - Can we get away without running DeadMachineInstructionElim again?
993   addPass(&SIFoldOperandsID);
994   if (EnableDPPCombine)
995     addPass(&GCNDPPCombineID);
996   addPass(&DeadMachineInstructionElimID);
997   addPass(&SILoadStoreOptimizerID);
998   if (EnableSDWAPeephole) {
999     addPass(&SIPeepholeSDWAID);
1000     addPass(&EarlyMachineLICMID);
1001     addPass(&MachineCSEID);
1002     addPass(&SIFoldOperandsID);
1003     addPass(&DeadMachineInstructionElimID);
1004   }
1005   addPass(createSIShrinkInstructionsPass());
1006 }
1007 
1008 bool GCNPassConfig::addILPOpts() {
1009   if (EnableEarlyIfConversion)
1010     addPass(&EarlyIfConverterID);
1011 
1012   TargetPassConfig::addILPOpts();
1013   return false;
1014 }
1015 
1016 bool GCNPassConfig::addInstSelector() {
1017   AMDGPUPassConfig::addInstSelector();
1018   addPass(&SIFixSGPRCopiesID);
1019   addPass(createSILowerI1CopiesPass());
1020   addPass(createSIAddIMGInitPass());
1021   return false;
1022 }
1023 
1024 bool GCNPassConfig::addIRTranslator() {
1025   addPass(new IRTranslator(getOptLevel()));
1026   return false;
1027 }
1028 
1029 void GCNPassConfig::addPreLegalizeMachineIR() {
1030   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1031   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1032   addPass(new Localizer());
1033 }
1034 
1035 bool GCNPassConfig::addLegalizeMachineIR() {
1036   addPass(new Legalizer());
1037   return false;
1038 }
1039 
1040 void GCNPassConfig::addPreRegBankSelect() {
1041   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1042   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1043 }
1044 
1045 bool GCNPassConfig::addRegBankSelect() {
1046   addPass(new RegBankSelect());
1047   return false;
1048 }
1049 
1050 bool GCNPassConfig::addGlobalInstructionSelect() {
1051   addPass(new InstructionSelect());
1052   return false;
1053 }
1054 
1055 void GCNPassConfig::addPreRegAlloc() {
1056   if (LateCFGStructurize) {
1057     addPass(createAMDGPUMachineCFGStructurizerPass());
1058   }
1059 }
1060 
1061 void GCNPassConfig::addFastRegAlloc() {
1062   // FIXME: We have to disable the verifier here because of PHIElimination +
1063   // TwoAddressInstructions disabling it.
1064 
1065   // This must be run immediately after phi elimination and before
1066   // TwoAddressInstructions, otherwise the processing of the tied operand of
1067   // SI_ELSE will introduce a copy of the tied operand source after the else.
1068   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1069 
1070   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1071   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1072 
1073   TargetPassConfig::addFastRegAlloc();
1074 }
1075 
1076 void GCNPassConfig::addOptimizedRegAlloc() {
1077   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1078   // instructions that cause scheduling barriers.
1079   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1080   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1081 
1082   if (OptExecMaskPreRA)
1083     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1084   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1085 
1086   // This must be run immediately after phi elimination and before
1087   // TwoAddressInstructions, otherwise the processing of the tied operand of
1088   // SI_ELSE will introduce a copy of the tied operand source after the else.
1089   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1090 
1091   if (EnableDCEInRA)
1092     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1093 
1094   TargetPassConfig::addOptimizedRegAlloc();
1095 }
1096 
1097 bool GCNPassConfig::addPreRewrite() {
1098   if (EnableRegReassign) {
1099     addPass(&GCNNSAReassignID);
1100     addPass(&GCNRegBankReassignID);
1101   }
1102   return true;
1103 }
1104 
1105 void GCNPassConfig::addPostRegAlloc() {
1106   addPass(&SIFixVGPRCopiesID);
1107   if (getOptLevel() > CodeGenOpt::None)
1108     addPass(&SIOptimizeExecMaskingID);
1109   TargetPassConfig::addPostRegAlloc();
1110 
1111   // Equivalent of PEI for SGPRs.
1112   addPass(&SILowerSGPRSpillsID);
1113 }
1114 
1115 void GCNPassConfig::addPreSched2() {
1116   addPass(&SIPostRABundlerID);
1117 }
1118 
1119 void GCNPassConfig::addPreEmitPass() {
1120   addPass(createSIMemoryLegalizerPass());
1121   addPass(createSIInsertWaitcntsPass());
1122   addPass(createSIShrinkInstructionsPass());
1123   addPass(createSIModeRegisterPass());
1124 
1125   if (getOptLevel() > CodeGenOpt::None)
1126     addPass(&SIInsertHardClausesID);
1127 
1128   addPass(&SIRemoveShortExecBranchesID);
1129   addPass(&SIInsertSkipsPassID);
1130   addPass(&SIPreEmitPeepholeID);
1131   // The hazard recognizer that runs as part of the post-ra scheduler does not
1132   // guarantee to be able handle all hazards correctly. This is because if there
1133   // are multiple scheduling regions in a basic block, the regions are scheduled
1134   // bottom up, so when we begin to schedule a region we don't know what
1135   // instructions were emitted directly before it.
1136   //
1137   // Here we add a stand-alone hazard recognizer pass which can handle all
1138   // cases.
1139   addPass(&PostRAHazardRecognizerID);
1140   addPass(&BranchRelaxationPassID);
1141 }
1142 
1143 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1144   return new GCNPassConfig(*this, PM);
1145 }
1146 
1147 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1148   return new yaml::SIMachineFunctionInfo();
1149 }
1150 
1151 yaml::MachineFunctionInfo *
1152 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1153   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1154   return new yaml::SIMachineFunctionInfo(*MFI,
1155                                          *MF.getSubtarget().getRegisterInfo());
1156 }
1157 
1158 bool GCNTargetMachine::parseMachineFunctionInfo(
1159     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1160     SMDiagnostic &Error, SMRange &SourceRange) const {
1161   const yaml::SIMachineFunctionInfo &YamlMFI =
1162       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1163   MachineFunction &MF = PFS.MF;
1164   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1165 
1166   MFI->initializeBaseYamlFields(YamlMFI);
1167 
1168   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1169     Register TempReg;
1170     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1171       SourceRange = RegName.SourceRange;
1172       return true;
1173     }
1174     RegVal = TempReg;
1175 
1176     return false;
1177   };
1178 
1179   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1180     // Create a diagnostic for a the register string literal.
1181     const MemoryBuffer &Buffer =
1182         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1183     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1184                          RegName.Value.size(), SourceMgr::DK_Error,
1185                          "incorrect register class for field", RegName.Value,
1186                          None, None);
1187     SourceRange = RegName.SourceRange;
1188     return true;
1189   };
1190 
1191   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1192       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1193       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1194     return true;
1195 
1196   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1197       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1198     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1199   }
1200 
1201   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1202       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1203     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1204   }
1205 
1206   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1207       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1208     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1209   }
1210 
1211   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1212                                    const TargetRegisterClass &RC,
1213                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1214                                    unsigned SystemSGPRs) {
1215     // Skip parsing if it's not present.
1216     if (!A)
1217       return false;
1218 
1219     if (A->IsRegister) {
1220       Register Reg;
1221       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1222         SourceRange = A->RegisterName.SourceRange;
1223         return true;
1224       }
1225       if (!RC.contains(Reg))
1226         return diagnoseRegisterClass(A->RegisterName);
1227       Arg = ArgDescriptor::createRegister(Reg);
1228     } else
1229       Arg = ArgDescriptor::createStack(A->StackOffset);
1230     // Check and apply the optional mask.
1231     if (A->Mask)
1232       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1233 
1234     MFI->NumUserSGPRs += UserSGPRs;
1235     MFI->NumSystemSGPRs += SystemSGPRs;
1236     return false;
1237   };
1238 
1239   if (YamlMFI.ArgInfo &&
1240       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1241                              AMDGPU::SGPR_128RegClass,
1242                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1243        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1244                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1245                              2, 0) ||
1246        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1247                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1248        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1249                              AMDGPU::SReg_64RegClass,
1250                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1251        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1252                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1253                              2, 0) ||
1254        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1255                              AMDGPU::SReg_64RegClass,
1256                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1257        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1258                              AMDGPU::SGPR_32RegClass,
1259                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1260        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1261                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1262                              0, 1) ||
1263        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1264                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1265                              0, 1) ||
1266        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1267                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1268                              0, 1) ||
1269        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1270                              AMDGPU::SGPR_32RegClass,
1271                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1272        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1273                              AMDGPU::SGPR_32RegClass,
1274                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1275        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1276                              AMDGPU::SReg_64RegClass,
1277                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1278        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1279                              AMDGPU::SReg_64RegClass,
1280                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1281        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1282                              AMDGPU::VGPR_32RegClass,
1283                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1284        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1285                              AMDGPU::VGPR_32RegClass,
1286                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1287        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1288                              AMDGPU::VGPR_32RegClass,
1289                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1290     return true;
1291 
1292   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1293   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1294   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1295   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1296   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1297   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1298 
1299   return false;
1300 }
1301