1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110   cl::desc("Enable AMDGPU Alias Analysis"),
111   cl::init(true));
112 
113 // Option to enable new waitcnt insertion pass.
114 static cl::opt<bool> EnableSIInsertWaitcntsPass(
115   "enable-si-insert-waitcnts",
116   cl::desc("Use new waitcnt insertion pass"),
117   cl::init(true));
118 
119 // Option to run late CFG structurizer
120 static cl::opt<bool> LateCFGStructurize(
121   "amdgpu-late-structurize",
122   cl::desc("Enable late CFG structurization"),
123   cl::init(false),
124   cl::Hidden);
125 
126 extern "C" void LLVMInitializeAMDGPUTarget() {
127   // Register the target
128   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
129   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
130 
131   PassRegistry *PR = PassRegistry::getPassRegistry();
132   initializeSILowerI1CopiesPass(*PR);
133   initializeSIFixSGPRCopiesPass(*PR);
134   initializeSIFixVGPRCopiesPass(*PR);
135   initializeSIFoldOperandsPass(*PR);
136   initializeSIPeepholeSDWAPass(*PR);
137   initializeSIShrinkInstructionsPass(*PR);
138   initializeSIFixControlFlowLiveIntervalsPass(*PR);
139   initializeSILoadStoreOptimizerPass(*PR);
140   initializeAMDGPUAlwaysInlinePass(*PR);
141   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
142   initializeAMDGPUAnnotateUniformValuesPass(*PR);
143   initializeAMDGPULowerIntrinsicsPass(*PR);
144   initializeAMDGPUPromoteAllocaPass(*PR);
145   initializeAMDGPUCodeGenPreparePass(*PR);
146   initializeAMDGPURewriteOutArgumentsPass(*PR);
147   initializeAMDGPUUnifyMetadataPass(*PR);
148   initializeSIAnnotateControlFlowPass(*PR);
149   initializeSIInsertWaitsPass(*PR);
150   initializeSIInsertWaitcntsPass(*PR);
151   initializeSIWholeQuadModePass(*PR);
152   initializeSILowerControlFlowPass(*PR);
153   initializeSIInsertSkipsPass(*PR);
154   initializeSIMemoryLegalizerPass(*PR);
155   initializeSIDebuggerInsertNopsPass(*PR);
156   initializeSIOptimizeExecMaskingPass(*PR);
157   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
158   initializeAMDGPUAAWrapperPassPass(*PR);
159 }
160 
161 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
162   return llvm::make_unique<AMDGPUTargetObjectFile>();
163 }
164 
165 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
166   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
167 }
168 
169 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
170   return new SIScheduleDAGMI(C);
171 }
172 
173 static ScheduleDAGInstrs *
174 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
175   ScheduleDAGMILive *DAG =
176     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
177   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
178   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
179   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
180   return DAG;
181 }
182 
183 static ScheduleDAGInstrs *
184 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
185   auto DAG = new GCNIterativeScheduler(C,
186     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
187   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
188   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
189   return DAG;
190 }
191 
192 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
193   return new GCNIterativeScheduler(C,
194     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
195 }
196 
197 static MachineSchedRegistry
198 R600SchedRegistry("r600", "Run R600's custom scheduler",
199                    createR600MachineScheduler);
200 
201 static MachineSchedRegistry
202 SISchedRegistry("si", "Run SI's custom scheduler",
203                 createSIMachineScheduler);
204 
205 static MachineSchedRegistry
206 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
207                              "Run GCN scheduler to maximize occupancy",
208                              createGCNMaxOccupancyMachineScheduler);
209 
210 static MachineSchedRegistry
211 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
212   "Run GCN scheduler to maximize occupancy (experimental)",
213   createIterativeGCNMaxOccupancyMachineScheduler);
214 
215 static MachineSchedRegistry
216 GCNMinRegSchedRegistry("gcn-minreg",
217   "Run GCN iterative scheduler for minimal register usage (experimental)",
218   createMinRegScheduler);
219 
220 static StringRef computeDataLayout(const Triple &TT) {
221   if (TT.getArch() == Triple::r600) {
222     // 32-bit pointers.
223     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
224             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
225   }
226 
227   // 32-bit private, local, and region pointers. 64-bit global, constant and
228   // flat.
229   if (TT.getEnvironmentName() == "amdgiz" ||
230       TT.getEnvironmentName() == "amdgizcl")
231     return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
232          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
233          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
234   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
235       "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
236       "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
237 }
238 
239 LLVM_READNONE
240 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
241   if (!GPU.empty())
242     return GPU;
243 
244   // HSA only supports CI+, so change the default GPU to a CI for HSA.
245   if (TT.getArch() == Triple::amdgcn)
246     return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
247 
248   return "r600";
249 }
250 
251 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
252   // The AMDGPU toolchain only supports generating shared objects, so we
253   // must always use PIC.
254   return Reloc::PIC_;
255 }
256 
257 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
258                                          StringRef CPU, StringRef FS,
259                                          TargetOptions Options,
260                                          Optional<Reloc::Model> RM,
261                                          CodeModel::Model CM,
262                                          CodeGenOpt::Level OptLevel)
263   : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
264                       FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
265     TLOF(createTLOF(getTargetTriple())) {
266   AS = AMDGPU::getAMDGPUAS(TT);
267   initAsmInfo();
268 }
269 
270 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
271 
272 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
273   Attribute GPUAttr = F.getFnAttribute("target-cpu");
274   return GPUAttr.hasAttribute(Attribute::None) ?
275     getTargetCPU() : GPUAttr.getValueAsString();
276 }
277 
278 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
279   Attribute FSAttr = F.getFnAttribute("target-features");
280 
281   return FSAttr.hasAttribute(Attribute::None) ?
282     getTargetFeatureString() :
283     FSAttr.getValueAsString();
284 }
285 
286 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
287   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
288       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
289         AAR.addAAResult(WrapperPass->getResult());
290       });
291 }
292 
293 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
294   Builder.DivergentTarget = true;
295 
296   bool Internalize = InternalizeSymbols &&
297                      (getOptLevel() > CodeGenOpt::None) &&
298                      (getTargetTriple().getArch() == Triple::amdgcn);
299   bool EarlyInline = EarlyInlineAll &&
300                      (getOptLevel() > CodeGenOpt::None);
301   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && getOptLevel() > CodeGenOpt::None;
302 
303   Builder.addExtension(
304     PassManagerBuilder::EP_ModuleOptimizerEarly,
305     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
306                                          legacy::PassManagerBase &PM) {
307       if (AMDGPUAA) {
308         PM.add(createAMDGPUAAWrapperPass());
309         PM.add(createAMDGPUExternalAAWrapperPass());
310       }
311       PM.add(createAMDGPUUnifyMetadataPass());
312       if (Internalize) {
313         PM.add(createInternalizePass([=](const GlobalValue &GV) -> bool {
314           if (const Function *F = dyn_cast<Function>(&GV)) {
315             if (F->isDeclaration())
316                 return true;
317             switch (F->getCallingConv()) {
318             default:
319               return false;
320             case CallingConv::AMDGPU_VS:
321             case CallingConv::AMDGPU_HS:
322             case CallingConv::AMDGPU_GS:
323             case CallingConv::AMDGPU_PS:
324             case CallingConv::AMDGPU_CS:
325             case CallingConv::AMDGPU_KERNEL:
326             case CallingConv::SPIR_KERNEL:
327               return true;
328             }
329           }
330           return !GV.use_empty();
331         }));
332         PM.add(createGlobalDCEPass());
333       }
334       if (EarlyInline)
335         PM.add(createAMDGPUAlwaysInlinePass(false));
336   });
337 
338   Builder.addExtension(
339     PassManagerBuilder::EP_EarlyAsPossible,
340     [AMDGPUAA](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
341       if (AMDGPUAA) {
342         PM.add(createAMDGPUAAWrapperPass());
343         PM.add(createAMDGPUExternalAAWrapperPass());
344       }
345   });
346 
347   Builder.addExtension(
348     PassManagerBuilder::EP_CGSCCOptimizerLate,
349     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
350       // Add infer address spaces pass to the opt pipeline after inlining
351       // but before SROA to increase SROA opportunities.
352       PM.add(createInferAddressSpacesPass());
353   });
354 }
355 
356 //===----------------------------------------------------------------------===//
357 // R600 Target Machine (R600 -> Cayman)
358 //===----------------------------------------------------------------------===//
359 
360 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
361                                      StringRef CPU, StringRef FS,
362                                      TargetOptions Options,
363                                      Optional<Reloc::Model> RM,
364                                      CodeModel::Model CM, CodeGenOpt::Level OL)
365   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
366   setRequiresStructuredCFG(true);
367 }
368 
369 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
370   const Function &F) const {
371   StringRef GPU = getGPUName(F);
372   StringRef FS = getFeatureString(F);
373 
374   SmallString<128> SubtargetKey(GPU);
375   SubtargetKey.append(FS);
376 
377   auto &I = SubtargetMap[SubtargetKey];
378   if (!I) {
379     // This needs to be done before we create a new subtarget since any
380     // creation will depend on the TM and the code generation flags on the
381     // function that reside in TargetOptions.
382     resetTargetOptions(F);
383     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
384   }
385 
386   return I.get();
387 }
388 
389 //===----------------------------------------------------------------------===//
390 // GCN Target Machine (SI+)
391 //===----------------------------------------------------------------------===//
392 
393 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
394                                    StringRef CPU, StringRef FS,
395                                    TargetOptions Options,
396                                    Optional<Reloc::Model> RM,
397                                    CodeModel::Model CM, CodeGenOpt::Level OL)
398   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
399 
400 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
401   StringRef GPU = getGPUName(F);
402   StringRef FS = getFeatureString(F);
403 
404   SmallString<128> SubtargetKey(GPU);
405   SubtargetKey.append(FS);
406 
407   auto &I = SubtargetMap[SubtargetKey];
408   if (!I) {
409     // This needs to be done before we create a new subtarget since any
410     // creation will depend on the TM and the code generation flags on the
411     // function that reside in TargetOptions.
412     resetTargetOptions(F);
413     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
414   }
415 
416   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
417 
418   return I.get();
419 }
420 
421 //===----------------------------------------------------------------------===//
422 // AMDGPU Pass Setup
423 //===----------------------------------------------------------------------===//
424 
425 namespace {
426 
427 class AMDGPUPassConfig : public TargetPassConfig {
428 public:
429   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
430     : TargetPassConfig(TM, PM) {
431     // Exceptions and StackMaps are not supported, so these passes will never do
432     // anything.
433     disablePass(&StackMapLivenessID);
434     disablePass(&FuncletLayoutID);
435   }
436 
437   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
438     return getTM<AMDGPUTargetMachine>();
439   }
440 
441   ScheduleDAGInstrs *
442   createMachineScheduler(MachineSchedContext *C) const override {
443     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
444     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
445     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
446     return DAG;
447   }
448 
449   void addEarlyCSEOrGVNPass();
450   void addStraightLineScalarOptimizationPasses();
451   void addIRPasses() override;
452   void addCodeGenPrepare() override;
453   bool addPreISel() override;
454   bool addInstSelector() override;
455   bool addGCPasses() override;
456 };
457 
458 class R600PassConfig final : public AMDGPUPassConfig {
459 public:
460   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
461     : AMDGPUPassConfig(TM, PM) {}
462 
463   ScheduleDAGInstrs *createMachineScheduler(
464     MachineSchedContext *C) const override {
465     return createR600MachineScheduler(C);
466   }
467 
468   bool addPreISel() override;
469   void addPreRegAlloc() override;
470   void addPreSched2() override;
471   void addPreEmitPass() override;
472 };
473 
474 class GCNPassConfig final : public AMDGPUPassConfig {
475 public:
476   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
477     : AMDGPUPassConfig(TM, PM) {}
478 
479   GCNTargetMachine &getGCNTargetMachine() const {
480     return getTM<GCNTargetMachine>();
481   }
482 
483   ScheduleDAGInstrs *
484   createMachineScheduler(MachineSchedContext *C) const override;
485 
486   bool addPreISel() override;
487   void addMachineSSAOptimization() override;
488   bool addILPOpts() override;
489   bool addInstSelector() override;
490 #ifdef LLVM_BUILD_GLOBAL_ISEL
491   bool addIRTranslator() override;
492   bool addLegalizeMachineIR() override;
493   bool addRegBankSelect() override;
494   bool addGlobalInstructionSelect() override;
495 #endif
496   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
497   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
498   void addPreRegAlloc() override;
499   void addPostRegAlloc() override;
500   void addPreSched2() override;
501   void addPreEmitPass() override;
502 };
503 
504 } // end anonymous namespace
505 
506 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
507   return TargetIRAnalysis([this](const Function &F) {
508     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
509   });
510 }
511 
512 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
513   if (getOptLevel() == CodeGenOpt::Aggressive)
514     addPass(createGVNPass());
515   else
516     addPass(createEarlyCSEPass());
517 }
518 
519 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
520   addPass(createSeparateConstOffsetFromGEPPass());
521   addPass(createSpeculativeExecutionPass());
522   // ReassociateGEPs exposes more opportunites for SLSR. See
523   // the example in reassociate-geps-and-slsr.ll.
524   addPass(createStraightLineStrengthReducePass());
525   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
526   // EarlyCSE can reuse.
527   addEarlyCSEOrGVNPass();
528   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
529   addPass(createNaryReassociatePass());
530   // NaryReassociate on GEPs creates redundant common expressions, so run
531   // EarlyCSE after it.
532   addPass(createEarlyCSEPass());
533 }
534 
535 void AMDGPUPassConfig::addIRPasses() {
536   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
537 
538   // There is no reason to run these.
539   disablePass(&StackMapLivenessID);
540   disablePass(&FuncletLayoutID);
541   disablePass(&PatchableFunctionID);
542 
543   addPass(createAMDGPULowerIntrinsicsPass());
544 
545   // Function calls are not supported, so make sure we inline everything.
546   addPass(createAMDGPUAlwaysInlinePass());
547   addPass(createAlwaysInlinerLegacyPass());
548   // We need to add the barrier noop pass, otherwise adding the function
549   // inlining pass will cause all of the PassConfigs passes to be run
550   // one function at a time, which means if we have a nodule with two
551   // functions, then we will generate code for the first function
552   // without ever running any passes on the second.
553   addPass(createBarrierNoopPass());
554 
555   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
556     // TODO: May want to move later or split into an early and late one.
557 
558     addPass(createAMDGPUCodeGenPreparePass());
559   }
560 
561   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
562   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
563 
564   if (TM.getOptLevel() > CodeGenOpt::None) {
565     addPass(createInferAddressSpacesPass());
566     addPass(createAMDGPUPromoteAlloca());
567 
568     if (EnableSROA)
569       addPass(createSROAPass());
570 
571     addStraightLineScalarOptimizationPasses();
572 
573     if (EnableAMDGPUAliasAnalysis) {
574       addPass(createAMDGPUAAWrapperPass());
575       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
576                                              AAResults &AAR) {
577         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
578           AAR.addAAResult(WrapperPass->getResult());
579         }));
580     }
581   }
582 
583   TargetPassConfig::addIRPasses();
584 
585   // EarlyCSE is not always strong enough to clean up what LSR produces. For
586   // example, GVN can combine
587   //
588   //   %0 = add %a, %b
589   //   %1 = add %b, %a
590   //
591   // and
592   //
593   //   %0 = shl nsw %a, 2
594   //   %1 = shl %a, 2
595   //
596   // but EarlyCSE can do neither of them.
597   if (getOptLevel() != CodeGenOpt::None)
598     addEarlyCSEOrGVNPass();
599 }
600 
601 void AMDGPUPassConfig::addCodeGenPrepare() {
602   TargetPassConfig::addCodeGenPrepare();
603 
604   if (EnableLoadStoreVectorizer)
605     addPass(createLoadStoreVectorizerPass());
606 }
607 
608 bool AMDGPUPassConfig::addPreISel() {
609   addPass(createFlattenCFGPass());
610   return false;
611 }
612 
613 bool AMDGPUPassConfig::addInstSelector() {
614   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));
615   return false;
616 }
617 
618 bool AMDGPUPassConfig::addGCPasses() {
619   // Do nothing. GC is not supported.
620   return false;
621 }
622 
623 //===----------------------------------------------------------------------===//
624 // R600 Pass Setup
625 //===----------------------------------------------------------------------===//
626 
627 bool R600PassConfig::addPreISel() {
628   AMDGPUPassConfig::addPreISel();
629 
630   if (EnableR600StructurizeCFG)
631     addPass(createStructurizeCFGPass());
632   return false;
633 }
634 
635 void R600PassConfig::addPreRegAlloc() {
636   addPass(createR600VectorRegMerger());
637 }
638 
639 void R600PassConfig::addPreSched2() {
640   addPass(createR600EmitClauseMarkers(), false);
641   if (EnableR600IfConvert)
642     addPass(&IfConverterID, false);
643   addPass(createR600ClauseMergePass(), false);
644 }
645 
646 void R600PassConfig::addPreEmitPass() {
647   addPass(createAMDGPUCFGStructurizerPass(), false);
648   addPass(createR600ExpandSpecialInstrsPass(), false);
649   addPass(&FinalizeMachineBundlesID, false);
650   addPass(createR600Packetizer(), false);
651   addPass(createR600ControlFlowFinalizer(), false);
652 }
653 
654 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
655   return new R600PassConfig(*this, PM);
656 }
657 
658 //===----------------------------------------------------------------------===//
659 // GCN Pass Setup
660 //===----------------------------------------------------------------------===//
661 
662 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
663   MachineSchedContext *C) const {
664   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
665   if (ST.enableSIScheduler())
666     return createSIMachineScheduler(C);
667   return createGCNMaxOccupancyMachineScheduler(C);
668 }
669 
670 bool GCNPassConfig::addPreISel() {
671   AMDGPUPassConfig::addPreISel();
672 
673   // FIXME: We need to run a pass to propagate the attributes when calls are
674   // supported.
675   addPass(createAMDGPUAnnotateKernelFeaturesPass());
676 
677   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
678   // regions formed by them.
679   addPass(&AMDGPUUnifyDivergentExitNodesID);
680   if (!LateCFGStructurize) {
681     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
682   }
683   addPass(createSinkingPass());
684   addPass(createAMDGPUAnnotateUniformValues());
685   if (!LateCFGStructurize) {
686     addPass(createSIAnnotateControlFlowPass());
687   }
688 
689   return false;
690 }
691 
692 void GCNPassConfig::addMachineSSAOptimization() {
693   TargetPassConfig::addMachineSSAOptimization();
694 
695   // We want to fold operands after PeepholeOptimizer has run (or as part of
696   // it), because it will eliminate extra copies making it easier to fold the
697   // real source operand. We want to eliminate dead instructions after, so that
698   // we see fewer uses of the copies. We then need to clean up the dead
699   // instructions leftover after the operands are folded as well.
700   //
701   // XXX - Can we get away without running DeadMachineInstructionElim again?
702   addPass(&SIFoldOperandsID);
703   addPass(&DeadMachineInstructionElimID);
704   addPass(&SILoadStoreOptimizerID);
705   if (EnableSDWAPeephole) {
706     addPass(&SIPeepholeSDWAID);
707     addPass(&MachineLICMID);
708     addPass(&MachineCSEID);
709     addPass(&SIFoldOperandsID);
710     addPass(&DeadMachineInstructionElimID);
711   }
712   addPass(createSIShrinkInstructionsPass());
713 }
714 
715 bool GCNPassConfig::addILPOpts() {
716   if (EnableEarlyIfConversion)
717     addPass(&EarlyIfConverterID);
718 
719   TargetPassConfig::addILPOpts();
720   return false;
721 }
722 
723 bool GCNPassConfig::addInstSelector() {
724   AMDGPUPassConfig::addInstSelector();
725   addPass(createSILowerI1CopiesPass());
726   addPass(&SIFixSGPRCopiesID);
727   return false;
728 }
729 
730 #ifdef LLVM_BUILD_GLOBAL_ISEL
731 bool GCNPassConfig::addIRTranslator() {
732   addPass(new IRTranslator());
733   return false;
734 }
735 
736 bool GCNPassConfig::addLegalizeMachineIR() {
737   addPass(new Legalizer());
738   return false;
739 }
740 
741 bool GCNPassConfig::addRegBankSelect() {
742   addPass(new RegBankSelect());
743   return false;
744 }
745 
746 bool GCNPassConfig::addGlobalInstructionSelect() {
747   addPass(new InstructionSelect());
748   return false;
749 }
750 
751 #endif
752 
753 void GCNPassConfig::addPreRegAlloc() {
754   if (LateCFGStructurize) {
755     addPass(createAMDGPUMachineCFGStructurizerPass());
756   }
757   addPass(createSIWholeQuadModePass());
758 }
759 
760 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
761   // FIXME: We have to disable the verifier here because of PHIElimination +
762   // TwoAddressInstructions disabling it.
763 
764   // This must be run immediately after phi elimination and before
765   // TwoAddressInstructions, otherwise the processing of the tied operand of
766   // SI_ELSE will introduce a copy of the tied operand source after the else.
767   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
768 
769   TargetPassConfig::addFastRegAlloc(RegAllocPass);
770 }
771 
772 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
773   // This needs to be run directly before register allocation because earlier
774   // passes might recompute live intervals.
775   insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
776 
777   // This must be run immediately after phi elimination and before
778   // TwoAddressInstructions, otherwise the processing of the tied operand of
779   // SI_ELSE will introduce a copy of the tied operand source after the else.
780   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
781 
782   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
783 }
784 
785 void GCNPassConfig::addPostRegAlloc() {
786   addPass(&SIFixVGPRCopiesID);
787   addPass(&SIOptimizeExecMaskingID);
788   TargetPassConfig::addPostRegAlloc();
789 }
790 
791 void GCNPassConfig::addPreSched2() {
792 }
793 
794 void GCNPassConfig::addPreEmitPass() {
795   // The hazard recognizer that runs as part of the post-ra scheduler does not
796   // guarantee to be able handle all hazards correctly. This is because if there
797   // are multiple scheduling regions in a basic block, the regions are scheduled
798   // bottom up, so when we begin to schedule a region we don't know what
799   // instructions were emitted directly before it.
800   //
801   // Here we add a stand-alone hazard recognizer pass which can handle all
802   // cases.
803   addPass(&PostRAHazardRecognizerID);
804 
805   if (EnableSIInsertWaitcntsPass)
806     addPass(createSIInsertWaitcntsPass());
807   else
808     addPass(createSIInsertWaitsPass());
809   addPass(createSIShrinkInstructionsPass());
810   addPass(&SIInsertSkipsPassID);
811   addPass(createSIMemoryLegalizerPass());
812   addPass(createSIDebuggerInsertNopsPass());
813   addPass(&BranchRelaxationPassID);
814 }
815 
816 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
817   return new GCNPassConfig(*this, PM);
818 }
819 
820