1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for SI+ GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUIGroupLP.h"
20 #include "AMDGPUMacroFusion.h"
21 #include "AMDGPUTargetObjectFile.h"
22 #include "AMDGPUTargetTransformInfo.h"
23 #include "GCNIterativeScheduler.h"
24 #include "GCNSchedStrategy.h"
25 #include "R600.h"
26 #include "R600TargetMachine.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIMachineScheduler.h"
29 #include "TargetInfo/AMDGPUTargetInfo.h"
30 #include "llvm/Analysis/CGSCCPassManager.h"
31 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
35 #include "llvm/CodeGen/GlobalISel/Localizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MIRParser/MIParser.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/RegAllocRegistry.h"
40 #include "llvm/CodeGen/TargetPassConfig.h"
41 #include "llvm/IR/IntrinsicsAMDGPU.h"
42 #include "llvm/IR/LegacyPassManager.h"
43 #include "llvm/IR/PassManager.h"
44 #include "llvm/IR/PatternMatch.h"
45 #include "llvm/InitializePasses.h"
46 #include "llvm/MC/TargetRegistry.h"
47 #include "llvm/Passes/PassBuilder.h"
48 #include "llvm/Transforms/IPO.h"
49 #include "llvm/Transforms/IPO/AlwaysInliner.h"
50 #include "llvm/Transforms/IPO/GlobalDCE.h"
51 #include "llvm/Transforms/IPO/Internalize.h"
52 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
53 #include "llvm/Transforms/Scalar.h"
54 #include "llvm/Transforms/Scalar/GVN.h"
55 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
56 #include "llvm/Transforms/Utils.h"
57 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
58 #include "llvm/Transforms/Vectorize.h"
59 
60 using namespace llvm;
61 using namespace llvm::PatternMatch;
62 
63 namespace {
64 class SGPRRegisterRegAlloc : public RegisterRegAllocBase<SGPRRegisterRegAlloc> {
65 public:
66   SGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
67     : RegisterRegAllocBase(N, D, C) {}
68 };
69 
70 class VGPRRegisterRegAlloc : public RegisterRegAllocBase<VGPRRegisterRegAlloc> {
71 public:
72   VGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
73     : RegisterRegAllocBase(N, D, C) {}
74 };
75 
76 static bool onlyAllocateSGPRs(const TargetRegisterInfo &TRI,
77                               const TargetRegisterClass &RC) {
78   return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
79 }
80 
81 static bool onlyAllocateVGPRs(const TargetRegisterInfo &TRI,
82                               const TargetRegisterClass &RC) {
83   return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
84 }
85 
86 
87 /// -{sgpr|vgpr}-regalloc=... command line option.
88 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
89 
90 /// A dummy default pass factory indicates whether the register allocator is
91 /// overridden on the command line.
92 static llvm::once_flag InitializeDefaultSGPRRegisterAllocatorFlag;
93 static llvm::once_flag InitializeDefaultVGPRRegisterAllocatorFlag;
94 
95 static SGPRRegisterRegAlloc
96 defaultSGPRRegAlloc("default",
97                     "pick SGPR register allocator based on -O option",
98                     useDefaultRegisterAllocator);
99 
100 static cl::opt<SGPRRegisterRegAlloc::FunctionPassCtor, false,
101                RegisterPassParser<SGPRRegisterRegAlloc>>
102 SGPRRegAlloc("sgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
103              cl::desc("Register allocator to use for SGPRs"));
104 
105 static cl::opt<VGPRRegisterRegAlloc::FunctionPassCtor, false,
106                RegisterPassParser<VGPRRegisterRegAlloc>>
107 VGPRRegAlloc("vgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
108              cl::desc("Register allocator to use for VGPRs"));
109 
110 
111 static void initializeDefaultSGPRRegisterAllocatorOnce() {
112   RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
113 
114   if (!Ctor) {
115     Ctor = SGPRRegAlloc;
116     SGPRRegisterRegAlloc::setDefault(SGPRRegAlloc);
117   }
118 }
119 
120 static void initializeDefaultVGPRRegisterAllocatorOnce() {
121   RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
122 
123   if (!Ctor) {
124     Ctor = VGPRRegAlloc;
125     VGPRRegisterRegAlloc::setDefault(VGPRRegAlloc);
126   }
127 }
128 
129 static FunctionPass *createBasicSGPRRegisterAllocator() {
130   return createBasicRegisterAllocator(onlyAllocateSGPRs);
131 }
132 
133 static FunctionPass *createGreedySGPRRegisterAllocator() {
134   return createGreedyRegisterAllocator(onlyAllocateSGPRs);
135 }
136 
137 static FunctionPass *createFastSGPRRegisterAllocator() {
138   return createFastRegisterAllocator(onlyAllocateSGPRs, false);
139 }
140 
141 static FunctionPass *createBasicVGPRRegisterAllocator() {
142   return createBasicRegisterAllocator(onlyAllocateVGPRs);
143 }
144 
145 static FunctionPass *createGreedyVGPRRegisterAllocator() {
146   return createGreedyRegisterAllocator(onlyAllocateVGPRs);
147 }
148 
149 static FunctionPass *createFastVGPRRegisterAllocator() {
150   return createFastRegisterAllocator(onlyAllocateVGPRs, true);
151 }
152 
153 static SGPRRegisterRegAlloc basicRegAllocSGPR(
154   "basic", "basic register allocator", createBasicSGPRRegisterAllocator);
155 static SGPRRegisterRegAlloc greedyRegAllocSGPR(
156   "greedy", "greedy register allocator", createGreedySGPRRegisterAllocator);
157 
158 static SGPRRegisterRegAlloc fastRegAllocSGPR(
159   "fast", "fast register allocator", createFastSGPRRegisterAllocator);
160 
161 
162 static VGPRRegisterRegAlloc basicRegAllocVGPR(
163   "basic", "basic register allocator", createBasicVGPRRegisterAllocator);
164 static VGPRRegisterRegAlloc greedyRegAllocVGPR(
165   "greedy", "greedy register allocator", createGreedyVGPRRegisterAllocator);
166 
167 static VGPRRegisterRegAlloc fastRegAllocVGPR(
168   "fast", "fast register allocator", createFastVGPRRegisterAllocator);
169 }
170 
171 static cl::opt<bool> EnableSROA(
172   "amdgpu-sroa",
173   cl::desc("Run SROA after promote alloca pass"),
174   cl::ReallyHidden,
175   cl::init(true));
176 
177 static cl::opt<bool>
178 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
179                         cl::desc("Run early if-conversion"),
180                         cl::init(false));
181 
182 static cl::opt<bool>
183 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
184             cl::desc("Run pre-RA exec mask optimizations"),
185             cl::init(true));
186 
187 // Option to disable vectorizer for tests.
188 static cl::opt<bool> EnableLoadStoreVectorizer(
189   "amdgpu-load-store-vectorizer",
190   cl::desc("Enable load store vectorizer"),
191   cl::init(true),
192   cl::Hidden);
193 
194 // Option to control global loads scalarization
195 static cl::opt<bool> ScalarizeGlobal(
196   "amdgpu-scalarize-global-loads",
197   cl::desc("Enable global load scalarization"),
198   cl::init(true),
199   cl::Hidden);
200 
201 // Option to run internalize pass.
202 static cl::opt<bool> InternalizeSymbols(
203   "amdgpu-internalize-symbols",
204   cl::desc("Enable elimination of non-kernel functions and unused globals"),
205   cl::init(false),
206   cl::Hidden);
207 
208 // Option to inline all early.
209 static cl::opt<bool> EarlyInlineAll(
210   "amdgpu-early-inline-all",
211   cl::desc("Inline all functions early"),
212   cl::init(false),
213   cl::Hidden);
214 
215 static cl::opt<bool> EnableSDWAPeephole(
216   "amdgpu-sdwa-peephole",
217   cl::desc("Enable SDWA peepholer"),
218   cl::init(true));
219 
220 static cl::opt<bool> EnableDPPCombine(
221   "amdgpu-dpp-combine",
222   cl::desc("Enable DPP combiner"),
223   cl::init(true));
224 
225 // Enable address space based alias analysis
226 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
227   cl::desc("Enable AMDGPU Alias Analysis"),
228   cl::init(true));
229 
230 // Option to run late CFG structurizer
231 static cl::opt<bool, true> LateCFGStructurize(
232   "amdgpu-late-structurize",
233   cl::desc("Enable late CFG structurization"),
234   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
235   cl::Hidden);
236 
237 // Enable lib calls simplifications
238 static cl::opt<bool> EnableLibCallSimplify(
239   "amdgpu-simplify-libcall",
240   cl::desc("Enable amdgpu library simplifications"),
241   cl::init(true),
242   cl::Hidden);
243 
244 static cl::opt<bool> EnableLowerKernelArguments(
245   "amdgpu-ir-lower-kernel-arguments",
246   cl::desc("Lower kernel argument loads in IR pass"),
247   cl::init(true),
248   cl::Hidden);
249 
250 static cl::opt<bool> EnableRegReassign(
251   "amdgpu-reassign-regs",
252   cl::desc("Enable register reassign optimizations on gfx10+"),
253   cl::init(true),
254   cl::Hidden);
255 
256 static cl::opt<bool> OptVGPRLiveRange(
257     "amdgpu-opt-vgpr-liverange",
258     cl::desc("Enable VGPR liverange optimizations for if-else structure"),
259     cl::init(true), cl::Hidden);
260 
261 // Enable atomic optimization
262 static cl::opt<bool> EnableAtomicOptimizations(
263   "amdgpu-atomic-optimizations",
264   cl::desc("Enable atomic optimizations"),
265   cl::init(false),
266   cl::Hidden);
267 
268 // Enable Mode register optimization
269 static cl::opt<bool> EnableSIModeRegisterPass(
270   "amdgpu-mode-register",
271   cl::desc("Enable mode register pass"),
272   cl::init(true),
273   cl::Hidden);
274 
275 // Enable GFX11+ s_delay_alu insertion
276 static cl::opt<bool>
277     EnableInsertDelayAlu("amdgpu-enable-delay-alu",
278                          cl::desc("Enable s_delay_alu insertion"),
279                          cl::init(true), cl::Hidden);
280 
281 // Option is used in lit tests to prevent deadcoding of patterns inspected.
282 static cl::opt<bool>
283 EnableDCEInRA("amdgpu-dce-in-ra",
284     cl::init(true), cl::Hidden,
285     cl::desc("Enable machine DCE inside regalloc"));
286 
287 static cl::opt<bool> EnableSetWavePriority("amdgpu-set-wave-priority",
288                                            cl::desc("Adjust wave priority"),
289                                            cl::init(false), cl::Hidden);
290 
291 static cl::opt<bool> EnableScalarIRPasses(
292   "amdgpu-scalar-ir-passes",
293   cl::desc("Enable scalar IR passes"),
294   cl::init(true),
295   cl::Hidden);
296 
297 static cl::opt<bool> EnableStructurizerWorkarounds(
298     "amdgpu-enable-structurizer-workarounds",
299     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
300     cl::Hidden);
301 
302 static cl::opt<bool> EnableLDSReplaceWithPointer(
303     "amdgpu-enable-lds-replace-with-pointer",
304     cl::desc("Enable LDS replace with pointer pass"), cl::init(false),
305     cl::Hidden);
306 
307 static cl::opt<bool, true> EnableLowerModuleLDS(
308     "amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"),
309     cl::location(AMDGPUTargetMachine::EnableLowerModuleLDS), cl::init(true),
310     cl::Hidden);
311 
312 static cl::opt<bool> EnablePreRAOptimizations(
313     "amdgpu-enable-pre-ra-optimizations",
314     cl::desc("Enable Pre-RA optimizations pass"), cl::init(true),
315     cl::Hidden);
316 
317 static cl::opt<bool> EnablePromoteKernelArguments(
318     "amdgpu-enable-promote-kernel-arguments",
319     cl::desc("Enable promotion of flat kernel pointer arguments to global"),
320     cl::Hidden, cl::init(true));
321 
322 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
323   // Register the target
324   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
325   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
326 
327   PassRegistry *PR = PassRegistry::getPassRegistry();
328   initializeR600ClauseMergePassPass(*PR);
329   initializeR600ControlFlowFinalizerPass(*PR);
330   initializeR600PacketizerPass(*PR);
331   initializeR600ExpandSpecialInstrsPassPass(*PR);
332   initializeR600VectorRegMergerPass(*PR);
333   initializeGlobalISel(*PR);
334   initializeAMDGPUDAGToDAGISelPass(*PR);
335   initializeGCNDPPCombinePass(*PR);
336   initializeSILowerI1CopiesPass(*PR);
337   initializeSILowerSGPRSpillsPass(*PR);
338   initializeSIFixSGPRCopiesPass(*PR);
339   initializeSIFixVGPRCopiesPass(*PR);
340   initializeSIFoldOperandsPass(*PR);
341   initializeSIPeepholeSDWAPass(*PR);
342   initializeSIShrinkInstructionsPass(*PR);
343   initializeSIOptimizeExecMaskingPreRAPass(*PR);
344   initializeSIOptimizeVGPRLiveRangePass(*PR);
345   initializeSILoadStoreOptimizerPass(*PR);
346   initializeAMDGPUCtorDtorLoweringPass(*PR);
347   initializeAMDGPUAlwaysInlinePass(*PR);
348   initializeAMDGPUAttributorPass(*PR);
349   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
350   initializeAMDGPUAnnotateUniformValuesPass(*PR);
351   initializeAMDGPUArgumentUsageInfoPass(*PR);
352   initializeAMDGPUAtomicOptimizerPass(*PR);
353   initializeAMDGPULowerKernelArgumentsPass(*PR);
354   initializeAMDGPUPromoteKernelArgumentsPass(*PR);
355   initializeAMDGPULowerKernelAttributesPass(*PR);
356   initializeAMDGPULowerIntrinsicsPass(*PR);
357   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
358   initializeAMDGPUPostLegalizerCombinerPass(*PR);
359   initializeAMDGPUPreLegalizerCombinerPass(*PR);
360   initializeAMDGPURegBankCombinerPass(*PR);
361   initializeAMDGPUPromoteAllocaPass(*PR);
362   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
363   initializeAMDGPUCodeGenPreparePass(*PR);
364   initializeAMDGPULateCodeGenPreparePass(*PR);
365   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
366   initializeAMDGPUPropagateAttributesLatePass(*PR);
367   initializeAMDGPUReplaceLDSUseWithPointerPass(*PR);
368   initializeAMDGPULowerModuleLDSPass(*PR);
369   initializeAMDGPURewriteOutArgumentsPass(*PR);
370   initializeAMDGPUUnifyMetadataPass(*PR);
371   initializeSIAnnotateControlFlowPass(*PR);
372   initializeAMDGPUInsertDelayAluPass(*PR);
373   initializeSIInsertHardClausesPass(*PR);
374   initializeSIInsertWaitcntsPass(*PR);
375   initializeSIModeRegisterPass(*PR);
376   initializeSIWholeQuadModePass(*PR);
377   initializeSILowerControlFlowPass(*PR);
378   initializeSIPreEmitPeepholePass(*PR);
379   initializeSILateBranchLoweringPass(*PR);
380   initializeSIMemoryLegalizerPass(*PR);
381   initializeSIOptimizeExecMaskingPass(*PR);
382   initializeSIPreAllocateWWMRegsPass(*PR);
383   initializeSIFormMemoryClausesPass(*PR);
384   initializeSIPostRABundlerPass(*PR);
385   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
386   initializeAMDGPUAAWrapperPassPass(*PR);
387   initializeAMDGPUExternalAAWrapperPass(*PR);
388   initializeAMDGPUUseNativeCallsPass(*PR);
389   initializeAMDGPUSimplifyLibCallsPass(*PR);
390   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
391   initializeAMDGPUResourceUsageAnalysisPass(*PR);
392   initializeGCNNSAReassignPass(*PR);
393   initializeGCNPreRAOptimizationsPass(*PR);
394 }
395 
396 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
397   return std::make_unique<AMDGPUTargetObjectFile>();
398 }
399 
400 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
401   return new SIScheduleDAGMI(C);
402 }
403 
404 static ScheduleDAGInstrs *
405 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
406   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
407   ScheduleDAGMILive *DAG =
408     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
409   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
410   if (ST.shouldClusterStores())
411     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
412   DAG->addMutation(createIGroupLPDAGMutation());
413   DAG->addMutation(createSchedBarrierDAGMutation());
414   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
415   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
416   return DAG;
417 }
418 
419 static ScheduleDAGInstrs *
420 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
421   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
422   auto DAG = new GCNIterativeScheduler(C,
423     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
424   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
425   if (ST.shouldClusterStores())
426     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
427   return DAG;
428 }
429 
430 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
431   return new GCNIterativeScheduler(C,
432     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
433 }
434 
435 static ScheduleDAGInstrs *
436 createIterativeILPMachineScheduler(MachineSchedContext *C) {
437   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
438   auto DAG = new GCNIterativeScheduler(C,
439     GCNIterativeScheduler::SCHEDULE_ILP);
440   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
441   if (ST.shouldClusterStores())
442     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
443   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
444   return DAG;
445 }
446 
447 static MachineSchedRegistry
448 SISchedRegistry("si", "Run SI's custom scheduler",
449                 createSIMachineScheduler);
450 
451 static MachineSchedRegistry
452 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
453                              "Run GCN scheduler to maximize occupancy",
454                              createGCNMaxOccupancyMachineScheduler);
455 
456 static MachineSchedRegistry
457 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
458   "Run GCN scheduler to maximize occupancy (experimental)",
459   createIterativeGCNMaxOccupancyMachineScheduler);
460 
461 static MachineSchedRegistry
462 GCNMinRegSchedRegistry("gcn-minreg",
463   "Run GCN iterative scheduler for minimal register usage (experimental)",
464   createMinRegScheduler);
465 
466 static MachineSchedRegistry
467 GCNILPSchedRegistry("gcn-ilp",
468   "Run GCN iterative scheduler for ILP scheduling (experimental)",
469   createIterativeILPMachineScheduler);
470 
471 static StringRef computeDataLayout(const Triple &TT) {
472   if (TT.getArch() == Triple::r600) {
473     // 32-bit pointers.
474     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
475            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
476   }
477 
478   // 32-bit private, local, and region pointers. 64-bit global, constant and
479   // flat, non-integral buffer fat pointers.
480   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
481          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
482          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
483          "-ni:7";
484 }
485 
486 LLVM_READNONE
487 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
488   if (!GPU.empty())
489     return GPU;
490 
491   // Need to default to a target with flat support for HSA.
492   if (TT.getArch() == Triple::amdgcn)
493     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
494 
495   return "r600";
496 }
497 
498 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
499   // The AMDGPU toolchain only supports generating shared objects, so we
500   // must always use PIC.
501   return Reloc::PIC_;
502 }
503 
504 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
505                                          StringRef CPU, StringRef FS,
506                                          TargetOptions Options,
507                                          Optional<Reloc::Model> RM,
508                                          Optional<CodeModel::Model> CM,
509                                          CodeGenOpt::Level OptLevel)
510     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
511                         FS, Options, getEffectiveRelocModel(RM),
512                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
513       TLOF(createTLOF(getTargetTriple())) {
514   initAsmInfo();
515   if (TT.getArch() == Triple::amdgcn) {
516     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
517       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
518     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
519       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
520   }
521 }
522 
523 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
524 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
525 bool AMDGPUTargetMachine::EnableLowerModuleLDS = true;
526 
527 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
528 
529 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
530   Attribute GPUAttr = F.getFnAttribute("target-cpu");
531   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
532 }
533 
534 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
535   Attribute FSAttr = F.getFnAttribute("target-features");
536 
537   return FSAttr.isValid() ? FSAttr.getValueAsString()
538                           : getTargetFeatureString();
539 }
540 
541 /// Predicate for Internalize pass.
542 static bool mustPreserveGV(const GlobalValue &GV) {
543   if (const Function *F = dyn_cast<Function>(&GV))
544     return F->isDeclaration() || F->getName().startswith("__asan_") ||
545            F->getName().startswith("__sanitizer_") ||
546            AMDGPU::isEntryFunctionCC(F->getCallingConv());
547 
548   GV.removeDeadConstantUsers();
549   return !GV.use_empty();
550 }
551 
552 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
553   Builder.DivergentTarget = true;
554 
555   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
556   bool Internalize = InternalizeSymbols;
557   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
558   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
559   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
560   bool PromoteKernelArguments =
561       EnablePromoteKernelArguments && getOptLevel() > CodeGenOpt::Less;
562 
563   if (EnableFunctionCalls) {
564     delete Builder.Inliner;
565     Builder.Inliner = createFunctionInliningPass();
566   }
567 
568   Builder.addExtension(
569     PassManagerBuilder::EP_ModuleOptimizerEarly,
570     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
571                                                legacy::PassManagerBase &PM) {
572       if (AMDGPUAA) {
573         PM.add(createAMDGPUAAWrapperPass());
574         PM.add(createAMDGPUExternalAAWrapperPass());
575       }
576       PM.add(createAMDGPUUnifyMetadataPass());
577       PM.add(createAMDGPUPrintfRuntimeBinding());
578       if (Internalize)
579         PM.add(createInternalizePass(mustPreserveGV));
580       PM.add(createAMDGPUPropagateAttributesLatePass(this));
581       if (Internalize)
582         PM.add(createGlobalDCEPass());
583       if (EarlyInline)
584         PM.add(createAMDGPUAlwaysInlinePass(false));
585   });
586 
587   Builder.addExtension(
588     PassManagerBuilder::EP_EarlyAsPossible,
589     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
590                                       legacy::PassManagerBase &PM) {
591       if (AMDGPUAA) {
592         PM.add(createAMDGPUAAWrapperPass());
593         PM.add(createAMDGPUExternalAAWrapperPass());
594       }
595       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
596       PM.add(llvm::createAMDGPUUseNativeCallsPass());
597       if (LibCallSimplify)
598         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
599   });
600 
601   Builder.addExtension(
602     PassManagerBuilder::EP_CGSCCOptimizerLate,
603     [EnableOpt, PromoteKernelArguments](const PassManagerBuilder &,
604                                         legacy::PassManagerBase &PM) {
605       // Add promote kernel arguments pass to the opt pipeline right before
606       // infer address spaces which is needed to do actual address space
607       // rewriting.
608       if (PromoteKernelArguments)
609         PM.add(createAMDGPUPromoteKernelArgumentsPass());
610 
611       // Add infer address spaces pass to the opt pipeline after inlining
612       // but before SROA to increase SROA opportunities.
613       PM.add(createInferAddressSpacesPass());
614 
615       // This should run after inlining to have any chance of doing anything,
616       // and before other cleanup optimizations.
617       PM.add(createAMDGPULowerKernelAttributesPass());
618 
619       // Promote alloca to vector before SROA and loop unroll. If we manage
620       // to eliminate allocas before unroll we may choose to unroll less.
621       if (EnableOpt)
622         PM.add(createAMDGPUPromoteAllocaToVector());
623   });
624 }
625 
626 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
627   AAM.registerFunctionAnalysis<AMDGPUAA>();
628 }
629 
630 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
631   PB.registerPipelineParsingCallback(
632       [this](StringRef PassName, ModulePassManager &PM,
633              ArrayRef<PassBuilder::PipelineElement>) {
634         if (PassName == "amdgpu-propagate-attributes-late") {
635           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
636           return true;
637         }
638         if (PassName == "amdgpu-unify-metadata") {
639           PM.addPass(AMDGPUUnifyMetadataPass());
640           return true;
641         }
642         if (PassName == "amdgpu-printf-runtime-binding") {
643           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
644           return true;
645         }
646         if (PassName == "amdgpu-always-inline") {
647           PM.addPass(AMDGPUAlwaysInlinePass());
648           return true;
649         }
650         if (PassName == "amdgpu-replace-lds-use-with-pointer") {
651           PM.addPass(AMDGPUReplaceLDSUseWithPointerPass());
652           return true;
653         }
654         if (PassName == "amdgpu-lower-module-lds") {
655           PM.addPass(AMDGPULowerModuleLDSPass());
656           return true;
657         }
658         return false;
659       });
660   PB.registerPipelineParsingCallback(
661       [this](StringRef PassName, FunctionPassManager &PM,
662              ArrayRef<PassBuilder::PipelineElement>) {
663         if (PassName == "amdgpu-simplifylib") {
664           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
665           return true;
666         }
667         if (PassName == "amdgpu-usenative") {
668           PM.addPass(AMDGPUUseNativeCallsPass());
669           return true;
670         }
671         if (PassName == "amdgpu-promote-alloca") {
672           PM.addPass(AMDGPUPromoteAllocaPass(*this));
673           return true;
674         }
675         if (PassName == "amdgpu-promote-alloca-to-vector") {
676           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
677           return true;
678         }
679         if (PassName == "amdgpu-lower-kernel-attributes") {
680           PM.addPass(AMDGPULowerKernelAttributesPass());
681           return true;
682         }
683         if (PassName == "amdgpu-propagate-attributes-early") {
684           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
685           return true;
686         }
687         if (PassName == "amdgpu-promote-kernel-arguments") {
688           PM.addPass(AMDGPUPromoteKernelArgumentsPass());
689           return true;
690         }
691         return false;
692       });
693 
694   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
695     FAM.registerPass([&] { return AMDGPUAA(); });
696   });
697 
698   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
699     if (AAName == "amdgpu-aa") {
700       AAM.registerFunctionAnalysis<AMDGPUAA>();
701       return true;
702     }
703     return false;
704   });
705 
706   PB.registerPipelineStartEPCallback(
707       [this](ModulePassManager &PM, OptimizationLevel Level) {
708         FunctionPassManager FPM;
709         FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
710         FPM.addPass(AMDGPUUseNativeCallsPass());
711         if (EnableLibCallSimplify && Level != OptimizationLevel::O0)
712           FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
713         PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
714       });
715 
716   PB.registerPipelineEarlySimplificationEPCallback(
717       [this](ModulePassManager &PM, OptimizationLevel Level) {
718         if (Level == OptimizationLevel::O0)
719           return;
720 
721         PM.addPass(AMDGPUUnifyMetadataPass());
722         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
723 
724         if (InternalizeSymbols) {
725           PM.addPass(InternalizePass(mustPreserveGV));
726         }
727         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
728         if (InternalizeSymbols) {
729           PM.addPass(GlobalDCEPass());
730         }
731         if (EarlyInlineAll && !EnableFunctionCalls)
732           PM.addPass(AMDGPUAlwaysInlinePass());
733       });
734 
735   PB.registerCGSCCOptimizerLateEPCallback(
736       [this](CGSCCPassManager &PM, OptimizationLevel Level) {
737         if (Level == OptimizationLevel::O0)
738           return;
739 
740         FunctionPassManager FPM;
741 
742         // Add promote kernel arguments pass to the opt pipeline right before
743         // infer address spaces which is needed to do actual address space
744         // rewriting.
745         if (Level.getSpeedupLevel() > OptimizationLevel::O1.getSpeedupLevel() &&
746             EnablePromoteKernelArguments)
747           FPM.addPass(AMDGPUPromoteKernelArgumentsPass());
748 
749         // Add infer address spaces pass to the opt pipeline after inlining
750         // but before SROA to increase SROA opportunities.
751         FPM.addPass(InferAddressSpacesPass());
752 
753         // This should run after inlining to have any chance of doing
754         // anything, and before other cleanup optimizations.
755         FPM.addPass(AMDGPULowerKernelAttributesPass());
756 
757         if (Level != OptimizationLevel::O0) {
758           // Promote alloca to vector before SROA and loop unroll. If we
759           // manage to eliminate allocas before unroll we may choose to unroll
760           // less.
761           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
762         }
763 
764         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
765       });
766 }
767 
768 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
769   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
770           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
771           AddrSpace == AMDGPUAS::REGION_ADDRESS)
772              ? -1
773              : 0;
774 }
775 
776 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
777                                               unsigned DestAS) const {
778   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
779          AMDGPU::isFlatGlobalAddrSpace(DestAS);
780 }
781 
782 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
783   const auto *LD = dyn_cast<LoadInst>(V);
784   if (!LD)
785     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
786 
787   // It must be a generic pointer loaded.
788   assert(V->getType()->isPointerTy() &&
789          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
790 
791   const auto *Ptr = LD->getPointerOperand();
792   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
793     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
794   // For a generic pointer loaded from the constant memory, it could be assumed
795   // as a global pointer since the constant memory is only populated on the
796   // host side. As implied by the offload programming model, only global
797   // pointers could be referenced on the host side.
798   return AMDGPUAS::GLOBAL_ADDRESS;
799 }
800 
801 std::pair<const Value *, unsigned>
802 AMDGPUTargetMachine::getPredicatedAddrSpace(const Value *V) const {
803   if (auto *II = dyn_cast<IntrinsicInst>(V)) {
804     switch (II->getIntrinsicID()) {
805     case Intrinsic::amdgcn_is_shared:
806       return std::make_pair(II->getArgOperand(0), AMDGPUAS::LOCAL_ADDRESS);
807     case Intrinsic::amdgcn_is_private:
808       return std::make_pair(II->getArgOperand(0), AMDGPUAS::PRIVATE_ADDRESS);
809     default:
810       break;
811     }
812     return std::make_pair(nullptr, -1);
813   }
814   // Check the global pointer predication based on
815   // (!is_share(p) && !is_private(p)). Note that logic 'and' is commutative and
816   // the order of 'is_shared' and 'is_private' is not significant.
817   Value *Ptr;
818   if (match(
819           const_cast<Value *>(V),
820           m_c_And(m_Not(m_Intrinsic<Intrinsic::amdgcn_is_shared>(m_Value(Ptr))),
821                   m_Not(m_Intrinsic<Intrinsic::amdgcn_is_private>(
822                       m_Deferred(Ptr))))))
823     return std::make_pair(Ptr, AMDGPUAS::GLOBAL_ADDRESS);
824 
825   return std::make_pair(nullptr, -1);
826 }
827 
828 unsigned
829 AMDGPUTargetMachine::getAddressSpaceForPseudoSourceKind(unsigned Kind) const {
830   switch (Kind) {
831   case PseudoSourceValue::Stack:
832   case PseudoSourceValue::FixedStack:
833     return AMDGPUAS::PRIVATE_ADDRESS;
834   case PseudoSourceValue::ConstantPool:
835   case PseudoSourceValue::GOT:
836   case PseudoSourceValue::JumpTable:
837   case PseudoSourceValue::GlobalValueCallEntry:
838   case PseudoSourceValue::ExternalSymbolCallEntry:
839   case PseudoSourceValue::TargetCustom:
840     return AMDGPUAS::CONSTANT_ADDRESS;
841   }
842   return AMDGPUAS::FLAT_ADDRESS;
843 }
844 
845 //===----------------------------------------------------------------------===//
846 // GCN Target Machine (SI+)
847 //===----------------------------------------------------------------------===//
848 
849 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
850                                    StringRef CPU, StringRef FS,
851                                    TargetOptions Options,
852                                    Optional<Reloc::Model> RM,
853                                    Optional<CodeModel::Model> CM,
854                                    CodeGenOpt::Level OL, bool JIT)
855     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
856 
857 const TargetSubtargetInfo *
858 GCNTargetMachine::getSubtargetImpl(const Function &F) const {
859   StringRef GPU = getGPUName(F);
860   StringRef FS = getFeatureString(F);
861 
862   SmallString<128> SubtargetKey(GPU);
863   SubtargetKey.append(FS);
864 
865   auto &I = SubtargetMap[SubtargetKey];
866   if (!I) {
867     // This needs to be done before we create a new subtarget since any
868     // creation will depend on the TM and the code generation flags on the
869     // function that reside in TargetOptions.
870     resetTargetOptions(F);
871     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
872   }
873 
874   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
875 
876   return I.get();
877 }
878 
879 TargetTransformInfo
880 GCNTargetMachine::getTargetTransformInfo(const Function &F) const {
881   return TargetTransformInfo(GCNTTIImpl(this, F));
882 }
883 
884 //===----------------------------------------------------------------------===//
885 // AMDGPU Pass Setup
886 //===----------------------------------------------------------------------===//
887 
888 std::unique_ptr<CSEConfigBase> llvm::AMDGPUPassConfig::getCSEConfig() const {
889   return getStandardCSEConfigForOpt(TM->getOptLevel());
890 }
891 
892 namespace {
893 
894 class GCNPassConfig final : public AMDGPUPassConfig {
895 public:
896   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
897     : AMDGPUPassConfig(TM, PM) {
898     // It is necessary to know the register usage of the entire call graph.  We
899     // allow calls without EnableAMDGPUFunctionCalls if they are marked
900     // noinline, so this is always required.
901     setRequiresCodeGenSCCOrder(true);
902     substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
903   }
904 
905   GCNTargetMachine &getGCNTargetMachine() const {
906     return getTM<GCNTargetMachine>();
907   }
908 
909   ScheduleDAGInstrs *
910   createMachineScheduler(MachineSchedContext *C) const override;
911 
912   ScheduleDAGInstrs *
913   createPostMachineScheduler(MachineSchedContext *C) const override {
914     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
915     const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
916     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
917     if (ST.shouldClusterStores())
918       DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
919     DAG->addMutation(ST.createFillMFMAShadowMutation(DAG->TII));
920     DAG->addMutation(createIGroupLPDAGMutation());
921     DAG->addMutation(createSchedBarrierDAGMutation());
922     return DAG;
923   }
924 
925   bool addPreISel() override;
926   void addMachineSSAOptimization() override;
927   bool addILPOpts() override;
928   bool addInstSelector() override;
929   bool addIRTranslator() override;
930   void addPreLegalizeMachineIR() override;
931   bool addLegalizeMachineIR() override;
932   void addPreRegBankSelect() override;
933   bool addRegBankSelect() override;
934   void addPreGlobalInstructionSelect() override;
935   bool addGlobalInstructionSelect() override;
936   void addFastRegAlloc() override;
937   void addOptimizedRegAlloc() override;
938 
939   FunctionPass *createSGPRAllocPass(bool Optimized);
940   FunctionPass *createVGPRAllocPass(bool Optimized);
941   FunctionPass *createRegAllocPass(bool Optimized) override;
942 
943   bool addRegAssignAndRewriteFast() override;
944   bool addRegAssignAndRewriteOptimized() override;
945 
946   void addPreRegAlloc() override;
947   bool addPreRewrite() override;
948   void addPostRegAlloc() override;
949   void addPreSched2() override;
950   void addPreEmitPass() override;
951 };
952 
953 } // end anonymous namespace
954 
955 AMDGPUPassConfig::AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
956     : TargetPassConfig(TM, PM) {
957   // Exceptions and StackMaps are not supported, so these passes will never do
958   // anything.
959   disablePass(&StackMapLivenessID);
960   disablePass(&FuncletLayoutID);
961   // Garbage collection is not supported.
962   disablePass(&GCLoweringID);
963   disablePass(&ShadowStackGCLoweringID);
964 }
965 
966 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
967   if (getOptLevel() == CodeGenOpt::Aggressive)
968     addPass(createGVNPass());
969   else
970     addPass(createEarlyCSEPass());
971 }
972 
973 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
974   addPass(createLICMPass());
975   addPass(createSeparateConstOffsetFromGEPPass());
976   addPass(createSpeculativeExecutionPass());
977   // ReassociateGEPs exposes more opportunities for SLSR. See
978   // the example in reassociate-geps-and-slsr.ll.
979   addPass(createStraightLineStrengthReducePass());
980   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
981   // EarlyCSE can reuse.
982   addEarlyCSEOrGVNPass();
983   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
984   addPass(createNaryReassociatePass());
985   // NaryReassociate on GEPs creates redundant common expressions, so run
986   // EarlyCSE after it.
987   addPass(createEarlyCSEPass());
988 }
989 
990 void AMDGPUPassConfig::addIRPasses() {
991   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
992 
993   // There is no reason to run these.
994   disablePass(&StackMapLivenessID);
995   disablePass(&FuncletLayoutID);
996   disablePass(&PatchableFunctionID);
997 
998   addPass(createAMDGPUPrintfRuntimeBinding());
999   addPass(createAMDGPUCtorDtorLoweringPass());
1000 
1001   // A call to propagate attributes pass in the backend in case opt was not run.
1002   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
1003 
1004   addPass(createAMDGPULowerIntrinsicsPass());
1005 
1006   // Function calls are not supported, so make sure we inline everything.
1007   addPass(createAMDGPUAlwaysInlinePass());
1008   addPass(createAlwaysInlinerLegacyPass());
1009   // We need to add the barrier noop pass, otherwise adding the function
1010   // inlining pass will cause all of the PassConfigs passes to be run
1011   // one function at a time, which means if we have a module with two
1012   // functions, then we will generate code for the first function
1013   // without ever running any passes on the second.
1014   addPass(createBarrierNoopPass());
1015 
1016   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
1017   if (TM.getTargetTriple().getArch() == Triple::r600)
1018     addPass(createR600OpenCLImageTypeLoweringPass());
1019 
1020   // Replace OpenCL enqueued block function pointers with global variables.
1021   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
1022 
1023   // Can increase LDS used by kernel so runs before PromoteAlloca
1024   if (EnableLowerModuleLDS) {
1025     // The pass "amdgpu-replace-lds-use-with-pointer" need to be run before the
1026     // pass "amdgpu-lower-module-lds", and also it required to be run only if
1027     // "amdgpu-lower-module-lds" pass is enabled.
1028     if (EnableLDSReplaceWithPointer)
1029       addPass(createAMDGPUReplaceLDSUseWithPointerPass());
1030 
1031     addPass(createAMDGPULowerModuleLDSPass());
1032   }
1033 
1034   if (TM.getOptLevel() > CodeGenOpt::None)
1035     addPass(createInferAddressSpacesPass());
1036 
1037   addPass(createAtomicExpandPass());
1038 
1039   if (TM.getOptLevel() > CodeGenOpt::None) {
1040     addPass(createAMDGPUPromoteAlloca());
1041 
1042     if (EnableSROA)
1043       addPass(createSROAPass());
1044     if (isPassEnabled(EnableScalarIRPasses))
1045       addStraightLineScalarOptimizationPasses();
1046 
1047     if (EnableAMDGPUAliasAnalysis) {
1048       addPass(createAMDGPUAAWrapperPass());
1049       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
1050                                              AAResults &AAR) {
1051         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
1052           AAR.addAAResult(WrapperPass->getResult());
1053         }));
1054     }
1055 
1056     if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
1057       // TODO: May want to move later or split into an early and late one.
1058       addPass(createAMDGPUCodeGenPreparePass());
1059     }
1060   }
1061 
1062   TargetPassConfig::addIRPasses();
1063 
1064   // EarlyCSE is not always strong enough to clean up what LSR produces. For
1065   // example, GVN can combine
1066   //
1067   //   %0 = add %a, %b
1068   //   %1 = add %b, %a
1069   //
1070   // and
1071   //
1072   //   %0 = shl nsw %a, 2
1073   //   %1 = shl %a, 2
1074   //
1075   // but EarlyCSE can do neither of them.
1076   if (isPassEnabled(EnableScalarIRPasses))
1077     addEarlyCSEOrGVNPass();
1078 }
1079 
1080 void AMDGPUPassConfig::addCodeGenPrepare() {
1081   if (TM->getTargetTriple().getArch() == Triple::amdgcn) {
1082     addPass(createAMDGPUAttributorPass());
1083 
1084     // FIXME: This pass adds 2 hacky attributes that can be replaced with an
1085     // analysis, and should be removed.
1086     addPass(createAMDGPUAnnotateKernelFeaturesPass());
1087   }
1088 
1089   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
1090       EnableLowerKernelArguments)
1091     addPass(createAMDGPULowerKernelArgumentsPass());
1092 
1093   TargetPassConfig::addCodeGenPrepare();
1094 
1095   if (isPassEnabled(EnableLoadStoreVectorizer))
1096     addPass(createLoadStoreVectorizerPass());
1097 
1098   // LowerSwitch pass may introduce unreachable blocks that can
1099   // cause unexpected behavior for subsequent passes. Placing it
1100   // here seems better that these blocks would get cleaned up by
1101   // UnreachableBlockElim inserted next in the pass flow.
1102   addPass(createLowerSwitchPass());
1103 }
1104 
1105 bool AMDGPUPassConfig::addPreISel() {
1106   if (TM->getOptLevel() > CodeGenOpt::None)
1107     addPass(createFlattenCFGPass());
1108   return false;
1109 }
1110 
1111 bool AMDGPUPassConfig::addInstSelector() {
1112   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
1113   return false;
1114 }
1115 
1116 bool AMDGPUPassConfig::addGCPasses() {
1117   // Do nothing. GC is not supported.
1118   return false;
1119 }
1120 
1121 llvm::ScheduleDAGInstrs *
1122 AMDGPUPassConfig::createMachineScheduler(MachineSchedContext *C) const {
1123   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1124   ScheduleDAGMILive *DAG = createGenericSchedLive(C);
1125   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1126   if (ST.shouldClusterStores())
1127     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1128   return DAG;
1129 }
1130 
1131 //===----------------------------------------------------------------------===//
1132 // GCN Pass Setup
1133 //===----------------------------------------------------------------------===//
1134 
1135 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1136   MachineSchedContext *C) const {
1137   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1138   if (ST.enableSIScheduler())
1139     return createSIMachineScheduler(C);
1140   return createGCNMaxOccupancyMachineScheduler(C);
1141 }
1142 
1143 bool GCNPassConfig::addPreISel() {
1144   AMDGPUPassConfig::addPreISel();
1145 
1146   if (TM->getOptLevel() > CodeGenOpt::None)
1147     addPass(createAMDGPULateCodeGenPreparePass());
1148 
1149   if (isPassEnabled(EnableAtomicOptimizations, CodeGenOpt::Less)) {
1150     addPass(createAMDGPUAtomicOptimizerPass());
1151   }
1152 
1153   if (TM->getOptLevel() > CodeGenOpt::None)
1154     addPass(createSinkingPass());
1155 
1156   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1157   // regions formed by them.
1158   addPass(&AMDGPUUnifyDivergentExitNodesID);
1159   if (!LateCFGStructurize) {
1160     if (EnableStructurizerWorkarounds) {
1161       addPass(createFixIrreduciblePass());
1162       addPass(createUnifyLoopExitsPass());
1163     }
1164     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1165   }
1166   addPass(createAMDGPUAnnotateUniformValues());
1167   if (!LateCFGStructurize) {
1168     addPass(createSIAnnotateControlFlowPass());
1169   }
1170   addPass(createLCSSAPass());
1171 
1172   if (TM->getOptLevel() > CodeGenOpt::Less)
1173     addPass(&AMDGPUPerfHintAnalysisID);
1174 
1175   return false;
1176 }
1177 
1178 void GCNPassConfig::addMachineSSAOptimization() {
1179   TargetPassConfig::addMachineSSAOptimization();
1180 
1181   // We want to fold operands after PeepholeOptimizer has run (or as part of
1182   // it), because it will eliminate extra copies making it easier to fold the
1183   // real source operand. We want to eliminate dead instructions after, so that
1184   // we see fewer uses of the copies. We then need to clean up the dead
1185   // instructions leftover after the operands are folded as well.
1186   //
1187   // XXX - Can we get away without running DeadMachineInstructionElim again?
1188   addPass(&SIFoldOperandsID);
1189   if (EnableDPPCombine)
1190     addPass(&GCNDPPCombineID);
1191   addPass(&SILoadStoreOptimizerID);
1192   if (isPassEnabled(EnableSDWAPeephole)) {
1193     addPass(&SIPeepholeSDWAID);
1194     addPass(&EarlyMachineLICMID);
1195     addPass(&MachineCSEID);
1196     addPass(&SIFoldOperandsID);
1197   }
1198   addPass(&DeadMachineInstructionElimID);
1199   addPass(createSIShrinkInstructionsPass());
1200 }
1201 
1202 bool GCNPassConfig::addILPOpts() {
1203   if (EnableEarlyIfConversion)
1204     addPass(&EarlyIfConverterID);
1205 
1206   TargetPassConfig::addILPOpts();
1207   return false;
1208 }
1209 
1210 bool GCNPassConfig::addInstSelector() {
1211   AMDGPUPassConfig::addInstSelector();
1212   addPass(&SIFixSGPRCopiesID);
1213   addPass(createSILowerI1CopiesPass());
1214   return false;
1215 }
1216 
1217 bool GCNPassConfig::addIRTranslator() {
1218   addPass(new IRTranslator(getOptLevel()));
1219   return false;
1220 }
1221 
1222 void GCNPassConfig::addPreLegalizeMachineIR() {
1223   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1224   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1225   addPass(new Localizer());
1226 }
1227 
1228 bool GCNPassConfig::addLegalizeMachineIR() {
1229   addPass(new Legalizer());
1230   return false;
1231 }
1232 
1233 void GCNPassConfig::addPreRegBankSelect() {
1234   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1235   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1236 }
1237 
1238 bool GCNPassConfig::addRegBankSelect() {
1239   addPass(new RegBankSelect());
1240   return false;
1241 }
1242 
1243 void GCNPassConfig::addPreGlobalInstructionSelect() {
1244   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1245   addPass(createAMDGPURegBankCombiner(IsOptNone));
1246 }
1247 
1248 bool GCNPassConfig::addGlobalInstructionSelect() {
1249   addPass(new InstructionSelect(getOptLevel()));
1250   return false;
1251 }
1252 
1253 void GCNPassConfig::addPreRegAlloc() {
1254   if (LateCFGStructurize) {
1255     addPass(createAMDGPUMachineCFGStructurizerPass());
1256   }
1257 }
1258 
1259 void GCNPassConfig::addFastRegAlloc() {
1260   // FIXME: We have to disable the verifier here because of PHIElimination +
1261   // TwoAddressInstructions disabling it.
1262 
1263   // This must be run immediately after phi elimination and before
1264   // TwoAddressInstructions, otherwise the processing of the tied operand of
1265   // SI_ELSE will introduce a copy of the tied operand source after the else.
1266   insertPass(&PHIEliminationID, &SILowerControlFlowID);
1267 
1268   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1269   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1270 
1271   TargetPassConfig::addFastRegAlloc();
1272 }
1273 
1274 void GCNPassConfig::addOptimizedRegAlloc() {
1275   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1276   // instructions that cause scheduling barriers.
1277   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1278   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1279 
1280   if (OptExecMaskPreRA)
1281     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1282 
1283   if (isPassEnabled(EnablePreRAOptimizations))
1284     insertPass(&RenameIndependentSubregsID, &GCNPreRAOptimizationsID);
1285 
1286   // This is not an essential optimization and it has a noticeable impact on
1287   // compilation time, so we only enable it from O2.
1288   if (TM->getOptLevel() > CodeGenOpt::Less)
1289     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1290 
1291   // FIXME: when an instruction has a Killed operand, and the instruction is
1292   // inside a bundle, seems only the BUNDLE instruction appears as the Kills of
1293   // the register in LiveVariables, this would trigger a failure in verifier,
1294   // we should fix it and enable the verifier.
1295   if (OptVGPRLiveRange)
1296     insertPass(&LiveVariablesID, &SIOptimizeVGPRLiveRangeID);
1297   // This must be run immediately after phi elimination and before
1298   // TwoAddressInstructions, otherwise the processing of the tied operand of
1299   // SI_ELSE will introduce a copy of the tied operand source after the else.
1300   insertPass(&PHIEliminationID, &SILowerControlFlowID);
1301 
1302   if (EnableDCEInRA)
1303     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1304 
1305   TargetPassConfig::addOptimizedRegAlloc();
1306 }
1307 
1308 bool GCNPassConfig::addPreRewrite() {
1309   if (EnableRegReassign)
1310     addPass(&GCNNSAReassignID);
1311   return true;
1312 }
1313 
1314 FunctionPass *GCNPassConfig::createSGPRAllocPass(bool Optimized) {
1315   // Initialize the global default.
1316   llvm::call_once(InitializeDefaultSGPRRegisterAllocatorFlag,
1317                   initializeDefaultSGPRRegisterAllocatorOnce);
1318 
1319   RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
1320   if (Ctor != useDefaultRegisterAllocator)
1321     return Ctor();
1322 
1323   if (Optimized)
1324     return createGreedyRegisterAllocator(onlyAllocateSGPRs);
1325 
1326   return createFastRegisterAllocator(onlyAllocateSGPRs, false);
1327 }
1328 
1329 FunctionPass *GCNPassConfig::createVGPRAllocPass(bool Optimized) {
1330   // Initialize the global default.
1331   llvm::call_once(InitializeDefaultVGPRRegisterAllocatorFlag,
1332                   initializeDefaultVGPRRegisterAllocatorOnce);
1333 
1334   RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
1335   if (Ctor != useDefaultRegisterAllocator)
1336     return Ctor();
1337 
1338   if (Optimized)
1339     return createGreedyVGPRRegisterAllocator();
1340 
1341   return createFastVGPRRegisterAllocator();
1342 }
1343 
1344 FunctionPass *GCNPassConfig::createRegAllocPass(bool Optimized) {
1345   llvm_unreachable("should not be used");
1346 }
1347 
1348 static const char RegAllocOptNotSupportedMessage[] =
1349   "-regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc";
1350 
1351 bool GCNPassConfig::addRegAssignAndRewriteFast() {
1352   if (!usingDefaultRegAlloc())
1353     report_fatal_error(RegAllocOptNotSupportedMessage);
1354 
1355   addPass(createSGPRAllocPass(false));
1356 
1357   // Equivalent of PEI for SGPRs.
1358   addPass(&SILowerSGPRSpillsID);
1359 
1360   addPass(createVGPRAllocPass(false));
1361   return true;
1362 }
1363 
1364 bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
1365   if (!usingDefaultRegAlloc())
1366     report_fatal_error(RegAllocOptNotSupportedMessage);
1367 
1368   addPass(createSGPRAllocPass(true));
1369 
1370   // Commit allocated register changes. This is mostly necessary because too
1371   // many things rely on the use lists of the physical registers, such as the
1372   // verifier. This is only necessary with allocators which use LiveIntervals,
1373   // since FastRegAlloc does the replacements itself.
1374   addPass(createVirtRegRewriter(false));
1375 
1376   // Equivalent of PEI for SGPRs.
1377   addPass(&SILowerSGPRSpillsID);
1378 
1379   addPass(createVGPRAllocPass(true));
1380 
1381   addPreRewrite();
1382   addPass(&VirtRegRewriterID);
1383 
1384   return true;
1385 }
1386 
1387 void GCNPassConfig::addPostRegAlloc() {
1388   addPass(&SIFixVGPRCopiesID);
1389   if (getOptLevel() > CodeGenOpt::None)
1390     addPass(&SIOptimizeExecMaskingID);
1391   TargetPassConfig::addPostRegAlloc();
1392 }
1393 
1394 void GCNPassConfig::addPreSched2() {
1395   if (TM->getOptLevel() > CodeGenOpt::None)
1396     addPass(createSIShrinkInstructionsPass());
1397   addPass(&SIPostRABundlerID);
1398 }
1399 
1400 void GCNPassConfig::addPreEmitPass() {
1401   addPass(createSIMemoryLegalizerPass());
1402   addPass(createSIInsertWaitcntsPass());
1403 
1404   addPass(createSIModeRegisterPass());
1405 
1406   if (getOptLevel() > CodeGenOpt::None)
1407     addPass(&SIInsertHardClausesID);
1408 
1409   addPass(&SILateBranchLoweringPassID);
1410   if (isPassEnabled(EnableSetWavePriority, CodeGenOpt::Less))
1411     addPass(createAMDGPUSetWavePriorityPass());
1412   if (getOptLevel() > CodeGenOpt::None)
1413     addPass(&SIPreEmitPeepholeID);
1414   // The hazard recognizer that runs as part of the post-ra scheduler does not
1415   // guarantee to be able handle all hazards correctly. This is because if there
1416   // are multiple scheduling regions in a basic block, the regions are scheduled
1417   // bottom up, so when we begin to schedule a region we don't know what
1418   // instructions were emitted directly before it.
1419   //
1420   // Here we add a stand-alone hazard recognizer pass which can handle all
1421   // cases.
1422   addPass(&PostRAHazardRecognizerID);
1423 
1424   if (isPassEnabled(EnableInsertDelayAlu, CodeGenOpt::Less))
1425     addPass(&AMDGPUInsertDelayAluID);
1426 
1427   addPass(&BranchRelaxationPassID);
1428 }
1429 
1430 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1431   return new GCNPassConfig(*this, PM);
1432 }
1433 
1434 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1435   return new yaml::SIMachineFunctionInfo();
1436 }
1437 
1438 yaml::MachineFunctionInfo *
1439 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1440   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1441   return new yaml::SIMachineFunctionInfo(
1442       *MFI, *MF.getSubtarget().getRegisterInfo(), MF);
1443 }
1444 
1445 bool GCNTargetMachine::parseMachineFunctionInfo(
1446     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1447     SMDiagnostic &Error, SMRange &SourceRange) const {
1448   const yaml::SIMachineFunctionInfo &YamlMFI =
1449       static_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1450   MachineFunction &MF = PFS.MF;
1451   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1452 
1453   if (MFI->initializeBaseYamlFields(YamlMFI, MF, PFS, Error, SourceRange))
1454     return true;
1455 
1456   if (MFI->Occupancy == 0) {
1457     // Fixup the subtarget dependent default value.
1458     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1459     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1460   }
1461 
1462   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1463     Register TempReg;
1464     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1465       SourceRange = RegName.SourceRange;
1466       return true;
1467     }
1468     RegVal = TempReg;
1469 
1470     return false;
1471   };
1472 
1473   auto parseOptionalRegister = [&](const yaml::StringValue &RegName,
1474                                    Register &RegVal) {
1475     return !RegName.Value.empty() && parseRegister(RegName, RegVal);
1476   };
1477 
1478   if (parseOptionalRegister(YamlMFI.VGPRForAGPRCopy, MFI->VGPRForAGPRCopy))
1479     return true;
1480 
1481   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1482     // Create a diagnostic for a the register string literal.
1483     const MemoryBuffer &Buffer =
1484         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1485     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1486                          RegName.Value.size(), SourceMgr::DK_Error,
1487                          "incorrect register class for field", RegName.Value,
1488                          None, None);
1489     SourceRange = RegName.SourceRange;
1490     return true;
1491   };
1492 
1493   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1494       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1495       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1496     return true;
1497 
1498   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1499       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1500     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1501   }
1502 
1503   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1504       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1505     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1506   }
1507 
1508   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1509       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1510     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1511   }
1512 
1513   for (const auto &YamlReg : YamlMFI.WWMReservedRegs) {
1514     Register ParsedReg;
1515     if (parseRegister(YamlReg, ParsedReg))
1516       return true;
1517 
1518     MFI->reserveWWMRegister(ParsedReg);
1519   }
1520 
1521   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1522                                    const TargetRegisterClass &RC,
1523                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1524                                    unsigned SystemSGPRs) {
1525     // Skip parsing if it's not present.
1526     if (!A)
1527       return false;
1528 
1529     if (A->IsRegister) {
1530       Register Reg;
1531       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1532         SourceRange = A->RegisterName.SourceRange;
1533         return true;
1534       }
1535       if (!RC.contains(Reg))
1536         return diagnoseRegisterClass(A->RegisterName);
1537       Arg = ArgDescriptor::createRegister(Reg);
1538     } else
1539       Arg = ArgDescriptor::createStack(A->StackOffset);
1540     // Check and apply the optional mask.
1541     if (A->Mask)
1542       Arg = ArgDescriptor::createArg(Arg, *A->Mask);
1543 
1544     MFI->NumUserSGPRs += UserSGPRs;
1545     MFI->NumSystemSGPRs += SystemSGPRs;
1546     return false;
1547   };
1548 
1549   if (YamlMFI.ArgInfo &&
1550       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1551                              AMDGPU::SGPR_128RegClass,
1552                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1553        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1554                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1555                              2, 0) ||
1556        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1557                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1558        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1559                              AMDGPU::SReg_64RegClass,
1560                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1561        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1562                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1563                              2, 0) ||
1564        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1565                              AMDGPU::SReg_64RegClass,
1566                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1567        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1568                              AMDGPU::SGPR_32RegClass,
1569                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1570        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1571                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1572                              0, 1) ||
1573        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1574                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1575                              0, 1) ||
1576        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1577                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1578                              0, 1) ||
1579        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1580                              AMDGPU::SGPR_32RegClass,
1581                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1582        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1583                              AMDGPU::SGPR_32RegClass,
1584                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1585        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1586                              AMDGPU::SReg_64RegClass,
1587                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1588        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1589                              AMDGPU::SReg_64RegClass,
1590                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1591        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1592                              AMDGPU::VGPR_32RegClass,
1593                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1594        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1595                              AMDGPU::VGPR_32RegClass,
1596                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1597        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1598                              AMDGPU::VGPR_32RegClass,
1599                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1600     return true;
1601 
1602   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1603   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1604   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1605   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1606   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1607   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1608 
1609   return false;
1610 }
1611