1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600MachineScheduler.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIMachineScheduler.h"
27 #include "TargetInfo/AMDGPUTargetInfo.h"
28 #include "llvm/Analysis/CGSCCPassManager.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/Localizer.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MIRParser/MIParser.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/LegacyPassManager.h"
37 #include "llvm/IR/PassManager.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/Passes/PassBuilder.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Transforms/IPO.h"
42 #include "llvm/Transforms/IPO/AlwaysInliner.h"
43 #include "llvm/Transforms/IPO/GlobalDCE.h"
44 #include "llvm/Transforms/IPO/Internalize.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
49 #include "llvm/Transforms/Utils.h"
50 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
51 #include "llvm/Transforms/Vectorize.h"
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73             cl::desc("Run pre-RA exec mask optimizations"),
74             cl::init(true));
75 
76 static cl::opt<bool> EnableR600IfConvert(
77   "r600-if-convert",
78   cl::desc("Use if conversion pass"),
79   cl::ReallyHidden,
80   cl::init(true));
81 
82 // Option to disable vectorizer for tests.
83 static cl::opt<bool> EnableLoadStoreVectorizer(
84   "amdgpu-load-store-vectorizer",
85   cl::desc("Enable load store vectorizer"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to control global loads scalarization
90 static cl::opt<bool> ScalarizeGlobal(
91   "amdgpu-scalarize-global-loads",
92   cl::desc("Enable global load scalarization"),
93   cl::init(true),
94   cl::Hidden);
95 
96 // Option to run internalize pass.
97 static cl::opt<bool> InternalizeSymbols(
98   "amdgpu-internalize-symbols",
99   cl::desc("Enable elimination of non-kernel functions and unused globals"),
100   cl::init(false),
101   cl::Hidden);
102 
103 // Option to inline all early.
104 static cl::opt<bool> EarlyInlineAll(
105   "amdgpu-early-inline-all",
106   cl::desc("Inline all functions early"),
107   cl::init(false),
108   cl::Hidden);
109 
110 static cl::opt<bool> EnableSDWAPeephole(
111   "amdgpu-sdwa-peephole",
112   cl::desc("Enable SDWA peepholer"),
113   cl::init(true));
114 
115 static cl::opt<bool> EnableDPPCombine(
116   "amdgpu-dpp-combine",
117   cl::desc("Enable DPP combiner"),
118   cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122   cl::desc("Enable AMDGPU Alias Analysis"),
123   cl::init(true));
124 
125 // Option to run late CFG structurizer
126 static cl::opt<bool, true> LateCFGStructurize(
127   "amdgpu-late-structurize",
128   cl::desc("Enable late CFG structurization"),
129   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
130   cl::Hidden);
131 
132 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
133   "amdgpu-function-calls",
134   cl::desc("Enable AMDGPU function call support"),
135   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
136   cl::init(true),
137   cl::Hidden);
138 
139 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
140   "amdgpu-fixed-function-abi",
141   cl::desc("Enable all implicit function arguments"),
142   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
143   cl::init(false),
144   cl::Hidden);
145 
146 // Enable lib calls simplifications
147 static cl::opt<bool> EnableLibCallSimplify(
148   "amdgpu-simplify-libcall",
149   cl::desc("Enable amdgpu library simplifications"),
150   cl::init(true),
151   cl::Hidden);
152 
153 static cl::opt<bool> EnableLowerKernelArguments(
154   "amdgpu-ir-lower-kernel-arguments",
155   cl::desc("Lower kernel argument loads in IR pass"),
156   cl::init(true),
157   cl::Hidden);
158 
159 static cl::opt<bool> EnableRegReassign(
160   "amdgpu-reassign-regs",
161   cl::desc("Enable register reassign optimizations on gfx10+"),
162   cl::init(true),
163   cl::Hidden);
164 
165 // Enable atomic optimization
166 static cl::opt<bool> EnableAtomicOptimizations(
167   "amdgpu-atomic-optimizations",
168   cl::desc("Enable atomic optimizations"),
169   cl::init(false),
170   cl::Hidden);
171 
172 // Enable Mode register optimization
173 static cl::opt<bool> EnableSIModeRegisterPass(
174   "amdgpu-mode-register",
175   cl::desc("Enable mode register pass"),
176   cl::init(true),
177   cl::Hidden);
178 
179 // Option is used in lit tests to prevent deadcoding of patterns inspected.
180 static cl::opt<bool>
181 EnableDCEInRA("amdgpu-dce-in-ra",
182     cl::init(true), cl::Hidden,
183     cl::desc("Enable machine DCE inside regalloc"));
184 
185 static cl::opt<bool> EnableScalarIRPasses(
186   "amdgpu-scalar-ir-passes",
187   cl::desc("Enable scalar IR passes"),
188   cl::init(true),
189   cl::Hidden);
190 
191 static cl::opt<bool> EnableStructurizerWorkarounds(
192     "amdgpu-enable-structurizer-workarounds",
193     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
194     cl::Hidden);
195 
196 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
197   // Register the target
198   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
199   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
200 
201   PassRegistry *PR = PassRegistry::getPassRegistry();
202   initializeR600ClauseMergePassPass(*PR);
203   initializeR600ControlFlowFinalizerPass(*PR);
204   initializeR600PacketizerPass(*PR);
205   initializeR600ExpandSpecialInstrsPassPass(*PR);
206   initializeR600VectorRegMergerPass(*PR);
207   initializeGlobalISel(*PR);
208   initializeAMDGPUDAGToDAGISelPass(*PR);
209   initializeGCNDPPCombinePass(*PR);
210   initializeSILowerI1CopiesPass(*PR);
211   initializeSILowerSGPRSpillsPass(*PR);
212   initializeSIFixSGPRCopiesPass(*PR);
213   initializeSIFixVGPRCopiesPass(*PR);
214   initializeSIFoldOperandsPass(*PR);
215   initializeSIPeepholeSDWAPass(*PR);
216   initializeSIShrinkInstructionsPass(*PR);
217   initializeSIOptimizeExecMaskingPreRAPass(*PR);
218   initializeSILoadStoreOptimizerPass(*PR);
219   initializeAMDGPUFixFunctionBitcastsPass(*PR);
220   initializeAMDGPUAlwaysInlinePass(*PR);
221   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
222   initializeAMDGPUAnnotateUniformValuesPass(*PR);
223   initializeAMDGPUArgumentUsageInfoPass(*PR);
224   initializeAMDGPUAtomicOptimizerPass(*PR);
225   initializeAMDGPULowerKernelArgumentsPass(*PR);
226   initializeAMDGPULowerKernelAttributesPass(*PR);
227   initializeAMDGPULowerIntrinsicsPass(*PR);
228   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
229   initializeAMDGPUPostLegalizerCombinerPass(*PR);
230   initializeAMDGPUPreLegalizerCombinerPass(*PR);
231   initializeAMDGPURegBankCombinerPass(*PR);
232   initializeAMDGPUPromoteAllocaPass(*PR);
233   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
234   initializeAMDGPUCodeGenPreparePass(*PR);
235   initializeAMDGPULateCodeGenPreparePass(*PR);
236   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
237   initializeAMDGPUPropagateAttributesLatePass(*PR);
238   initializeAMDGPURewriteOutArgumentsPass(*PR);
239   initializeAMDGPUUnifyMetadataPass(*PR);
240   initializeSIAnnotateControlFlowPass(*PR);
241   initializeSIInsertHardClausesPass(*PR);
242   initializeSIInsertWaitcntsPass(*PR);
243   initializeSIModeRegisterPass(*PR);
244   initializeSIWholeQuadModePass(*PR);
245   initializeSILowerControlFlowPass(*PR);
246   initializeSIRemoveShortExecBranchesPass(*PR);
247   initializeSIPreEmitPeepholePass(*PR);
248   initializeSIInsertSkipsPass(*PR);
249   initializeSIMemoryLegalizerPass(*PR);
250   initializeSIOptimizeExecMaskingPass(*PR);
251   initializeSIPreAllocateWWMRegsPass(*PR);
252   initializeSIFormMemoryClausesPass(*PR);
253   initializeSIPostRABundlerPass(*PR);
254   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
255   initializeAMDGPUAAWrapperPassPass(*PR);
256   initializeAMDGPUExternalAAWrapperPass(*PR);
257   initializeAMDGPUUseNativeCallsPass(*PR);
258   initializeAMDGPUSimplifyLibCallsPass(*PR);
259   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
260   initializeGCNRegBankReassignPass(*PR);
261   initializeGCNNSAReassignPass(*PR);
262   initializeSIAddIMGInitPass(*PR);
263 }
264 
265 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
266   return std::make_unique<AMDGPUTargetObjectFile>();
267 }
268 
269 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
270   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
271 }
272 
273 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
274   return new SIScheduleDAGMI(C);
275 }
276 
277 static ScheduleDAGInstrs *
278 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
279   ScheduleDAGMILive *DAG =
280     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
281   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
282   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
283   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
284   return DAG;
285 }
286 
287 static ScheduleDAGInstrs *
288 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
289   auto DAG = new GCNIterativeScheduler(C,
290     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
291   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
292   return DAG;
293 }
294 
295 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
296   return new GCNIterativeScheduler(C,
297     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
298 }
299 
300 static ScheduleDAGInstrs *
301 createIterativeILPMachineScheduler(MachineSchedContext *C) {
302   auto DAG = new GCNIterativeScheduler(C,
303     GCNIterativeScheduler::SCHEDULE_ILP);
304   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
305   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
306   return DAG;
307 }
308 
309 static MachineSchedRegistry
310 R600SchedRegistry("r600", "Run R600's custom scheduler",
311                    createR600MachineScheduler);
312 
313 static MachineSchedRegistry
314 SISchedRegistry("si", "Run SI's custom scheduler",
315                 createSIMachineScheduler);
316 
317 static MachineSchedRegistry
318 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
319                              "Run GCN scheduler to maximize occupancy",
320                              createGCNMaxOccupancyMachineScheduler);
321 
322 static MachineSchedRegistry
323 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
324   "Run GCN scheduler to maximize occupancy (experimental)",
325   createIterativeGCNMaxOccupancyMachineScheduler);
326 
327 static MachineSchedRegistry
328 GCNMinRegSchedRegistry("gcn-minreg",
329   "Run GCN iterative scheduler for minimal register usage (experimental)",
330   createMinRegScheduler);
331 
332 static MachineSchedRegistry
333 GCNILPSchedRegistry("gcn-ilp",
334   "Run GCN iterative scheduler for ILP scheduling (experimental)",
335   createIterativeILPMachineScheduler);
336 
337 static StringRef computeDataLayout(const Triple &TT) {
338   if (TT.getArch() == Triple::r600) {
339     // 32-bit pointers.
340     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
341            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
342   }
343 
344   // 32-bit private, local, and region pointers. 64-bit global, constant and
345   // flat, non-integral buffer fat pointers.
346   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
347          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
348          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
349          "-ni:7";
350 }
351 
352 LLVM_READNONE
353 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
354   if (!GPU.empty())
355     return GPU;
356 
357   // Need to default to a target with flat support for HSA.
358   if (TT.getArch() == Triple::amdgcn)
359     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
360 
361   return "r600";
362 }
363 
364 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
365   // The AMDGPU toolchain only supports generating shared objects, so we
366   // must always use PIC.
367   return Reloc::PIC_;
368 }
369 
370 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
371                                          StringRef CPU, StringRef FS,
372                                          TargetOptions Options,
373                                          Optional<Reloc::Model> RM,
374                                          Optional<CodeModel::Model> CM,
375                                          CodeGenOpt::Level OptLevel)
376     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
377                         FS, Options, getEffectiveRelocModel(RM),
378                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
379       TLOF(createTLOF(getTargetTriple())) {
380   initAsmInfo();
381   if (TT.getArch() == Triple::amdgcn) {
382     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
383       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
384     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
385       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
386   }
387   // Set -fixed-function-abi to true if not provided..
388   if (TT.getOS() == Triple::AMDHSA &&
389       EnableAMDGPUFixedFunctionABIOpt.getNumOccurrences() == 0)
390     EnableFixedFunctionABI = true;
391 }
392 
393 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
394 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
395 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
396 
397 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
398 
399 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
400   Attribute GPUAttr = F.getFnAttribute("target-cpu");
401   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
402 }
403 
404 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
405   Attribute FSAttr = F.getFnAttribute("target-features");
406 
407   return FSAttr.isValid() ? FSAttr.getValueAsString()
408                           : getTargetFeatureString();
409 }
410 
411 /// Predicate for Internalize pass.
412 static bool mustPreserveGV(const GlobalValue &GV) {
413   if (const Function *F = dyn_cast<Function>(&GV))
414     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
415 
416   return !GV.use_empty();
417 }
418 
419 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
420   Builder.DivergentTarget = true;
421 
422   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
423   bool Internalize = InternalizeSymbols;
424   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
425   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
426   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
427 
428   if (EnableFunctionCalls) {
429     delete Builder.Inliner;
430     Builder.Inliner = createFunctionInliningPass();
431   }
432 
433   Builder.addExtension(
434     PassManagerBuilder::EP_ModuleOptimizerEarly,
435     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
436                                                legacy::PassManagerBase &PM) {
437       if (AMDGPUAA) {
438         PM.add(createAMDGPUAAWrapperPass());
439         PM.add(createAMDGPUExternalAAWrapperPass());
440       }
441       PM.add(createAMDGPUUnifyMetadataPass());
442       PM.add(createAMDGPUPrintfRuntimeBinding());
443       if (Internalize)
444         PM.add(createInternalizePass(mustPreserveGV));
445       PM.add(createAMDGPUPropagateAttributesLatePass(this));
446       if (Internalize)
447         PM.add(createGlobalDCEPass());
448       if (EarlyInline)
449         PM.add(createAMDGPUAlwaysInlinePass(false));
450   });
451 
452   Builder.addExtension(
453     PassManagerBuilder::EP_EarlyAsPossible,
454     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
455                                       legacy::PassManagerBase &PM) {
456       if (AMDGPUAA) {
457         PM.add(createAMDGPUAAWrapperPass());
458         PM.add(createAMDGPUExternalAAWrapperPass());
459       }
460       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
461       PM.add(llvm::createAMDGPUUseNativeCallsPass());
462       if (LibCallSimplify)
463         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
464   });
465 
466   Builder.addExtension(
467     PassManagerBuilder::EP_CGSCCOptimizerLate,
468     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
469       // Add infer address spaces pass to the opt pipeline after inlining
470       // but before SROA to increase SROA opportunities.
471       PM.add(createInferAddressSpacesPass());
472 
473       // This should run after inlining to have any chance of doing anything,
474       // and before other cleanup optimizations.
475       PM.add(createAMDGPULowerKernelAttributesPass());
476 
477       // Promote alloca to vector before SROA and loop unroll. If we manage
478       // to eliminate allocas before unroll we may choose to unroll less.
479       if (EnableOpt)
480         PM.add(createAMDGPUPromoteAllocaToVector());
481   });
482 }
483 
484 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
485   AAM.registerFunctionAnalysis<AMDGPUAA>();
486 }
487 
488 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
489                                                        bool DebugPassManager) {
490   PB.registerPipelineParsingCallback(
491       [this](StringRef PassName, ModulePassManager &PM,
492              ArrayRef<PassBuilder::PipelineElement>) {
493         if (PassName == "amdgpu-propagate-attributes-late") {
494           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
495           return true;
496         }
497         if (PassName == "amdgpu-unify-metadata") {
498           PM.addPass(AMDGPUUnifyMetadataPass());
499           return true;
500         }
501         if (PassName == "amdgpu-printf-runtime-binding") {
502           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
503           return true;
504         }
505         if (PassName == "amdgpu-always-inline") {
506           PM.addPass(AMDGPUAlwaysInlinePass());
507           return true;
508         }
509         return false;
510       });
511   PB.registerPipelineParsingCallback(
512       [this](StringRef PassName, FunctionPassManager &PM,
513              ArrayRef<PassBuilder::PipelineElement>) {
514         if (PassName == "amdgpu-simplifylib") {
515           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
516           return true;
517         }
518         if (PassName == "amdgpu-usenative") {
519           PM.addPass(AMDGPUUseNativeCallsPass());
520           return true;
521         }
522         if (PassName == "amdgpu-promote-alloca") {
523           PM.addPass(AMDGPUPromoteAllocaPass(*this));
524           return true;
525         }
526         if (PassName == "amdgpu-promote-alloca-to-vector") {
527           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
528           return true;
529         }
530         if (PassName == "amdgpu-lower-kernel-attributes") {
531           PM.addPass(AMDGPULowerKernelAttributesPass());
532           return true;
533         }
534         if (PassName == "amdgpu-propagate-attributes-early") {
535           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
536           return true;
537         }
538 
539         return false;
540       });
541 
542   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
543     FAM.registerPass([&] { return AMDGPUAA(); });
544   });
545 
546   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
547     if (AAName == "amdgpu-aa") {
548       AAM.registerFunctionAnalysis<AMDGPUAA>();
549       return true;
550     }
551     return false;
552   });
553 
554   PB.registerPipelineStartEPCallback([this, DebugPassManager](
555                                          ModulePassManager &PM,
556                                          PassBuilder::OptimizationLevel Level) {
557     FunctionPassManager FPM(DebugPassManager);
558     FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
559     FPM.addPass(AMDGPUUseNativeCallsPass());
560     if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
561       FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
562     PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
563   });
564 
565   PB.registerPipelineEarlySimplificationEPCallback(
566       [this](ModulePassManager &PM, PassBuilder::OptimizationLevel Level) {
567         if (Level == PassBuilder::OptimizationLevel::O0)
568           return;
569 
570         PM.addPass(AMDGPUUnifyMetadataPass());
571         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
572 
573         if (InternalizeSymbols) {
574           PM.addPass(InternalizePass(mustPreserveGV));
575         }
576         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
577         if (InternalizeSymbols) {
578           PM.addPass(GlobalDCEPass());
579         }
580         if (EarlyInlineAll && !EnableFunctionCalls)
581           PM.addPass(AMDGPUAlwaysInlinePass());
582       });
583 
584   PB.registerCGSCCOptimizerLateEPCallback(
585       [this, DebugPassManager](CGSCCPassManager &PM,
586                                PassBuilder::OptimizationLevel Level) {
587         if (Level == PassBuilder::OptimizationLevel::O0)
588           return;
589 
590         FunctionPassManager FPM(DebugPassManager);
591 
592         // Add infer address spaces pass to the opt pipeline after inlining
593         // but before SROA to increase SROA opportunities.
594         FPM.addPass(InferAddressSpacesPass());
595 
596         // This should run after inlining to have any chance of doing
597         // anything, and before other cleanup optimizations.
598         FPM.addPass(AMDGPULowerKernelAttributesPass());
599 
600         if (Level != PassBuilder::OptimizationLevel::O0) {
601           // Promote alloca to vector before SROA and loop unroll. If we
602           // manage to eliminate allocas before unroll we may choose to unroll
603           // less.
604           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
605         }
606 
607         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
608       });
609 }
610 
611 //===----------------------------------------------------------------------===//
612 // R600 Target Machine (R600 -> Cayman)
613 //===----------------------------------------------------------------------===//
614 
615 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
616                                      StringRef CPU, StringRef FS,
617                                      TargetOptions Options,
618                                      Optional<Reloc::Model> RM,
619                                      Optional<CodeModel::Model> CM,
620                                      CodeGenOpt::Level OL, bool JIT)
621     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
622   setRequiresStructuredCFG(true);
623 
624   // Override the default since calls aren't supported for r600.
625   if (EnableFunctionCalls &&
626       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
627     EnableFunctionCalls = false;
628 }
629 
630 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
631   const Function &F) const {
632   StringRef GPU = getGPUName(F);
633   StringRef FS = getFeatureString(F);
634 
635   SmallString<128> SubtargetKey(GPU);
636   SubtargetKey.append(FS);
637 
638   auto &I = SubtargetMap[SubtargetKey];
639   if (!I) {
640     // This needs to be done before we create a new subtarget since any
641     // creation will depend on the TM and the code generation flags on the
642     // function that reside in TargetOptions.
643     resetTargetOptions(F);
644     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
645   }
646 
647   return I.get();
648 }
649 
650 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
651   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
652           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
653           AddrSpace == AMDGPUAS::REGION_ADDRESS)
654              ? -1
655              : 0;
656 }
657 
658 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
659                                               unsigned DestAS) const {
660   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
661          AMDGPU::isFlatGlobalAddrSpace(DestAS);
662 }
663 
664 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
665   const auto *LD = dyn_cast<LoadInst>(V);
666   if (!LD)
667     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
668 
669   // It must be a generic pointer loaded.
670   assert(V->getType()->isPointerTy() &&
671          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
672 
673   const auto *Ptr = LD->getPointerOperand();
674   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
675     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
676   // For a generic pointer loaded from the constant memory, it could be assumed
677   // as a global pointer since the constant memory is only populated on the
678   // host side. As implied by the offload programming model, only global
679   // pointers could be referenced on the host side.
680   return AMDGPUAS::GLOBAL_ADDRESS;
681 }
682 
683 TargetTransformInfo
684 R600TargetMachine::getTargetTransformInfo(const Function &F) {
685   return TargetTransformInfo(R600TTIImpl(this, F));
686 }
687 
688 //===----------------------------------------------------------------------===//
689 // GCN Target Machine (SI+)
690 //===----------------------------------------------------------------------===//
691 
692 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
693                                    StringRef CPU, StringRef FS,
694                                    TargetOptions Options,
695                                    Optional<Reloc::Model> RM,
696                                    Optional<CodeModel::Model> CM,
697                                    CodeGenOpt::Level OL, bool JIT)
698     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
699 
700 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
701   StringRef GPU = getGPUName(F);
702   StringRef FS = getFeatureString(F);
703 
704   SmallString<128> SubtargetKey(GPU);
705   SubtargetKey.append(FS);
706 
707   auto &I = SubtargetMap[SubtargetKey];
708   if (!I) {
709     // This needs to be done before we create a new subtarget since any
710     // creation will depend on the TM and the code generation flags on the
711     // function that reside in TargetOptions.
712     resetTargetOptions(F);
713     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
714   }
715 
716   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
717 
718   return I.get();
719 }
720 
721 TargetTransformInfo
722 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
723   return TargetTransformInfo(GCNTTIImpl(this, F));
724 }
725 
726 //===----------------------------------------------------------------------===//
727 // AMDGPU Pass Setup
728 //===----------------------------------------------------------------------===//
729 
730 namespace {
731 
732 class AMDGPUPassConfig : public TargetPassConfig {
733 public:
734   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
735     : TargetPassConfig(TM, PM) {
736     // Exceptions and StackMaps are not supported, so these passes will never do
737     // anything.
738     disablePass(&StackMapLivenessID);
739     disablePass(&FuncletLayoutID);
740   }
741 
742   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
743     return getTM<AMDGPUTargetMachine>();
744   }
745 
746   ScheduleDAGInstrs *
747   createMachineScheduler(MachineSchedContext *C) const override {
748     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
749     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
750     return DAG;
751   }
752 
753   void addEarlyCSEOrGVNPass();
754   void addStraightLineScalarOptimizationPasses();
755   void addIRPasses() override;
756   void addCodeGenPrepare() override;
757   bool addPreISel() override;
758   bool addInstSelector() override;
759   bool addGCPasses() override;
760 
761   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
762 };
763 
764 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
765   return getStandardCSEConfigForOpt(TM->getOptLevel());
766 }
767 
768 class R600PassConfig final : public AMDGPUPassConfig {
769 public:
770   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
771     : AMDGPUPassConfig(TM, PM) {}
772 
773   ScheduleDAGInstrs *createMachineScheduler(
774     MachineSchedContext *C) const override {
775     return createR600MachineScheduler(C);
776   }
777 
778   bool addPreISel() override;
779   bool addInstSelector() override;
780   void addPreRegAlloc() override;
781   void addPreSched2() override;
782   void addPreEmitPass() override;
783 };
784 
785 class GCNPassConfig final : public AMDGPUPassConfig {
786 public:
787   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
788     : AMDGPUPassConfig(TM, PM) {
789     // It is necessary to know the register usage of the entire call graph.  We
790     // allow calls without EnableAMDGPUFunctionCalls if they are marked
791     // noinline, so this is always required.
792     setRequiresCodeGenSCCOrder(true);
793   }
794 
795   GCNTargetMachine &getGCNTargetMachine() const {
796     return getTM<GCNTargetMachine>();
797   }
798 
799   ScheduleDAGInstrs *
800   createMachineScheduler(MachineSchedContext *C) const override;
801 
802   bool addPreISel() override;
803   void addMachineSSAOptimization() override;
804   bool addILPOpts() override;
805   bool addInstSelector() override;
806   bool addIRTranslator() override;
807   void addPreLegalizeMachineIR() override;
808   bool addLegalizeMachineIR() override;
809   void addPreRegBankSelect() override;
810   bool addRegBankSelect() override;
811   void addPreGlobalInstructionSelect() override;
812   bool addGlobalInstructionSelect() override;
813   void addFastRegAlloc() override;
814   void addOptimizedRegAlloc() override;
815   void addPreRegAlloc() override;
816   bool addPreRewrite() override;
817   void addPostRegAlloc() override;
818   void addPreSched2() override;
819   void addPreEmitPass() override;
820 };
821 
822 } // end anonymous namespace
823 
824 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
825   if (getOptLevel() == CodeGenOpt::Aggressive)
826     addPass(createGVNPass());
827   else
828     addPass(createEarlyCSEPass());
829 }
830 
831 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
832   addPass(createLICMPass());
833   addPass(createSeparateConstOffsetFromGEPPass());
834   addPass(createSpeculativeExecutionPass());
835   // ReassociateGEPs exposes more opportunites for SLSR. See
836   // the example in reassociate-geps-and-slsr.ll.
837   addPass(createStraightLineStrengthReducePass());
838   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
839   // EarlyCSE can reuse.
840   addEarlyCSEOrGVNPass();
841   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
842   addPass(createNaryReassociatePass());
843   // NaryReassociate on GEPs creates redundant common expressions, so run
844   // EarlyCSE after it.
845   addPass(createEarlyCSEPass());
846 }
847 
848 void AMDGPUPassConfig::addIRPasses() {
849   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
850 
851   // There is no reason to run these.
852   disablePass(&StackMapLivenessID);
853   disablePass(&FuncletLayoutID);
854   disablePass(&PatchableFunctionID);
855 
856   addPass(createAMDGPUPrintfRuntimeBinding());
857 
858   // This must occur before inlining, as the inliner will not look through
859   // bitcast calls.
860   addPass(createAMDGPUFixFunctionBitcastsPass());
861 
862   // A call to propagate attributes pass in the backend in case opt was not run.
863   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
864 
865   addPass(createAtomicExpandPass());
866 
867 
868   addPass(createAMDGPULowerIntrinsicsPass());
869 
870   // Function calls are not supported, so make sure we inline everything.
871   addPass(createAMDGPUAlwaysInlinePass());
872   addPass(createAlwaysInlinerLegacyPass());
873   // We need to add the barrier noop pass, otherwise adding the function
874   // inlining pass will cause all of the PassConfigs passes to be run
875   // one function at a time, which means if we have a nodule with two
876   // functions, then we will generate code for the first function
877   // without ever running any passes on the second.
878   addPass(createBarrierNoopPass());
879 
880   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
881   if (TM.getTargetTriple().getArch() == Triple::r600)
882     addPass(createR600OpenCLImageTypeLoweringPass());
883 
884   // Replace OpenCL enqueued block function pointers with global variables.
885   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
886 
887   if (TM.getOptLevel() > CodeGenOpt::None) {
888     addPass(createInferAddressSpacesPass());
889     addPass(createAMDGPUPromoteAlloca());
890 
891     if (EnableSROA)
892       addPass(createSROAPass());
893 
894     if (EnableScalarIRPasses)
895       addStraightLineScalarOptimizationPasses();
896 
897     if (EnableAMDGPUAliasAnalysis) {
898       addPass(createAMDGPUAAWrapperPass());
899       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
900                                              AAResults &AAR) {
901         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
902           AAR.addAAResult(WrapperPass->getResult());
903         }));
904     }
905   }
906 
907   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
908     // TODO: May want to move later or split into an early and late one.
909     addPass(createAMDGPUCodeGenPreparePass());
910   }
911 
912   TargetPassConfig::addIRPasses();
913 
914   // EarlyCSE is not always strong enough to clean up what LSR produces. For
915   // example, GVN can combine
916   //
917   //   %0 = add %a, %b
918   //   %1 = add %b, %a
919   //
920   // and
921   //
922   //   %0 = shl nsw %a, 2
923   //   %1 = shl %a, 2
924   //
925   // but EarlyCSE can do neither of them.
926   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
927     addEarlyCSEOrGVNPass();
928 }
929 
930 void AMDGPUPassConfig::addCodeGenPrepare() {
931   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
932     addPass(createAMDGPUAnnotateKernelFeaturesPass());
933 
934   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
935       EnableLowerKernelArguments)
936     addPass(createAMDGPULowerKernelArgumentsPass());
937 
938   addPass(&AMDGPUPerfHintAnalysisID);
939 
940   TargetPassConfig::addCodeGenPrepare();
941 
942   if (EnableLoadStoreVectorizer)
943     addPass(createLoadStoreVectorizerPass());
944 
945   // LowerSwitch pass may introduce unreachable blocks that can
946   // cause unexpected behavior for subsequent passes. Placing it
947   // here seems better that these blocks would get cleaned up by
948   // UnreachableBlockElim inserted next in the pass flow.
949   addPass(createLowerSwitchPass());
950 }
951 
952 bool AMDGPUPassConfig::addPreISel() {
953   addPass(createFlattenCFGPass());
954   return false;
955 }
956 
957 bool AMDGPUPassConfig::addInstSelector() {
958   // Defer the verifier until FinalizeISel.
959   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
960   return false;
961 }
962 
963 bool AMDGPUPassConfig::addGCPasses() {
964   // Do nothing. GC is not supported.
965   return false;
966 }
967 
968 //===----------------------------------------------------------------------===//
969 // R600 Pass Setup
970 //===----------------------------------------------------------------------===//
971 
972 bool R600PassConfig::addPreISel() {
973   AMDGPUPassConfig::addPreISel();
974 
975   if (EnableR600StructurizeCFG)
976     addPass(createStructurizeCFGPass());
977   return false;
978 }
979 
980 bool R600PassConfig::addInstSelector() {
981   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
982   return false;
983 }
984 
985 void R600PassConfig::addPreRegAlloc() {
986   addPass(createR600VectorRegMerger());
987 }
988 
989 void R600PassConfig::addPreSched2() {
990   addPass(createR600EmitClauseMarkers(), false);
991   if (EnableR600IfConvert)
992     addPass(&IfConverterID, false);
993   addPass(createR600ClauseMergePass(), false);
994 }
995 
996 void R600PassConfig::addPreEmitPass() {
997   addPass(createAMDGPUCFGStructurizerPass(), false);
998   addPass(createR600ExpandSpecialInstrsPass(), false);
999   addPass(&FinalizeMachineBundlesID, false);
1000   addPass(createR600Packetizer(), false);
1001   addPass(createR600ControlFlowFinalizer(), false);
1002 }
1003 
1004 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
1005   return new R600PassConfig(*this, PM);
1006 }
1007 
1008 //===----------------------------------------------------------------------===//
1009 // GCN Pass Setup
1010 //===----------------------------------------------------------------------===//
1011 
1012 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1013   MachineSchedContext *C) const {
1014   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1015   if (ST.enableSIScheduler())
1016     return createSIMachineScheduler(C);
1017   return createGCNMaxOccupancyMachineScheduler(C);
1018 }
1019 
1020 bool GCNPassConfig::addPreISel() {
1021   AMDGPUPassConfig::addPreISel();
1022 
1023   addPass(createAMDGPULateCodeGenPreparePass());
1024   if (EnableAtomicOptimizations) {
1025     addPass(createAMDGPUAtomicOptimizerPass());
1026   }
1027 
1028   // FIXME: We need to run a pass to propagate the attributes when calls are
1029   // supported.
1030 
1031   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1032   // regions formed by them.
1033   addPass(&AMDGPUUnifyDivergentExitNodesID);
1034   if (!LateCFGStructurize) {
1035     if (EnableStructurizerWorkarounds) {
1036       addPass(createFixIrreduciblePass());
1037       addPass(createUnifyLoopExitsPass());
1038     }
1039     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1040   }
1041   addPass(createSinkingPass());
1042   addPass(createAMDGPUAnnotateUniformValues());
1043   if (!LateCFGStructurize) {
1044     addPass(createSIAnnotateControlFlowPass());
1045   }
1046   addPass(createLCSSAPass());
1047 
1048   return false;
1049 }
1050 
1051 void GCNPassConfig::addMachineSSAOptimization() {
1052   TargetPassConfig::addMachineSSAOptimization();
1053 
1054   // We want to fold operands after PeepholeOptimizer has run (or as part of
1055   // it), because it will eliminate extra copies making it easier to fold the
1056   // real source operand. We want to eliminate dead instructions after, so that
1057   // we see fewer uses of the copies. We then need to clean up the dead
1058   // instructions leftover after the operands are folded as well.
1059   //
1060   // XXX - Can we get away without running DeadMachineInstructionElim again?
1061   addPass(&SIFoldOperandsID);
1062   if (EnableDPPCombine)
1063     addPass(&GCNDPPCombineID);
1064   addPass(&DeadMachineInstructionElimID);
1065   addPass(&SILoadStoreOptimizerID);
1066   if (EnableSDWAPeephole) {
1067     addPass(&SIPeepholeSDWAID);
1068     addPass(&EarlyMachineLICMID);
1069     addPass(&MachineCSEID);
1070     addPass(&SIFoldOperandsID);
1071     addPass(&DeadMachineInstructionElimID);
1072   }
1073   addPass(createSIShrinkInstructionsPass());
1074 }
1075 
1076 bool GCNPassConfig::addILPOpts() {
1077   if (EnableEarlyIfConversion)
1078     addPass(&EarlyIfConverterID);
1079 
1080   TargetPassConfig::addILPOpts();
1081   return false;
1082 }
1083 
1084 bool GCNPassConfig::addInstSelector() {
1085   AMDGPUPassConfig::addInstSelector();
1086   addPass(&SIFixSGPRCopiesID);
1087   addPass(createSILowerI1CopiesPass());
1088   addPass(createSIAddIMGInitPass());
1089   return false;
1090 }
1091 
1092 bool GCNPassConfig::addIRTranslator() {
1093   addPass(new IRTranslator(getOptLevel()));
1094   return false;
1095 }
1096 
1097 void GCNPassConfig::addPreLegalizeMachineIR() {
1098   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1099   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1100   addPass(new Localizer());
1101 }
1102 
1103 bool GCNPassConfig::addLegalizeMachineIR() {
1104   addPass(new Legalizer());
1105   return false;
1106 }
1107 
1108 void GCNPassConfig::addPreRegBankSelect() {
1109   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1110   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1111 }
1112 
1113 bool GCNPassConfig::addRegBankSelect() {
1114   addPass(new RegBankSelect());
1115   return false;
1116 }
1117 
1118 void GCNPassConfig::addPreGlobalInstructionSelect() {
1119   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1120   addPass(createAMDGPURegBankCombiner(IsOptNone));
1121 }
1122 
1123 bool GCNPassConfig::addGlobalInstructionSelect() {
1124   addPass(new InstructionSelect(getOptLevel()));
1125   // TODO: Fix instruction selection to do the right thing for image
1126   // instructions with tfe or lwe in the first place, instead of running a
1127   // separate pass to fix them up?
1128   addPass(createSIAddIMGInitPass());
1129   return false;
1130 }
1131 
1132 void GCNPassConfig::addPreRegAlloc() {
1133   if (LateCFGStructurize) {
1134     addPass(createAMDGPUMachineCFGStructurizerPass());
1135   }
1136 }
1137 
1138 void GCNPassConfig::addFastRegAlloc() {
1139   // FIXME: We have to disable the verifier here because of PHIElimination +
1140   // TwoAddressInstructions disabling it.
1141 
1142   // This must be run immediately after phi elimination and before
1143   // TwoAddressInstructions, otherwise the processing of the tied operand of
1144   // SI_ELSE will introduce a copy of the tied operand source after the else.
1145   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1146 
1147   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1148   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1149 
1150   TargetPassConfig::addFastRegAlloc();
1151 }
1152 
1153 void GCNPassConfig::addOptimizedRegAlloc() {
1154   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1155   // instructions that cause scheduling barriers.
1156   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1157   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1158 
1159   if (OptExecMaskPreRA)
1160     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1161   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1162 
1163   // This must be run immediately after phi elimination and before
1164   // TwoAddressInstructions, otherwise the processing of the tied operand of
1165   // SI_ELSE will introduce a copy of the tied operand source after the else.
1166   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1167 
1168   if (EnableDCEInRA)
1169     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1170 
1171   TargetPassConfig::addOptimizedRegAlloc();
1172 }
1173 
1174 bool GCNPassConfig::addPreRewrite() {
1175   if (EnableRegReassign) {
1176     addPass(&GCNNSAReassignID);
1177     addPass(&GCNRegBankReassignID);
1178   }
1179   return true;
1180 }
1181 
1182 void GCNPassConfig::addPostRegAlloc() {
1183   addPass(&SIFixVGPRCopiesID);
1184   if (getOptLevel() > CodeGenOpt::None)
1185     addPass(&SIOptimizeExecMaskingID);
1186   TargetPassConfig::addPostRegAlloc();
1187 
1188   // Equivalent of PEI for SGPRs.
1189   addPass(&SILowerSGPRSpillsID);
1190 }
1191 
1192 void GCNPassConfig::addPreSched2() {
1193   addPass(&SIPostRABundlerID);
1194 }
1195 
1196 void GCNPassConfig::addPreEmitPass() {
1197   addPass(createSIMemoryLegalizerPass());
1198   addPass(createSIInsertWaitcntsPass());
1199   addPass(createSIShrinkInstructionsPass());
1200   addPass(createSIModeRegisterPass());
1201 
1202   if (getOptLevel() > CodeGenOpt::None)
1203     addPass(&SIInsertHardClausesID);
1204 
1205   addPass(&SIRemoveShortExecBranchesID);
1206   addPass(&SIInsertSkipsPassID);
1207   addPass(&SIPreEmitPeepholeID);
1208   // The hazard recognizer that runs as part of the post-ra scheduler does not
1209   // guarantee to be able handle all hazards correctly. This is because if there
1210   // are multiple scheduling regions in a basic block, the regions are scheduled
1211   // bottom up, so when we begin to schedule a region we don't know what
1212   // instructions were emitted directly before it.
1213   //
1214   // Here we add a stand-alone hazard recognizer pass which can handle all
1215   // cases.
1216   addPass(&PostRAHazardRecognizerID);
1217   addPass(&BranchRelaxationPassID);
1218 }
1219 
1220 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1221   return new GCNPassConfig(*this, PM);
1222 }
1223 
1224 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1225   return new yaml::SIMachineFunctionInfo();
1226 }
1227 
1228 yaml::MachineFunctionInfo *
1229 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1230   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1231   return new yaml::SIMachineFunctionInfo(*MFI,
1232                                          *MF.getSubtarget().getRegisterInfo());
1233 }
1234 
1235 bool GCNTargetMachine::parseMachineFunctionInfo(
1236     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1237     SMDiagnostic &Error, SMRange &SourceRange) const {
1238   const yaml::SIMachineFunctionInfo &YamlMFI =
1239       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1240   MachineFunction &MF = PFS.MF;
1241   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1242 
1243   MFI->initializeBaseYamlFields(YamlMFI);
1244 
1245   if (MFI->Occupancy == 0) {
1246     // Fixup the subtarget dependent default value.
1247     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1248     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1249   }
1250 
1251   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1252     Register TempReg;
1253     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1254       SourceRange = RegName.SourceRange;
1255       return true;
1256     }
1257     RegVal = TempReg;
1258 
1259     return false;
1260   };
1261 
1262   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1263     // Create a diagnostic for a the register string literal.
1264     const MemoryBuffer &Buffer =
1265         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1266     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1267                          RegName.Value.size(), SourceMgr::DK_Error,
1268                          "incorrect register class for field", RegName.Value,
1269                          None, None);
1270     SourceRange = RegName.SourceRange;
1271     return true;
1272   };
1273 
1274   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1275       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1276       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1277     return true;
1278 
1279   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1280       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1281     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1282   }
1283 
1284   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1285       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1286     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1287   }
1288 
1289   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1290       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1291     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1292   }
1293 
1294   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1295                                    const TargetRegisterClass &RC,
1296                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1297                                    unsigned SystemSGPRs) {
1298     // Skip parsing if it's not present.
1299     if (!A)
1300       return false;
1301 
1302     if (A->IsRegister) {
1303       Register Reg;
1304       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1305         SourceRange = A->RegisterName.SourceRange;
1306         return true;
1307       }
1308       if (!RC.contains(Reg))
1309         return diagnoseRegisterClass(A->RegisterName);
1310       Arg = ArgDescriptor::createRegister(Reg);
1311     } else
1312       Arg = ArgDescriptor::createStack(A->StackOffset);
1313     // Check and apply the optional mask.
1314     if (A->Mask)
1315       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1316 
1317     MFI->NumUserSGPRs += UserSGPRs;
1318     MFI->NumSystemSGPRs += SystemSGPRs;
1319     return false;
1320   };
1321 
1322   if (YamlMFI.ArgInfo &&
1323       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1324                              AMDGPU::SGPR_128RegClass,
1325                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1326        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1327                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1328                              2, 0) ||
1329        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1330                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1331        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1332                              AMDGPU::SReg_64RegClass,
1333                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1334        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1335                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1336                              2, 0) ||
1337        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1338                              AMDGPU::SReg_64RegClass,
1339                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1340        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1341                              AMDGPU::SGPR_32RegClass,
1342                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1343        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1344                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1345                              0, 1) ||
1346        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1347                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1348                              0, 1) ||
1349        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1350                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1351                              0, 1) ||
1352        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1353                              AMDGPU::SGPR_32RegClass,
1354                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1355        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1356                              AMDGPU::SGPR_32RegClass,
1357                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1358        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1359                              AMDGPU::SReg_64RegClass,
1360                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1361        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1362                              AMDGPU::SReg_64RegClass,
1363                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1364        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1365                              AMDGPU::VGPR_32RegClass,
1366                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1367        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1368                              AMDGPU::VGPR_32RegClass,
1369                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1370        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1371                              AMDGPU::VGPR_32RegClass,
1372                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1373     return true;
1374 
1375   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1376   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1377   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1378   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1379   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1380   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1381 
1382   return false;
1383 }
1384