1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUExportClustering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
28 #include "R600MachineScheduler.h"
29 #include "SIMachineFunctionInfo.h"
30 #include "SIMachineScheduler.h"
31 #include "TargetInfo/AMDGPUTargetInfo.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
35 #include "llvm/CodeGen/GlobalISel/Localizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MIRParser/MIParser.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/LegacyPassManager.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/Pass.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Transforms/IPO.h"
50 #include "llvm/Transforms/IPO/AlwaysInliner.h"
51 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
52 #include "llvm/Transforms/Scalar.h"
53 #include "llvm/Transforms/Scalar/GVN.h"
54 #include "llvm/Transforms/Utils.h"
55 #include "llvm/Transforms/Vectorize.h"
56 #include <memory>
57 
58 using namespace llvm;
59 
60 static cl::opt<bool> EnableR600StructurizeCFG(
61   "r600-ir-structurize",
62   cl::desc("Use StructurizeCFG IR pass"),
63   cl::init(true));
64 
65 static cl::opt<bool> EnableSROA(
66   "amdgpu-sroa",
67   cl::desc("Run SROA after promote alloca pass"),
68   cl::ReallyHidden,
69   cl::init(true));
70 
71 static cl::opt<bool>
72 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
73                         cl::desc("Run early if-conversion"),
74                         cl::init(false));
75 
76 static cl::opt<bool>
77 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
78             cl::desc("Run pre-RA exec mask optimizations"),
79             cl::init(true));
80 
81 static cl::opt<bool> EnableR600IfConvert(
82   "r600-if-convert",
83   cl::desc("Use if conversion pass"),
84   cl::ReallyHidden,
85   cl::init(true));
86 
87 // Option to disable vectorizer for tests.
88 static cl::opt<bool> EnableLoadStoreVectorizer(
89   "amdgpu-load-store-vectorizer",
90   cl::desc("Enable load store vectorizer"),
91   cl::init(true),
92   cl::Hidden);
93 
94 // Option to control global loads scalarization
95 static cl::opt<bool> ScalarizeGlobal(
96   "amdgpu-scalarize-global-loads",
97   cl::desc("Enable global load scalarization"),
98   cl::init(true),
99   cl::Hidden);
100 
101 // Option to run internalize pass.
102 static cl::opt<bool> InternalizeSymbols(
103   "amdgpu-internalize-symbols",
104   cl::desc("Enable elimination of non-kernel functions and unused globals"),
105   cl::init(false),
106   cl::Hidden);
107 
108 // Option to inline all early.
109 static cl::opt<bool> EarlyInlineAll(
110   "amdgpu-early-inline-all",
111   cl::desc("Inline all functions early"),
112   cl::init(false),
113   cl::Hidden);
114 
115 static cl::opt<bool> EnableSDWAPeephole(
116   "amdgpu-sdwa-peephole",
117   cl::desc("Enable SDWA peepholer"),
118   cl::init(true));
119 
120 static cl::opt<bool> EnableDPPCombine(
121   "amdgpu-dpp-combine",
122   cl::desc("Enable DPP combiner"),
123   cl::init(true));
124 
125 // Enable address space based alias analysis
126 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
127   cl::desc("Enable AMDGPU Alias Analysis"),
128   cl::init(true));
129 
130 // Option to run late CFG structurizer
131 static cl::opt<bool, true> LateCFGStructurize(
132   "amdgpu-late-structurize",
133   cl::desc("Enable late CFG structurization"),
134   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
135   cl::Hidden);
136 
137 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
138   "amdgpu-function-calls",
139   cl::desc("Enable AMDGPU function call support"),
140   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
141   cl::init(true),
142   cl::Hidden);
143 
144 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
145   "amdgpu-fixed-function-abi",
146   cl::desc("Enable all implicit function arguments"),
147   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
148   cl::init(false),
149   cl::Hidden);
150 
151 // Enable lib calls simplifications
152 static cl::opt<bool> EnableLibCallSimplify(
153   "amdgpu-simplify-libcall",
154   cl::desc("Enable amdgpu library simplifications"),
155   cl::init(true),
156   cl::Hidden);
157 
158 static cl::opt<bool> EnableLowerKernelArguments(
159   "amdgpu-ir-lower-kernel-arguments",
160   cl::desc("Lower kernel argument loads in IR pass"),
161   cl::init(true),
162   cl::Hidden);
163 
164 static cl::opt<bool> EnableRegReassign(
165   "amdgpu-reassign-regs",
166   cl::desc("Enable register reassign optimizations on gfx10+"),
167   cl::init(true),
168   cl::Hidden);
169 
170 // Enable atomic optimization
171 static cl::opt<bool> EnableAtomicOptimizations(
172   "amdgpu-atomic-optimizations",
173   cl::desc("Enable atomic optimizations"),
174   cl::init(false),
175   cl::Hidden);
176 
177 // Enable Mode register optimization
178 static cl::opt<bool> EnableSIModeRegisterPass(
179   "amdgpu-mode-register",
180   cl::desc("Enable mode register pass"),
181   cl::init(true),
182   cl::Hidden);
183 
184 // Option is used in lit tests to prevent deadcoding of patterns inspected.
185 static cl::opt<bool>
186 EnableDCEInRA("amdgpu-dce-in-ra",
187     cl::init(true), cl::Hidden,
188     cl::desc("Enable machine DCE inside regalloc"));
189 
190 static cl::opt<bool> EnableScalarIRPasses(
191   "amdgpu-scalar-ir-passes",
192   cl::desc("Enable scalar IR passes"),
193   cl::init(true),
194   cl::Hidden);
195 
196 static cl::opt<bool> EnableStructurizerWorkarounds(
197     "amdgpu-enable-structurizer-workarounds",
198     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(false),
199     cl::Hidden);
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFixupVectorISelPass(*PR);
220   initializeSIFoldOperandsPass(*PR);
221   initializeSIPeepholeSDWAPass(*PR);
222   initializeSIShrinkInstructionsPass(*PR);
223   initializeSIOptimizeExecMaskingPreRAPass(*PR);
224   initializeSILoadStoreOptimizerPass(*PR);
225   initializeAMDGPUFixFunctionBitcastsPass(*PR);
226   initializeAMDGPUAlwaysInlinePass(*PR);
227   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
228   initializeAMDGPUAnnotateUniformValuesPass(*PR);
229   initializeAMDGPUArgumentUsageInfoPass(*PR);
230   initializeAMDGPUAtomicOptimizerPass(*PR);
231   initializeAMDGPULowerKernelArgumentsPass(*PR);
232   initializeAMDGPULowerKernelAttributesPass(*PR);
233   initializeAMDGPULowerIntrinsicsPass(*PR);
234   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
235   initializeAMDGPUPostLegalizerCombinerPass(*PR);
236   initializeAMDGPUPreLegalizerCombinerPass(*PR);
237   initializeAMDGPUPromoteAllocaPass(*PR);
238   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
239   initializeAMDGPUCodeGenPreparePass(*PR);
240   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
241   initializeAMDGPUPropagateAttributesLatePass(*PR);
242   initializeAMDGPURewriteOutArgumentsPass(*PR);
243   initializeAMDGPUUnifyMetadataPass(*PR);
244   initializeSIAnnotateControlFlowPass(*PR);
245   initializeSIInsertHardClausesPass(*PR);
246   initializeSIInsertWaitcntsPass(*PR);
247   initializeSIModeRegisterPass(*PR);
248   initializeSIWholeQuadModePass(*PR);
249   initializeSILowerControlFlowPass(*PR);
250   initializeSIRemoveShortExecBranchesPass(*PR);
251   initializeSIPreEmitPeepholePass(*PR);
252   initializeSIInsertSkipsPass(*PR);
253   initializeSIMemoryLegalizerPass(*PR);
254   initializeSIOptimizeExecMaskingPass(*PR);
255   initializeSIPreAllocateWWMRegsPass(*PR);
256   initializeSIFormMemoryClausesPass(*PR);
257   initializeSIPostRABundlerPass(*PR);
258   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
259   initializeAMDGPUAAWrapperPassPass(*PR);
260   initializeAMDGPUExternalAAWrapperPass(*PR);
261   initializeAMDGPUUseNativeCallsPass(*PR);
262   initializeAMDGPUSimplifyLibCallsPass(*PR);
263   initializeAMDGPUInlinerPass(*PR);
264   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
265   initializeGCNRegBankReassignPass(*PR);
266   initializeGCNNSAReassignPass(*PR);
267   initializeSIAddIMGInitPass(*PR);
268 }
269 
270 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
271   return std::make_unique<AMDGPUTargetObjectFile>();
272 }
273 
274 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
275   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
276 }
277 
278 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
279   return new SIScheduleDAGMI(C);
280 }
281 
282 static ScheduleDAGInstrs *
283 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
284   ScheduleDAGMILive *DAG =
285     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
286   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
287   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
288   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
289   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
290   return DAG;
291 }
292 
293 static ScheduleDAGInstrs *
294 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
295   auto DAG = new GCNIterativeScheduler(C,
296     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
297   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
298   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
299   return DAG;
300 }
301 
302 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
303   return new GCNIterativeScheduler(C,
304     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
305 }
306 
307 static ScheduleDAGInstrs *
308 createIterativeILPMachineScheduler(MachineSchedContext *C) {
309   auto DAG = new GCNIterativeScheduler(C,
310     GCNIterativeScheduler::SCHEDULE_ILP);
311   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
312   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
313   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
314   return DAG;
315 }
316 
317 static MachineSchedRegistry
318 R600SchedRegistry("r600", "Run R600's custom scheduler",
319                    createR600MachineScheduler);
320 
321 static MachineSchedRegistry
322 SISchedRegistry("si", "Run SI's custom scheduler",
323                 createSIMachineScheduler);
324 
325 static MachineSchedRegistry
326 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
327                              "Run GCN scheduler to maximize occupancy",
328                              createGCNMaxOccupancyMachineScheduler);
329 
330 static MachineSchedRegistry
331 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
332   "Run GCN scheduler to maximize occupancy (experimental)",
333   createIterativeGCNMaxOccupancyMachineScheduler);
334 
335 static MachineSchedRegistry
336 GCNMinRegSchedRegistry("gcn-minreg",
337   "Run GCN iterative scheduler for minimal register usage (experimental)",
338   createMinRegScheduler);
339 
340 static MachineSchedRegistry
341 GCNILPSchedRegistry("gcn-ilp",
342   "Run GCN iterative scheduler for ILP scheduling (experimental)",
343   createIterativeILPMachineScheduler);
344 
345 static StringRef computeDataLayout(const Triple &TT) {
346   if (TT.getArch() == Triple::r600) {
347     // 32-bit pointers.
348       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
349              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
350   }
351 
352   // 32-bit private, local, and region pointers. 64-bit global, constant and
353   // flat, non-integral buffer fat pointers.
354     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
355          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
356          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
357          "-ni:7";
358 }
359 
360 LLVM_READNONE
361 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
362   if (!GPU.empty())
363     return GPU;
364 
365   // Need to default to a target with flat support for HSA.
366   if (TT.getArch() == Triple::amdgcn)
367     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
368 
369   return "r600";
370 }
371 
372 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
373   // The AMDGPU toolchain only supports generating shared objects, so we
374   // must always use PIC.
375   return Reloc::PIC_;
376 }
377 
378 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
379                                          StringRef CPU, StringRef FS,
380                                          TargetOptions Options,
381                                          Optional<Reloc::Model> RM,
382                                          Optional<CodeModel::Model> CM,
383                                          CodeGenOpt::Level OptLevel)
384     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
385                         FS, Options, getEffectiveRelocModel(RM),
386                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
387       TLOF(createTLOF(getTargetTriple())) {
388   initAsmInfo();
389   if (TT.getArch() == Triple::amdgcn) {
390     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
391       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
392     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
393       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
394   }
395 }
396 
397 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
398 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
399 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
400 
401 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
402 
403 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
404   Attribute GPUAttr = F.getFnAttribute("target-cpu");
405   return GPUAttr.hasAttribute(Attribute::None) ?
406     getTargetCPU() : GPUAttr.getValueAsString();
407 }
408 
409 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
410   Attribute FSAttr = F.getFnAttribute("target-features");
411 
412   return FSAttr.hasAttribute(Attribute::None) ?
413     getTargetFeatureString() :
414     FSAttr.getValueAsString();
415 }
416 
417 /// Predicate for Internalize pass.
418 static bool mustPreserveGV(const GlobalValue &GV) {
419   if (const Function *F = dyn_cast<Function>(&GV))
420     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
421 
422   return !GV.use_empty();
423 }
424 
425 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
426   Builder.DivergentTarget = true;
427 
428   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
429   bool Internalize = InternalizeSymbols;
430   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
431   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
432   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
433 
434   if (EnableFunctionCalls) {
435     delete Builder.Inliner;
436     Builder.Inliner = createAMDGPUFunctionInliningPass();
437   }
438 
439   Builder.addExtension(
440     PassManagerBuilder::EP_ModuleOptimizerEarly,
441     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
442                                                legacy::PassManagerBase &PM) {
443       if (AMDGPUAA) {
444         PM.add(createAMDGPUAAWrapperPass());
445         PM.add(createAMDGPUExternalAAWrapperPass());
446       }
447       PM.add(createAMDGPUUnifyMetadataPass());
448       PM.add(createAMDGPUPrintfRuntimeBinding());
449       if (Internalize)
450         PM.add(createInternalizePass(mustPreserveGV));
451       PM.add(createAMDGPUPropagateAttributesLatePass(this));
452       if (Internalize)
453         PM.add(createGlobalDCEPass());
454       if (EarlyInline)
455         PM.add(createAMDGPUAlwaysInlinePass(false));
456   });
457 
458   Builder.addExtension(
459     PassManagerBuilder::EP_EarlyAsPossible,
460     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
461                                       legacy::PassManagerBase &PM) {
462       if (AMDGPUAA) {
463         PM.add(createAMDGPUAAWrapperPass());
464         PM.add(createAMDGPUExternalAAWrapperPass());
465       }
466       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
467       PM.add(llvm::createAMDGPUUseNativeCallsPass());
468       if (LibCallSimplify)
469         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
470   });
471 
472   Builder.addExtension(
473     PassManagerBuilder::EP_CGSCCOptimizerLate,
474     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
475       // Add infer address spaces pass to the opt pipeline after inlining
476       // but before SROA to increase SROA opportunities.
477       PM.add(createInferAddressSpacesPass());
478 
479       // This should run after inlining to have any chance of doing anything,
480       // and before other cleanup optimizations.
481       PM.add(createAMDGPULowerKernelAttributesPass());
482 
483       // Promote alloca to vector before SROA and loop unroll. If we manage
484       // to eliminate allocas before unroll we may choose to unroll less.
485       if (EnableOpt)
486         PM.add(createAMDGPUPromoteAllocaToVector());
487   });
488 }
489 
490 //===----------------------------------------------------------------------===//
491 // R600 Target Machine (R600 -> Cayman)
492 //===----------------------------------------------------------------------===//
493 
494 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
495                                      StringRef CPU, StringRef FS,
496                                      TargetOptions Options,
497                                      Optional<Reloc::Model> RM,
498                                      Optional<CodeModel::Model> CM,
499                                      CodeGenOpt::Level OL, bool JIT)
500     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
501   setRequiresStructuredCFG(true);
502 
503   // Override the default since calls aren't supported for r600.
504   if (EnableFunctionCalls &&
505       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
506     EnableFunctionCalls = false;
507 }
508 
509 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
510   const Function &F) const {
511   StringRef GPU = getGPUName(F);
512   StringRef FS = getFeatureString(F);
513 
514   SmallString<128> SubtargetKey(GPU);
515   SubtargetKey.append(FS);
516 
517   auto &I = SubtargetMap[SubtargetKey];
518   if (!I) {
519     // This needs to be done before we create a new subtarget since any
520     // creation will depend on the TM and the code generation flags on the
521     // function that reside in TargetOptions.
522     resetTargetOptions(F);
523     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
524   }
525 
526   return I.get();
527 }
528 
529 TargetTransformInfo
530 R600TargetMachine::getTargetTransformInfo(const Function &F) {
531   return TargetTransformInfo(R600TTIImpl(this, F));
532 }
533 
534 //===----------------------------------------------------------------------===//
535 // GCN Target Machine (SI+)
536 //===----------------------------------------------------------------------===//
537 
538 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
539                                    StringRef CPU, StringRef FS,
540                                    TargetOptions Options,
541                                    Optional<Reloc::Model> RM,
542                                    Optional<CodeModel::Model> CM,
543                                    CodeGenOpt::Level OL, bool JIT)
544     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
545 
546 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
547   StringRef GPU = getGPUName(F);
548   StringRef FS = getFeatureString(F);
549 
550   SmallString<128> SubtargetKey(GPU);
551   SubtargetKey.append(FS);
552 
553   auto &I = SubtargetMap[SubtargetKey];
554   if (!I) {
555     // This needs to be done before we create a new subtarget since any
556     // creation will depend on the TM and the code generation flags on the
557     // function that reside in TargetOptions.
558     resetTargetOptions(F);
559     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
560   }
561 
562   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
563 
564   return I.get();
565 }
566 
567 TargetTransformInfo
568 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
569   return TargetTransformInfo(GCNTTIImpl(this, F));
570 }
571 
572 //===----------------------------------------------------------------------===//
573 // AMDGPU Pass Setup
574 //===----------------------------------------------------------------------===//
575 
576 namespace {
577 
578 class AMDGPUPassConfig : public TargetPassConfig {
579 public:
580   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
581     : TargetPassConfig(TM, PM) {
582     // Exceptions and StackMaps are not supported, so these passes will never do
583     // anything.
584     disablePass(&StackMapLivenessID);
585     disablePass(&FuncletLayoutID);
586   }
587 
588   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
589     return getTM<AMDGPUTargetMachine>();
590   }
591 
592   ScheduleDAGInstrs *
593   createMachineScheduler(MachineSchedContext *C) const override {
594     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
595     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
596     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
597     return DAG;
598   }
599 
600   void addEarlyCSEOrGVNPass();
601   void addStraightLineScalarOptimizationPasses();
602   void addIRPasses() override;
603   void addCodeGenPrepare() override;
604   bool addPreISel() override;
605   bool addInstSelector() override;
606   bool addGCPasses() override;
607 
608   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
609 };
610 
611 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
612   return getStandardCSEConfigForOpt(TM->getOptLevel());
613 }
614 
615 class R600PassConfig final : public AMDGPUPassConfig {
616 public:
617   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
618     : AMDGPUPassConfig(TM, PM) {}
619 
620   ScheduleDAGInstrs *createMachineScheduler(
621     MachineSchedContext *C) const override {
622     return createR600MachineScheduler(C);
623   }
624 
625   bool addPreISel() override;
626   bool addInstSelector() override;
627   void addPreRegAlloc() override;
628   void addPreSched2() override;
629   void addPreEmitPass() override;
630 };
631 
632 class GCNPassConfig final : public AMDGPUPassConfig {
633 public:
634   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
635     : AMDGPUPassConfig(TM, PM) {
636     // It is necessary to know the register usage of the entire call graph.  We
637     // allow calls without EnableAMDGPUFunctionCalls if they are marked
638     // noinline, so this is always required.
639     setRequiresCodeGenSCCOrder(true);
640   }
641 
642   GCNTargetMachine &getGCNTargetMachine() const {
643     return getTM<GCNTargetMachine>();
644   }
645 
646   ScheduleDAGInstrs *
647   createMachineScheduler(MachineSchedContext *C) const override;
648 
649   bool addPreISel() override;
650   void addMachineSSAOptimization() override;
651   bool addILPOpts() override;
652   bool addInstSelector() override;
653   bool addIRTranslator() override;
654   void addPreLegalizeMachineIR() override;
655   bool addLegalizeMachineIR() override;
656   void addPreRegBankSelect() override;
657   bool addRegBankSelect() override;
658   bool addGlobalInstructionSelect() override;
659   void addFastRegAlloc() override;
660   void addOptimizedRegAlloc() override;
661   void addPreRegAlloc() override;
662   bool addPreRewrite() override;
663   void addPostRegAlloc() override;
664   void addPreSched2() override;
665   void addPreEmitPass() override;
666 };
667 
668 } // end anonymous namespace
669 
670 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
671   if (getOptLevel() == CodeGenOpt::Aggressive)
672     addPass(createGVNPass());
673   else
674     addPass(createEarlyCSEPass());
675 }
676 
677 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
678   addPass(createLICMPass());
679   addPass(createSeparateConstOffsetFromGEPPass());
680   addPass(createSpeculativeExecutionPass());
681   // ReassociateGEPs exposes more opportunites for SLSR. See
682   // the example in reassociate-geps-and-slsr.ll.
683   addPass(createStraightLineStrengthReducePass());
684   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
685   // EarlyCSE can reuse.
686   addEarlyCSEOrGVNPass();
687   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
688   addPass(createNaryReassociatePass());
689   // NaryReassociate on GEPs creates redundant common expressions, so run
690   // EarlyCSE after it.
691   addPass(createEarlyCSEPass());
692 }
693 
694 void AMDGPUPassConfig::addIRPasses() {
695   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
696 
697   // There is no reason to run these.
698   disablePass(&StackMapLivenessID);
699   disablePass(&FuncletLayoutID);
700   disablePass(&PatchableFunctionID);
701 
702   addPass(createAMDGPUPrintfRuntimeBinding());
703 
704   // This must occur before inlining, as the inliner will not look through
705   // bitcast calls.
706   addPass(createAMDGPUFixFunctionBitcastsPass());
707 
708   // A call to propagate attributes pass in the backend in case opt was not run.
709   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
710 
711   addPass(createAtomicExpandPass());
712 
713 
714   addPass(createAMDGPULowerIntrinsicsPass());
715 
716   // Function calls are not supported, so make sure we inline everything.
717   addPass(createAMDGPUAlwaysInlinePass());
718   addPass(createAlwaysInlinerLegacyPass());
719   // We need to add the barrier noop pass, otherwise adding the function
720   // inlining pass will cause all of the PassConfigs passes to be run
721   // one function at a time, which means if we have a nodule with two
722   // functions, then we will generate code for the first function
723   // without ever running any passes on the second.
724   addPass(createBarrierNoopPass());
725 
726   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
727   if (TM.getTargetTriple().getArch() == Triple::r600)
728     addPass(createR600OpenCLImageTypeLoweringPass());
729 
730   // Replace OpenCL enqueued block function pointers with global variables.
731   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
732 
733   if (TM.getOptLevel() > CodeGenOpt::None) {
734     addPass(createInferAddressSpacesPass());
735     addPass(createAMDGPUPromoteAlloca());
736 
737     if (EnableSROA)
738       addPass(createSROAPass());
739 
740     if (EnableScalarIRPasses)
741       addStraightLineScalarOptimizationPasses();
742 
743     if (EnableAMDGPUAliasAnalysis) {
744       addPass(createAMDGPUAAWrapperPass());
745       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
746                                              AAResults &AAR) {
747         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
748           AAR.addAAResult(WrapperPass->getResult());
749         }));
750     }
751   }
752 
753   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
754     // TODO: May want to move later or split into an early and late one.
755     addPass(createAMDGPUCodeGenPreparePass());
756   }
757 
758   TargetPassConfig::addIRPasses();
759 
760   // EarlyCSE is not always strong enough to clean up what LSR produces. For
761   // example, GVN can combine
762   //
763   //   %0 = add %a, %b
764   //   %1 = add %b, %a
765   //
766   // and
767   //
768   //   %0 = shl nsw %a, 2
769   //   %1 = shl %a, 2
770   //
771   // but EarlyCSE can do neither of them.
772   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
773     addEarlyCSEOrGVNPass();
774 }
775 
776 void AMDGPUPassConfig::addCodeGenPrepare() {
777   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
778     addPass(createAMDGPUAnnotateKernelFeaturesPass());
779 
780   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
781       EnableLowerKernelArguments)
782     addPass(createAMDGPULowerKernelArgumentsPass());
783 
784   addPass(&AMDGPUPerfHintAnalysisID);
785 
786   TargetPassConfig::addCodeGenPrepare();
787 
788   if (EnableLoadStoreVectorizer)
789     addPass(createLoadStoreVectorizerPass());
790 }
791 
792 bool AMDGPUPassConfig::addPreISel() {
793   addPass(createLowerSwitchPass());
794   addPass(createFlattenCFGPass());
795   return false;
796 }
797 
798 bool AMDGPUPassConfig::addInstSelector() {
799   // Defer the verifier until FinalizeISel.
800   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
801   return false;
802 }
803 
804 bool AMDGPUPassConfig::addGCPasses() {
805   // Do nothing. GC is not supported.
806   return false;
807 }
808 
809 //===----------------------------------------------------------------------===//
810 // R600 Pass Setup
811 //===----------------------------------------------------------------------===//
812 
813 bool R600PassConfig::addPreISel() {
814   AMDGPUPassConfig::addPreISel();
815 
816   if (EnableR600StructurizeCFG)
817     addPass(createStructurizeCFGPass());
818   return false;
819 }
820 
821 bool R600PassConfig::addInstSelector() {
822   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
823   return false;
824 }
825 
826 void R600PassConfig::addPreRegAlloc() {
827   addPass(createR600VectorRegMerger());
828 }
829 
830 void R600PassConfig::addPreSched2() {
831   addPass(createR600EmitClauseMarkers(), false);
832   if (EnableR600IfConvert)
833     addPass(&IfConverterID, false);
834   addPass(createR600ClauseMergePass(), false);
835 }
836 
837 void R600PassConfig::addPreEmitPass() {
838   addPass(createAMDGPUCFGStructurizerPass(), false);
839   addPass(createR600ExpandSpecialInstrsPass(), false);
840   addPass(&FinalizeMachineBundlesID, false);
841   addPass(createR600Packetizer(), false);
842   addPass(createR600ControlFlowFinalizer(), false);
843 }
844 
845 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
846   return new R600PassConfig(*this, PM);
847 }
848 
849 //===----------------------------------------------------------------------===//
850 // GCN Pass Setup
851 //===----------------------------------------------------------------------===//
852 
853 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
854   MachineSchedContext *C) const {
855   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
856   if (ST.enableSIScheduler())
857     return createSIMachineScheduler(C);
858   return createGCNMaxOccupancyMachineScheduler(C);
859 }
860 
861 bool GCNPassConfig::addPreISel() {
862   AMDGPUPassConfig::addPreISel();
863 
864   if (EnableAtomicOptimizations) {
865     addPass(createAMDGPUAtomicOptimizerPass());
866   }
867 
868   // FIXME: We need to run a pass to propagate the attributes when calls are
869   // supported.
870 
871   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
872   // regions formed by them.
873   addPass(&AMDGPUUnifyDivergentExitNodesID);
874   if (!LateCFGStructurize) {
875     if (EnableStructurizerWorkarounds) {
876       addPass(createFixIrreduciblePass());
877       addPass(createUnifyLoopExitsPass());
878     }
879     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
880   }
881   addPass(createSinkingPass());
882   addPass(createAMDGPUAnnotateUniformValues());
883   if (!LateCFGStructurize) {
884     addPass(createSIAnnotateControlFlowPass());
885   }
886   addPass(createLCSSAPass());
887 
888   return false;
889 }
890 
891 void GCNPassConfig::addMachineSSAOptimization() {
892   TargetPassConfig::addMachineSSAOptimization();
893 
894   // We want to fold operands after PeepholeOptimizer has run (or as part of
895   // it), because it will eliminate extra copies making it easier to fold the
896   // real source operand. We want to eliminate dead instructions after, so that
897   // we see fewer uses of the copies. We then need to clean up the dead
898   // instructions leftover after the operands are folded as well.
899   //
900   // XXX - Can we get away without running DeadMachineInstructionElim again?
901   addPass(&SIFoldOperandsID);
902   if (EnableDPPCombine)
903     addPass(&GCNDPPCombineID);
904   addPass(&DeadMachineInstructionElimID);
905   addPass(&SILoadStoreOptimizerID);
906   if (EnableSDWAPeephole) {
907     addPass(&SIPeepholeSDWAID);
908     addPass(&EarlyMachineLICMID);
909     addPass(&MachineCSEID);
910     addPass(&SIFoldOperandsID);
911     addPass(&DeadMachineInstructionElimID);
912   }
913   addPass(createSIShrinkInstructionsPass());
914 }
915 
916 bool GCNPassConfig::addILPOpts() {
917   if (EnableEarlyIfConversion)
918     addPass(&EarlyIfConverterID);
919 
920   TargetPassConfig::addILPOpts();
921   return false;
922 }
923 
924 bool GCNPassConfig::addInstSelector() {
925   AMDGPUPassConfig::addInstSelector();
926   addPass(&SIFixSGPRCopiesID);
927   addPass(createSILowerI1CopiesPass());
928   // TODO: We have to add FinalizeISel
929   // to expand V_ADD/SUB_U64_PSEUDO before SIFixupVectorISel
930   // that expects V_ADD/SUB -> A_ADDC/SUBB pairs expanded.
931   // Will be removed as soon as SIFixupVectorISel is changed
932   // to work with V_ADD/SUB_U64_PSEUDO instead.
933   addPass(&FinalizeISelID);
934   addPass(createSIFixupVectorISelPass());
935   addPass(createSIAddIMGInitPass());
936   return false;
937 }
938 
939 bool GCNPassConfig::addIRTranslator() {
940   addPass(new IRTranslator());
941   return false;
942 }
943 
944 void GCNPassConfig::addPreLegalizeMachineIR() {
945   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
946   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
947   addPass(new Localizer());
948 }
949 
950 bool GCNPassConfig::addLegalizeMachineIR() {
951   addPass(new Legalizer());
952   return false;
953 }
954 
955 void GCNPassConfig::addPreRegBankSelect() {
956   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
957   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
958 }
959 
960 bool GCNPassConfig::addRegBankSelect() {
961   addPass(new RegBankSelect());
962   return false;
963 }
964 
965 bool GCNPassConfig::addGlobalInstructionSelect() {
966   addPass(new InstructionSelect());
967   return false;
968 }
969 
970 void GCNPassConfig::addPreRegAlloc() {
971   if (LateCFGStructurize) {
972     addPass(createAMDGPUMachineCFGStructurizerPass());
973   }
974   addPass(createSIWholeQuadModePass());
975 }
976 
977 void GCNPassConfig::addFastRegAlloc() {
978   // FIXME: We have to disable the verifier here because of PHIElimination +
979   // TwoAddressInstructions disabling it.
980 
981   // This must be run immediately after phi elimination and before
982   // TwoAddressInstructions, otherwise the processing of the tied operand of
983   // SI_ELSE will introduce a copy of the tied operand source after the else.
984   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
985 
986   // This must be run just after RegisterCoalescing.
987   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
988 
989   TargetPassConfig::addFastRegAlloc();
990 }
991 
992 void GCNPassConfig::addOptimizedRegAlloc() {
993   if (OptExecMaskPreRA) {
994     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
995     insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
996   } else {
997     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
998   }
999 
1000   // This must be run immediately after phi elimination and before
1001   // TwoAddressInstructions, otherwise the processing of the tied operand of
1002   // SI_ELSE will introduce a copy of the tied operand source after the else.
1003   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1004 
1005   // This must be run just after RegisterCoalescing.
1006   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
1007 
1008   if (EnableDCEInRA)
1009     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1010 
1011   TargetPassConfig::addOptimizedRegAlloc();
1012 }
1013 
1014 bool GCNPassConfig::addPreRewrite() {
1015   if (EnableRegReassign) {
1016     addPass(&GCNNSAReassignID);
1017     addPass(&GCNRegBankReassignID);
1018   }
1019   return true;
1020 }
1021 
1022 void GCNPassConfig::addPostRegAlloc() {
1023   addPass(&SIFixVGPRCopiesID);
1024   if (getOptLevel() > CodeGenOpt::None)
1025     addPass(&SIOptimizeExecMaskingID);
1026   TargetPassConfig::addPostRegAlloc();
1027 
1028   // Equivalent of PEI for SGPRs.
1029   addPass(&SILowerSGPRSpillsID);
1030 }
1031 
1032 void GCNPassConfig::addPreSched2() {
1033   addPass(&SIPostRABundlerID);
1034 }
1035 
1036 void GCNPassConfig::addPreEmitPass() {
1037   addPass(createSIMemoryLegalizerPass());
1038   addPass(createSIInsertWaitcntsPass());
1039   addPass(createSIShrinkInstructionsPass());
1040   addPass(createSIModeRegisterPass());
1041 
1042   // The hazard recognizer that runs as part of the post-ra scheduler does not
1043   // guarantee to be able handle all hazards correctly. This is because if there
1044   // are multiple scheduling regions in a basic block, the regions are scheduled
1045   // bottom up, so when we begin to schedule a region we don't know what
1046   // instructions were emitted directly before it.
1047   //
1048   // Here we add a stand-alone hazard recognizer pass which can handle all
1049   // cases.
1050   //
1051   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
1052   // be better for it to emit S_NOP <N> when possible.
1053   addPass(&PostRAHazardRecognizerID);
1054   if (getOptLevel() > CodeGenOpt::None)
1055     addPass(&SIInsertHardClausesID);
1056 
1057   addPass(&SIRemoveShortExecBranchesID);
1058   addPass(&SIPreEmitPeepholeID);
1059   addPass(&SIInsertSkipsPassID);
1060   addPass(&BranchRelaxationPassID);
1061 }
1062 
1063 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1064   return new GCNPassConfig(*this, PM);
1065 }
1066 
1067 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1068   return new yaml::SIMachineFunctionInfo();
1069 }
1070 
1071 yaml::MachineFunctionInfo *
1072 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1073   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1074   return new yaml::SIMachineFunctionInfo(*MFI,
1075                                          *MF.getSubtarget().getRegisterInfo());
1076 }
1077 
1078 bool GCNTargetMachine::parseMachineFunctionInfo(
1079     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1080     SMDiagnostic &Error, SMRange &SourceRange) const {
1081   const yaml::SIMachineFunctionInfo &YamlMFI =
1082       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1083   MachineFunction &MF = PFS.MF;
1084   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1085 
1086   MFI->initializeBaseYamlFields(YamlMFI);
1087 
1088   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1089     Register TempReg;
1090     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1091       SourceRange = RegName.SourceRange;
1092       return true;
1093     }
1094     RegVal = TempReg;
1095 
1096     return false;
1097   };
1098 
1099   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1100     // Create a diagnostic for a the register string literal.
1101     const MemoryBuffer &Buffer =
1102         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1103     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1104                          RegName.Value.size(), SourceMgr::DK_Error,
1105                          "incorrect register class for field", RegName.Value,
1106                          None, None);
1107     SourceRange = RegName.SourceRange;
1108     return true;
1109   };
1110 
1111   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1112       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1113       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1114     return true;
1115 
1116   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1117       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1118     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1119   }
1120 
1121   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1122       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1123     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1124   }
1125 
1126   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1127       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1128     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1129   }
1130 
1131   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1132                                    const TargetRegisterClass &RC,
1133                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1134                                    unsigned SystemSGPRs) {
1135     // Skip parsing if it's not present.
1136     if (!A)
1137       return false;
1138 
1139     if (A->IsRegister) {
1140       Register Reg;
1141       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1142         SourceRange = A->RegisterName.SourceRange;
1143         return true;
1144       }
1145       if (!RC.contains(Reg))
1146         return diagnoseRegisterClass(A->RegisterName);
1147       Arg = ArgDescriptor::createRegister(Reg);
1148     } else
1149       Arg = ArgDescriptor::createStack(A->StackOffset);
1150     // Check and apply the optional mask.
1151     if (A->Mask)
1152       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1153 
1154     MFI->NumUserSGPRs += UserSGPRs;
1155     MFI->NumSystemSGPRs += SystemSGPRs;
1156     return false;
1157   };
1158 
1159   if (YamlMFI.ArgInfo &&
1160       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1161                              AMDGPU::SGPR_128RegClass,
1162                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1163        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1164                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1165                              2, 0) ||
1166        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1167                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1168        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1169                              AMDGPU::SReg_64RegClass,
1170                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1171        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1172                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1173                              2, 0) ||
1174        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1175                              AMDGPU::SReg_64RegClass,
1176                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1177        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1178                              AMDGPU::SGPR_32RegClass,
1179                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1180        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1181                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1182                              0, 1) ||
1183        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1184                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1185                              0, 1) ||
1186        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1187                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1188                              0, 1) ||
1189        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1190                              AMDGPU::SGPR_32RegClass,
1191                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1192        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1193                              AMDGPU::SGPR_32RegClass,
1194                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1195        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1196                              AMDGPU::SReg_64RegClass,
1197                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1198        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1199                              AMDGPU::SReg_64RegClass,
1200                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1201        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1202                              AMDGPU::VGPR_32RegClass,
1203                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1204        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1205                              AMDGPU::VGPR_32RegClass,
1206                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1207        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1208                              AMDGPU::VGPR_32RegClass,
1209                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1210     return true;
1211 
1212   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1213   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1214   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1215   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1216   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1217   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1218 
1219   return false;
1220 }
1221