1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110   cl::desc("Enable AMDGPU Alias Analysis"),
111   cl::init(true));
112 
113 // Option to run late CFG structurizer
114 static cl::opt<bool, true> LateCFGStructurize(
115   "amdgpu-late-structurize",
116   cl::desc("Enable late CFG structurization"),
117   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
118   cl::Hidden);
119 
120 static cl::opt<bool> EnableAMDGPUFunctionCalls(
121   "amdgpu-function-calls",
122   cl::Hidden,
123   cl::desc("Enable AMDGPU function call support"),
124   cl::init(false));
125 
126 // Enable lib calls simplifications
127 static cl::opt<bool> EnableLibCallSimplify(
128   "amdgpu-simplify-libcall",
129   cl::desc("Enable mdgpu library simplifications"),
130   cl::init(true),
131   cl::Hidden);
132 
133 extern "C" void LLVMInitializeAMDGPUTarget() {
134   // Register the target
135   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
136   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
137 
138   PassRegistry *PR = PassRegistry::getPassRegistry();
139   initializeR600ClauseMergePassPass(*PR);
140   initializeR600ControlFlowFinalizerPass(*PR);
141   initializeR600PacketizerPass(*PR);
142   initializeR600ExpandSpecialInstrsPassPass(*PR);
143   initializeR600VectorRegMergerPass(*PR);
144   initializeGlobalISel(*PR);
145   initializeAMDGPUDAGToDAGISelPass(*PR);
146   initializeSILowerI1CopiesPass(*PR);
147   initializeSIFixSGPRCopiesPass(*PR);
148   initializeSIFixVGPRCopiesPass(*PR);
149   initializeSIFoldOperandsPass(*PR);
150   initializeSIPeepholeSDWAPass(*PR);
151   initializeSIShrinkInstructionsPass(*PR);
152   initializeSIOptimizeExecMaskingPreRAPass(*PR);
153   initializeSILoadStoreOptimizerPass(*PR);
154   initializeAMDGPUAlwaysInlinePass(*PR);
155   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
156   initializeAMDGPUAnnotateUniformValuesPass(*PR);
157   initializeAMDGPUArgumentUsageInfoPass(*PR);
158   initializeAMDGPULowerKernelAttributesPass(*PR);
159   initializeAMDGPULowerIntrinsicsPass(*PR);
160   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
161   initializeAMDGPUPromoteAllocaPass(*PR);
162   initializeAMDGPUCodeGenPreparePass(*PR);
163   initializeAMDGPURewriteOutArgumentsPass(*PR);
164   initializeAMDGPUUnifyMetadataPass(*PR);
165   initializeSIAnnotateControlFlowPass(*PR);
166   initializeSIInsertWaitcntsPass(*PR);
167   initializeSIWholeQuadModePass(*PR);
168   initializeSILowerControlFlowPass(*PR);
169   initializeSIInsertSkipsPass(*PR);
170   initializeSIMemoryLegalizerPass(*PR);
171   initializeSIDebuggerInsertNopsPass(*PR);
172   initializeSIOptimizeExecMaskingPass(*PR);
173   initializeSIFixWWMLivenessPass(*PR);
174   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
175   initializeAMDGPUAAWrapperPassPass(*PR);
176   initializeAMDGPUUseNativeCallsPass(*PR);
177   initializeAMDGPUSimplifyLibCallsPass(*PR);
178   initializeAMDGPUInlinerPass(*PR);
179 }
180 
181 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
182   return llvm::make_unique<AMDGPUTargetObjectFile>();
183 }
184 
185 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
186   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
187 }
188 
189 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
190   return new SIScheduleDAGMI(C);
191 }
192 
193 static ScheduleDAGInstrs *
194 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
195   ScheduleDAGMILive *DAG =
196     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
197   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
198   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
199   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
200   return DAG;
201 }
202 
203 static ScheduleDAGInstrs *
204 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
205   auto DAG = new GCNIterativeScheduler(C,
206     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
207   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
208   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
209   return DAG;
210 }
211 
212 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
213   return new GCNIterativeScheduler(C,
214     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
215 }
216 
217 static ScheduleDAGInstrs *
218 createIterativeILPMachineScheduler(MachineSchedContext *C) {
219   auto DAG = new GCNIterativeScheduler(C,
220     GCNIterativeScheduler::SCHEDULE_ILP);
221   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
222   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
223   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
224   return DAG;
225 }
226 
227 static MachineSchedRegistry
228 R600SchedRegistry("r600", "Run R600's custom scheduler",
229                    createR600MachineScheduler);
230 
231 static MachineSchedRegistry
232 SISchedRegistry("si", "Run SI's custom scheduler",
233                 createSIMachineScheduler);
234 
235 static MachineSchedRegistry
236 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
237                              "Run GCN scheduler to maximize occupancy",
238                              createGCNMaxOccupancyMachineScheduler);
239 
240 static MachineSchedRegistry
241 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
242   "Run GCN scheduler to maximize occupancy (experimental)",
243   createIterativeGCNMaxOccupancyMachineScheduler);
244 
245 static MachineSchedRegistry
246 GCNMinRegSchedRegistry("gcn-minreg",
247   "Run GCN iterative scheduler for minimal register usage (experimental)",
248   createMinRegScheduler);
249 
250 static MachineSchedRegistry
251 GCNILPSchedRegistry("gcn-ilp",
252   "Run GCN iterative scheduler for ILP scheduling (experimental)",
253   createIterativeILPMachineScheduler);
254 
255 static StringRef computeDataLayout(const Triple &TT) {
256   if (TT.getArch() == Triple::r600) {
257     // 32-bit pointers.
258       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
259              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
260   }
261 
262   // 32-bit private, local, and region pointers. 64-bit global, constant and
263   // flat.
264     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
265          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
266          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
267 }
268 
269 LLVM_READNONE
270 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
271   if (!GPU.empty())
272     return GPU;
273 
274   if (TT.getArch() == Triple::amdgcn)
275     return "generic";
276 
277   return "r600";
278 }
279 
280 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
281   // The AMDGPU toolchain only supports generating shared objects, so we
282   // must always use PIC.
283   return Reloc::PIC_;
284 }
285 
286 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
287   if (CM)
288     return *CM;
289   return CodeModel::Small;
290 }
291 
292 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
293                                          StringRef CPU, StringRef FS,
294                                          TargetOptions Options,
295                                          Optional<Reloc::Model> RM,
296                                          Optional<CodeModel::Model> CM,
297                                          CodeGenOpt::Level OptLevel)
298     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
299                         FS, Options, getEffectiveRelocModel(RM),
300                         getEffectiveCodeModel(CM), OptLevel),
301       TLOF(createTLOF(getTargetTriple())) {
302   AS = AMDGPU::getAMDGPUAS(TT);
303   initAsmInfo();
304 }
305 
306 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
307 
308 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
309 
310 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
311   Attribute GPUAttr = F.getFnAttribute("target-cpu");
312   return GPUAttr.hasAttribute(Attribute::None) ?
313     getTargetCPU() : GPUAttr.getValueAsString();
314 }
315 
316 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
317   Attribute FSAttr = F.getFnAttribute("target-features");
318 
319   return FSAttr.hasAttribute(Attribute::None) ?
320     getTargetFeatureString() :
321     FSAttr.getValueAsString();
322 }
323 
324 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
325   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
326       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
327         AAR.addAAResult(WrapperPass->getResult());
328       });
329 }
330 
331 /// Predicate for Internalize pass.
332 static bool mustPreserveGV(const GlobalValue &GV) {
333   if (const Function *F = dyn_cast<Function>(&GV))
334     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
335 
336   return !GV.use_empty();
337 }
338 
339 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
340   Builder.DivergentTarget = true;
341 
342   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
343   bool Internalize = InternalizeSymbols;
344   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
345   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
346   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
347 
348   if (EnableAMDGPUFunctionCalls) {
349     delete Builder.Inliner;
350     Builder.Inliner = createAMDGPUFunctionInliningPass();
351   }
352 
353   if (Internalize) {
354     // If we're generating code, we always have the whole program available. The
355     // relocations expected for externally visible functions aren't supported,
356     // so make sure every non-entry function is hidden.
357     Builder.addExtension(
358       PassManagerBuilder::EP_EnabledOnOptLevel0,
359       [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
360         PM.add(createInternalizePass(mustPreserveGV));
361       });
362   }
363 
364   Builder.addExtension(
365     PassManagerBuilder::EP_ModuleOptimizerEarly,
366     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
367                                          legacy::PassManagerBase &PM) {
368       if (AMDGPUAA) {
369         PM.add(createAMDGPUAAWrapperPass());
370         PM.add(createAMDGPUExternalAAWrapperPass());
371       }
372       PM.add(createAMDGPUUnifyMetadataPass());
373       if (Internalize) {
374         PM.add(createInternalizePass(mustPreserveGV));
375         PM.add(createGlobalDCEPass());
376       }
377       if (EarlyInline)
378         PM.add(createAMDGPUAlwaysInlinePass(false));
379   });
380 
381   const auto &Opt = Options;
382   Builder.addExtension(
383     PassManagerBuilder::EP_EarlyAsPossible,
384     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
385                                       legacy::PassManagerBase &PM) {
386       if (AMDGPUAA) {
387         PM.add(createAMDGPUAAWrapperPass());
388         PM.add(createAMDGPUExternalAAWrapperPass());
389       }
390       PM.add(llvm::createAMDGPUUseNativeCallsPass());
391       if (LibCallSimplify)
392         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
393   });
394 
395   Builder.addExtension(
396     PassManagerBuilder::EP_CGSCCOptimizerLate,
397     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
398       // Add infer address spaces pass to the opt pipeline after inlining
399       // but before SROA to increase SROA opportunities.
400       PM.add(createInferAddressSpacesPass());
401 
402       // This should run after inlining to have any chance of doing anything,
403       // and before other cleanup optimizations.
404       PM.add(createAMDGPULowerKernelAttributesPass());
405   });
406 }
407 
408 //===----------------------------------------------------------------------===//
409 // R600 Target Machine (R600 -> Cayman)
410 //===----------------------------------------------------------------------===//
411 
412 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
413                                      StringRef CPU, StringRef FS,
414                                      TargetOptions Options,
415                                      Optional<Reloc::Model> RM,
416                                      Optional<CodeModel::Model> CM,
417                                      CodeGenOpt::Level OL, bool JIT)
418     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
419   setRequiresStructuredCFG(true);
420 }
421 
422 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
423   const Function &F) const {
424   StringRef GPU = getGPUName(F);
425   StringRef FS = getFeatureString(F);
426 
427   SmallString<128> SubtargetKey(GPU);
428   SubtargetKey.append(FS);
429 
430   auto &I = SubtargetMap[SubtargetKey];
431   if (!I) {
432     // This needs to be done before we create a new subtarget since any
433     // creation will depend on the TM and the code generation flags on the
434     // function that reside in TargetOptions.
435     resetTargetOptions(F);
436     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
437   }
438 
439   return I.get();
440 }
441 
442 //===----------------------------------------------------------------------===//
443 // GCN Target Machine (SI+)
444 //===----------------------------------------------------------------------===//
445 
446 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
447                                    StringRef CPU, StringRef FS,
448                                    TargetOptions Options,
449                                    Optional<Reloc::Model> RM,
450                                    Optional<CodeModel::Model> CM,
451                                    CodeGenOpt::Level OL, bool JIT)
452     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
453 
454 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
455   StringRef GPU = getGPUName(F);
456   StringRef FS = getFeatureString(F);
457 
458   SmallString<128> SubtargetKey(GPU);
459   SubtargetKey.append(FS);
460 
461   auto &I = SubtargetMap[SubtargetKey];
462   if (!I) {
463     // This needs to be done before we create a new subtarget since any
464     // creation will depend on the TM and the code generation flags on the
465     // function that reside in TargetOptions.
466     resetTargetOptions(F);
467     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
468   }
469 
470   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
471 
472   return I.get();
473 }
474 
475 //===----------------------------------------------------------------------===//
476 // AMDGPU Pass Setup
477 //===----------------------------------------------------------------------===//
478 
479 namespace {
480 
481 class AMDGPUPassConfig : public TargetPassConfig {
482 public:
483   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
484     : TargetPassConfig(TM, PM) {
485     // Exceptions and StackMaps are not supported, so these passes will never do
486     // anything.
487     disablePass(&StackMapLivenessID);
488     disablePass(&FuncletLayoutID);
489   }
490 
491   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
492     return getTM<AMDGPUTargetMachine>();
493   }
494 
495   ScheduleDAGInstrs *
496   createMachineScheduler(MachineSchedContext *C) const override {
497     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
498     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
499     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
500     return DAG;
501   }
502 
503   void addEarlyCSEOrGVNPass();
504   void addStraightLineScalarOptimizationPasses();
505   void addIRPasses() override;
506   void addCodeGenPrepare() override;
507   bool addPreISel() override;
508   bool addInstSelector() override;
509   bool addGCPasses() override;
510 };
511 
512 class R600PassConfig final : public AMDGPUPassConfig {
513 public:
514   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
515     : AMDGPUPassConfig(TM, PM) {}
516 
517   ScheduleDAGInstrs *createMachineScheduler(
518     MachineSchedContext *C) const override {
519     return createR600MachineScheduler(C);
520   }
521 
522   bool addPreISel() override;
523   bool addInstSelector() override;
524   void addPreRegAlloc() override;
525   void addPreSched2() override;
526   void addPreEmitPass() override;
527 };
528 
529 class GCNPassConfig final : public AMDGPUPassConfig {
530 public:
531   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
532     : AMDGPUPassConfig(TM, PM) {
533     // It is necessary to know the register usage of the entire call graph.  We
534     // allow calls without EnableAMDGPUFunctionCalls if they are marked
535     // noinline, so this is always required.
536     setRequiresCodeGenSCCOrder(true);
537   }
538 
539   GCNTargetMachine &getGCNTargetMachine() const {
540     return getTM<GCNTargetMachine>();
541   }
542 
543   ScheduleDAGInstrs *
544   createMachineScheduler(MachineSchedContext *C) const override;
545 
546   bool addPreISel() override;
547   void addMachineSSAOptimization() override;
548   bool addILPOpts() override;
549   bool addInstSelector() override;
550   bool addIRTranslator() override;
551   bool addLegalizeMachineIR() override;
552   bool addRegBankSelect() override;
553   bool addGlobalInstructionSelect() override;
554   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
555   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
556   void addPreRegAlloc() override;
557   void addPostRegAlloc() override;
558   void addPreSched2() override;
559   void addPreEmitPass() override;
560 };
561 
562 } // end anonymous namespace
563 
564 TargetTransformInfo
565 AMDGPUTargetMachine::getTargetTransformInfo(const Function &F) {
566   return TargetTransformInfo(AMDGPUTTIImpl(this, F));
567 }
568 
569 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
570   if (getOptLevel() == CodeGenOpt::Aggressive)
571     addPass(createGVNPass());
572   else
573     addPass(createEarlyCSEPass());
574 }
575 
576 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
577   addPass(createSeparateConstOffsetFromGEPPass());
578   addPass(createSpeculativeExecutionPass());
579   // ReassociateGEPs exposes more opportunites for SLSR. See
580   // the example in reassociate-geps-and-slsr.ll.
581   addPass(createStraightLineStrengthReducePass());
582   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
583   // EarlyCSE can reuse.
584   addEarlyCSEOrGVNPass();
585   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
586   addPass(createNaryReassociatePass());
587   // NaryReassociate on GEPs creates redundant common expressions, so run
588   // EarlyCSE after it.
589   addPass(createEarlyCSEPass());
590 }
591 
592 void AMDGPUPassConfig::addIRPasses() {
593   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
594 
595   // There is no reason to run these.
596   disablePass(&StackMapLivenessID);
597   disablePass(&FuncletLayoutID);
598   disablePass(&PatchableFunctionID);
599 
600   addPass(createAMDGPULowerIntrinsicsPass());
601 
602   if (TM.getTargetTriple().getArch() == Triple::r600 ||
603       !EnableAMDGPUFunctionCalls) {
604     // Function calls are not supported, so make sure we inline everything.
605     addPass(createAMDGPUAlwaysInlinePass());
606     addPass(createAlwaysInlinerLegacyPass());
607     // We need to add the barrier noop pass, otherwise adding the function
608     // inlining pass will cause all of the PassConfigs passes to be run
609     // one function at a time, which means if we have a nodule with two
610     // functions, then we will generate code for the first function
611     // without ever running any passes on the second.
612     addPass(createBarrierNoopPass());
613   }
614 
615   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
616     // TODO: May want to move later or split into an early and late one.
617 
618     addPass(createAMDGPUCodeGenPreparePass());
619   }
620 
621   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
622   if (TM.getTargetTriple().getArch() == Triple::r600)
623     addPass(createR600OpenCLImageTypeLoweringPass());
624 
625   // Replace OpenCL enqueued block function pointers with global variables.
626   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
627 
628   if (TM.getOptLevel() > CodeGenOpt::None) {
629     addPass(createInferAddressSpacesPass());
630     addPass(createAMDGPUPromoteAlloca());
631 
632     if (EnableSROA)
633       addPass(createSROAPass());
634 
635     addStraightLineScalarOptimizationPasses();
636 
637     if (EnableAMDGPUAliasAnalysis) {
638       addPass(createAMDGPUAAWrapperPass());
639       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
640                                              AAResults &AAR) {
641         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
642           AAR.addAAResult(WrapperPass->getResult());
643         }));
644     }
645   }
646 
647   TargetPassConfig::addIRPasses();
648 
649   // EarlyCSE is not always strong enough to clean up what LSR produces. For
650   // example, GVN can combine
651   //
652   //   %0 = add %a, %b
653   //   %1 = add %b, %a
654   //
655   // and
656   //
657   //   %0 = shl nsw %a, 2
658   //   %1 = shl %a, 2
659   //
660   // but EarlyCSE can do neither of them.
661   if (getOptLevel() != CodeGenOpt::None)
662     addEarlyCSEOrGVNPass();
663 }
664 
665 void AMDGPUPassConfig::addCodeGenPrepare() {
666   TargetPassConfig::addCodeGenPrepare();
667 
668   if (EnableLoadStoreVectorizer)
669     addPass(createLoadStoreVectorizerPass());
670 }
671 
672 bool AMDGPUPassConfig::addPreISel() {
673   addPass(createFlattenCFGPass());
674   return false;
675 }
676 
677 bool AMDGPUPassConfig::addInstSelector() {
678   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
679   return false;
680 }
681 
682 bool AMDGPUPassConfig::addGCPasses() {
683   // Do nothing. GC is not supported.
684   return false;
685 }
686 
687 //===----------------------------------------------------------------------===//
688 // R600 Pass Setup
689 //===----------------------------------------------------------------------===//
690 
691 bool R600PassConfig::addPreISel() {
692   AMDGPUPassConfig::addPreISel();
693 
694   if (EnableR600StructurizeCFG)
695     addPass(createStructurizeCFGPass());
696   return false;
697 }
698 
699 bool R600PassConfig::addInstSelector() {
700   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
701   return false;
702 }
703 
704 void R600PassConfig::addPreRegAlloc() {
705   addPass(createR600VectorRegMerger());
706 }
707 
708 void R600PassConfig::addPreSched2() {
709   addPass(createR600EmitClauseMarkers(), false);
710   if (EnableR600IfConvert)
711     addPass(&IfConverterID, false);
712   addPass(createR600ClauseMergePass(), false);
713 }
714 
715 void R600PassConfig::addPreEmitPass() {
716   addPass(createAMDGPUCFGStructurizerPass(), false);
717   addPass(createR600ExpandSpecialInstrsPass(), false);
718   addPass(&FinalizeMachineBundlesID, false);
719   addPass(createR600Packetizer(), false);
720   addPass(createR600ControlFlowFinalizer(), false);
721 }
722 
723 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
724   return new R600PassConfig(*this, PM);
725 }
726 
727 //===----------------------------------------------------------------------===//
728 // GCN Pass Setup
729 //===----------------------------------------------------------------------===//
730 
731 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
732   MachineSchedContext *C) const {
733   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
734   if (ST.enableSIScheduler())
735     return createSIMachineScheduler(C);
736   return createGCNMaxOccupancyMachineScheduler(C);
737 }
738 
739 bool GCNPassConfig::addPreISel() {
740   AMDGPUPassConfig::addPreISel();
741 
742   // FIXME: We need to run a pass to propagate the attributes when calls are
743   // supported.
744   addPass(createAMDGPUAnnotateKernelFeaturesPass());
745 
746   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
747   // regions formed by them.
748   addPass(&AMDGPUUnifyDivergentExitNodesID);
749   if (!LateCFGStructurize) {
750     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
751   }
752   addPass(createSinkingPass());
753   addPass(createAMDGPUAnnotateUniformValues());
754   if (!LateCFGStructurize) {
755     addPass(createSIAnnotateControlFlowPass());
756   }
757 
758   return false;
759 }
760 
761 void GCNPassConfig::addMachineSSAOptimization() {
762   TargetPassConfig::addMachineSSAOptimization();
763 
764   // We want to fold operands after PeepholeOptimizer has run (or as part of
765   // it), because it will eliminate extra copies making it easier to fold the
766   // real source operand. We want to eliminate dead instructions after, so that
767   // we see fewer uses of the copies. We then need to clean up the dead
768   // instructions leftover after the operands are folded as well.
769   //
770   // XXX - Can we get away without running DeadMachineInstructionElim again?
771   addPass(&SIFoldOperandsID);
772   addPass(&DeadMachineInstructionElimID);
773   addPass(&SILoadStoreOptimizerID);
774   if (EnableSDWAPeephole) {
775     addPass(&SIPeepholeSDWAID);
776     addPass(&EarlyMachineLICMID);
777     addPass(&MachineCSEID);
778     addPass(&SIFoldOperandsID);
779     addPass(&DeadMachineInstructionElimID);
780   }
781   addPass(createSIShrinkInstructionsPass());
782 }
783 
784 bool GCNPassConfig::addILPOpts() {
785   if (EnableEarlyIfConversion)
786     addPass(&EarlyIfConverterID);
787 
788   TargetPassConfig::addILPOpts();
789   return false;
790 }
791 
792 bool GCNPassConfig::addInstSelector() {
793   AMDGPUPassConfig::addInstSelector();
794   addPass(createSILowerI1CopiesPass());
795   addPass(&SIFixSGPRCopiesID);
796   return false;
797 }
798 
799 bool GCNPassConfig::addIRTranslator() {
800   addPass(new IRTranslator());
801   return false;
802 }
803 
804 bool GCNPassConfig::addLegalizeMachineIR() {
805   addPass(new Legalizer());
806   return false;
807 }
808 
809 bool GCNPassConfig::addRegBankSelect() {
810   addPass(new RegBankSelect());
811   return false;
812 }
813 
814 bool GCNPassConfig::addGlobalInstructionSelect() {
815   addPass(new InstructionSelect());
816   return false;
817 }
818 
819 void GCNPassConfig::addPreRegAlloc() {
820   if (LateCFGStructurize) {
821     addPass(createAMDGPUMachineCFGStructurizerPass());
822   }
823   addPass(createSIWholeQuadModePass());
824 }
825 
826 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
827   // FIXME: We have to disable the verifier here because of PHIElimination +
828   // TwoAddressInstructions disabling it.
829 
830   // This must be run immediately after phi elimination and before
831   // TwoAddressInstructions, otherwise the processing of the tied operand of
832   // SI_ELSE will introduce a copy of the tied operand source after the else.
833   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
834 
835   // This must be run after SILowerControlFlow, since it needs to use the
836   // machine-level CFG, but before register allocation.
837   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
838 
839   TargetPassConfig::addFastRegAlloc(RegAllocPass);
840 }
841 
842 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
843   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
844 
845   // This must be run immediately after phi elimination and before
846   // TwoAddressInstructions, otherwise the processing of the tied operand of
847   // SI_ELSE will introduce a copy of the tied operand source after the else.
848   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
849 
850   // This must be run after SILowerControlFlow, since it needs to use the
851   // machine-level CFG, but before register allocation.
852   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
853 
854   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
855 }
856 
857 void GCNPassConfig::addPostRegAlloc() {
858   addPass(&SIFixVGPRCopiesID);
859   addPass(&SIOptimizeExecMaskingID);
860   TargetPassConfig::addPostRegAlloc();
861 }
862 
863 void GCNPassConfig::addPreSched2() {
864 }
865 
866 void GCNPassConfig::addPreEmitPass() {
867   // The hazard recognizer that runs as part of the post-ra scheduler does not
868   // guarantee to be able handle all hazards correctly. This is because if there
869   // are multiple scheduling regions in a basic block, the regions are scheduled
870   // bottom up, so when we begin to schedule a region we don't know what
871   // instructions were emitted directly before it.
872   //
873   // Here we add a stand-alone hazard recognizer pass which can handle all
874   // cases.
875   addPass(&PostRAHazardRecognizerID);
876 
877   addPass(createSIMemoryLegalizerPass());
878   addPass(createSIInsertWaitcntsPass());
879   addPass(createSIShrinkInstructionsPass());
880   addPass(&SIInsertSkipsPassID);
881   addPass(createSIDebuggerInsertNopsPass());
882   addPass(&BranchRelaxationPassID);
883 }
884 
885 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
886   return new GCNPassConfig(*this, PM);
887 }
888