1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPUTargetObjectFile.h"
18 #include "AMDGPU.h"
19 #include "AMDGPUTargetTransformInfo.h"
20 #include "R600ISelLowering.h"
21 #include "R600InstrInfo.h"
22 #include "R600MachineScheduler.h"
23 #include "SIISelLowering.h"
24 #include "SIInstrInfo.h"
25 #include "llvm/Analysis/Passes.h"
26 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/IR/Verifier.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/IR/LegacyPassManager.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/TargetRegistry.h"
35 #include "llvm/Support/raw_os_ostream.h"
36 #include "llvm/Transforms/IPO.h"
37 #include "llvm/Transforms/Scalar.h"
38 #include <llvm/CodeGen/Passes.h>
39 
40 using namespace llvm;
41 
42 extern "C" void LLVMInitializeAMDGPUTarget() {
43   // Register the target
44   RegisterTargetMachine<R600TargetMachine> X(TheAMDGPUTarget);
45   RegisterTargetMachine<GCNTargetMachine> Y(TheGCNTarget);
46 
47   PassRegistry *PR = PassRegistry::getPassRegistry();
48   initializeSILowerI1CopiesPass(*PR);
49   initializeSIFixSGPRCopiesPass(*PR);
50   initializeSIFoldOperandsPass(*PR);
51   initializeSIFixSGPRLiveRangesPass(*PR);
52   initializeSIFixControlFlowLiveIntervalsPass(*PR);
53   initializeSILoadStoreOptimizerPass(*PR);
54   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
55   initializeAMDGPUAnnotateUniformValuesPass(*PR);
56   initializeAMDGPUPromoteAllocaPass(*PR);
57   initializeSIAnnotateControlFlowPass(*PR);
58   initializeSIInsertNopsPass(*PR);
59   initializeSIInsertWaitsPass(*PR);
60   initializeSIWholeQuadModePass(*PR);
61   initializeSILowerControlFlowPass(*PR);
62 }
63 
64 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
65   if (TT.getOS() == Triple::AMDHSA)
66     return make_unique<AMDGPUHSATargetObjectFile>();
67 
68   return make_unique<AMDGPUTargetObjectFile>();
69 }
70 
71 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
72   return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
73 }
74 
75 static MachineSchedRegistry
76 R600SchedRegistry("r600", "Run R600's custom scheduler",
77                    createR600MachineScheduler);
78 
79 static MachineSchedRegistry
80 SISchedRegistry("si", "Run SI's custom scheduler",
81                 createSIMachineScheduler);
82 
83 static std::string computeDataLayout(const Triple &TT) {
84   std::string Ret = "e-p:32:32";
85 
86   if (TT.getArch() == Triple::amdgcn) {
87     // 32-bit private, local, and region pointers. 64-bit global and constant.
88     Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
89   }
90 
91   Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
92          "-v512:512-v1024:1024-v2048:2048-n32:64";
93 
94   return Ret;
95 }
96 
97 LLVM_READNONE
98 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
99   if (!GPU.empty())
100     return GPU;
101 
102   // HSA only supports CI+, so change the default GPU to a CI for HSA.
103   if (TT.getArch() == Triple::amdgcn)
104     return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
105 
106   return "";
107 }
108 
109 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
110                                          StringRef CPU, StringRef FS,
111                                          TargetOptions Options, Reloc::Model RM,
112                                          CodeModel::Model CM,
113                                          CodeGenOpt::Level OptLevel)
114     : LLVMTargetMachine(T, computeDataLayout(TT), TT,
115                         getGPUOrDefault(TT, CPU), FS, Options, RM, CM,
116                         OptLevel),
117       TLOF(createTLOF(getTargetTriple())),
118       Subtarget(TT, getTargetCPU(), FS, *this),
119       IntrinsicInfo() {
120   setRequiresStructuredCFG(true);
121   initAsmInfo();
122 }
123 
124 AMDGPUTargetMachine::~AMDGPUTargetMachine() { }
125 
126 //===----------------------------------------------------------------------===//
127 // R600 Target Machine (R600 -> Cayman)
128 //===----------------------------------------------------------------------===//
129 
130 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
131                                      StringRef CPU, StringRef FS,
132                                      TargetOptions Options, Reloc::Model RM,
133                                      CodeModel::Model CM, CodeGenOpt::Level OL)
134     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
135 
136 //===----------------------------------------------------------------------===//
137 // GCN Target Machine (SI+)
138 //===----------------------------------------------------------------------===//
139 
140 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
141                                    StringRef CPU, StringRef FS,
142                                    TargetOptions Options, Reloc::Model RM,
143                                    CodeModel::Model CM, CodeGenOpt::Level OL)
144     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
145 
146 //===----------------------------------------------------------------------===//
147 // AMDGPU Pass Setup
148 //===----------------------------------------------------------------------===//
149 
150 namespace {
151 
152 cl::opt<bool> InsertNops(
153   "amdgpu-insert-nops",
154   cl::desc("Insert two nop instructions for each high level source statement"),
155   cl::init(false));
156 
157 class AMDGPUPassConfig : public TargetPassConfig {
158 public:
159   AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
160     : TargetPassConfig(TM, PM) {
161 
162     // Exceptions and StackMaps are not supported, so these passes will never do
163     // anything.
164     disablePass(&StackMapLivenessID);
165     disablePass(&FuncletLayoutID);
166   }
167 
168   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
169     return getTM<AMDGPUTargetMachine>();
170   }
171 
172   ScheduleDAGInstrs *
173   createMachineScheduler(MachineSchedContext *C) const override {
174     const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
175     if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
176       return createR600MachineScheduler(C);
177     else if (ST.enableSIScheduler())
178       return createSIMachineScheduler(C);
179     return nullptr;
180   }
181 
182   void addIRPasses() override;
183   void addCodeGenPrepare() override;
184   bool addPreISel() override;
185   bool addInstSelector() override;
186   bool addGCPasses() override;
187 };
188 
189 class R600PassConfig final : public AMDGPUPassConfig {
190 public:
191   R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
192     : AMDGPUPassConfig(TM, PM) { }
193 
194   bool addPreISel() override;
195   void addPreRegAlloc() override;
196   void addPreSched2() override;
197   void addPreEmitPass() override;
198 };
199 
200 class GCNPassConfig final : public AMDGPUPassConfig {
201 public:
202   GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
203     : AMDGPUPassConfig(TM, PM) { }
204   bool addPreISel() override;
205   bool addInstSelector() override;
206   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
207   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
208   void addPreRegAlloc() override;
209   void addPostRegAlloc() override;
210   void addPreSched2() override;
211   void addPreEmitPass() override;
212 };
213 
214 } // End of anonymous namespace
215 
216 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
217   return TargetIRAnalysis([this](const Function &F) {
218     return TargetTransformInfo(
219         AMDGPUTTIImpl(this, F.getParent()->getDataLayout()));
220   });
221 }
222 
223 void AMDGPUPassConfig::addIRPasses() {
224   // Function calls are not supported, so make sure we inline everything.
225   addPass(createAMDGPUAlwaysInlinePass());
226   addPass(createAlwaysInlinerPass());
227   // We need to add the barrier noop pass, otherwise adding the function
228   // inlining pass will cause all of the PassConfigs passes to be run
229   // one function at a time, which means if we have a nodule with two
230   // functions, then we will generate code for the first function
231   // without ever running any passes on the second.
232   addPass(createBarrierNoopPass());
233 
234   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
235   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
236 
237   TargetPassConfig::addIRPasses();
238 }
239 
240 void AMDGPUPassConfig::addCodeGenPrepare() {
241   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
242   const AMDGPUSubtarget &ST = *TM.getSubtargetImpl();
243   if (TM.getOptLevel() > CodeGenOpt::None && ST.isPromoteAllocaEnabled()) {
244     addPass(createAMDGPUPromoteAlloca(&TM));
245     addPass(createSROAPass());
246   }
247   TargetPassConfig::addCodeGenPrepare();
248 }
249 
250 bool
251 AMDGPUPassConfig::addPreISel() {
252   addPass(createFlattenCFGPass());
253   return false;
254 }
255 
256 bool AMDGPUPassConfig::addInstSelector() {
257   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
258   return false;
259 }
260 
261 bool AMDGPUPassConfig::addGCPasses() {
262   // Do nothing. GC is not supported.
263   return false;
264 }
265 
266 //===----------------------------------------------------------------------===//
267 // R600 Pass Setup
268 //===----------------------------------------------------------------------===//
269 
270 bool R600PassConfig::addPreISel() {
271   AMDGPUPassConfig::addPreISel();
272   const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
273   if (ST.IsIRStructurizerEnabled())
274     addPass(createStructurizeCFGPass());
275   addPass(createR600TextureIntrinsicsReplacer());
276   return false;
277 }
278 
279 void R600PassConfig::addPreRegAlloc() {
280   addPass(createR600VectorRegMerger(*TM));
281 }
282 
283 void R600PassConfig::addPreSched2() {
284   const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
285   addPass(createR600EmitClauseMarkers(), false);
286   if (ST.isIfCvtEnabled())
287     addPass(&IfConverterID, false);
288   addPass(createR600ClauseMergePass(*TM), false);
289 }
290 
291 void R600PassConfig::addPreEmitPass() {
292   addPass(createAMDGPUCFGStructurizerPass(), false);
293   addPass(createR600ExpandSpecialInstrsPass(*TM), false);
294   addPass(&FinalizeMachineBundlesID, false);
295   addPass(createR600Packetizer(*TM), false);
296   addPass(createR600ControlFlowFinalizer(*TM), false);
297 }
298 
299 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
300   return new R600PassConfig(this, PM);
301 }
302 
303 //===----------------------------------------------------------------------===//
304 // GCN Pass Setup
305 //===----------------------------------------------------------------------===//
306 
307 bool GCNPassConfig::addPreISel() {
308   AMDGPUPassConfig::addPreISel();
309 
310   // FIXME: We need to run a pass to propagate the attributes when calls are
311   // supported.
312   addPass(&AMDGPUAnnotateKernelFeaturesID);
313   addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
314   addPass(createSinkingPass());
315   addPass(createSITypeRewriter());
316   addPass(createAMDGPUAnnotateUniformValues());
317   addPass(createSIAnnotateControlFlowPass());
318 
319   return false;
320 }
321 
322 bool GCNPassConfig::addInstSelector() {
323   AMDGPUPassConfig::addInstSelector();
324   addPass(createSILowerI1CopiesPass());
325   addPass(&SIFixSGPRCopiesID);
326   addPass(createSIFoldOperandsPass());
327   return false;
328 }
329 
330 void GCNPassConfig::addPreRegAlloc() {
331   const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
332 
333   // This needs to be run directly before register allocation because
334   // earlier passes might recompute live intervals.
335   // TODO: handle CodeGenOpt::None; fast RA ignores spill weights set by the pass
336   if (getOptLevel() > CodeGenOpt::None) {
337     insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
338   }
339 
340   if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {
341     // Don't do this with no optimizations since it throws away debug info by
342     // merging nonadjacent loads.
343 
344     // This should be run after scheduling, but before register allocation. It
345     // also need extra copies to the address operand to be eliminated.
346     insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
347     insertPass(&MachineSchedulerID, &RegisterCoalescerID);
348   }
349   addPass(createSIShrinkInstructionsPass(), false);
350   addPass(createSIWholeQuadModePass());
351 }
352 
353 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
354   addPass(&SIFixSGPRLiveRangesID);
355   TargetPassConfig::addFastRegAlloc(RegAllocPass);
356 }
357 
358 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
359   // We want to run this after LiveVariables is computed to avoid computing them
360   // twice.
361   // FIXME: We shouldn't disable the verifier here. r249087 introduced a failure
362   // that needs to be fixed.
363   insertPass(&LiveVariablesID, &SIFixSGPRLiveRangesID, /*VerifyAfter=*/false);
364   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
365 }
366 
367 void GCNPassConfig::addPostRegAlloc() {
368   addPass(createSIShrinkInstructionsPass(), false);
369 }
370 
371 void GCNPassConfig::addPreSched2() {
372 }
373 
374 void GCNPassConfig::addPreEmitPass() {
375   addPass(createSIInsertWaitsPass(), false);
376   addPass(createSILowerControlFlowPass(), false);
377   if (InsertNops) {
378     addPass(createSIInsertNopsPass(), false);
379   }
380 }
381 
382 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
383   return new GCNPassConfig(this, PM);
384 }
385