1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUExportClustering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
28 #include "R600MachineScheduler.h"
29 #include "SIMachineFunctionInfo.h"
30 #include "SIMachineScheduler.h"
31 #include "TargetInfo/AMDGPUTargetInfo.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
35 #include "llvm/CodeGen/GlobalISel/Localizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MIRParser/MIParser.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/LegacyPassManager.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/Pass.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Transforms/IPO.h"
50 #include "llvm/Transforms/IPO/AlwaysInliner.h"
51 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
52 #include "llvm/Transforms/Scalar.h"
53 #include "llvm/Transforms/Scalar/GVN.h"
54 #include "llvm/Transforms/Utils.h"
55 #include "llvm/Transforms/Vectorize.h"
56 #include <memory>
57 
58 using namespace llvm;
59 
60 static cl::opt<bool> EnableR600StructurizeCFG(
61   "r600-ir-structurize",
62   cl::desc("Use StructurizeCFG IR pass"),
63   cl::init(true));
64 
65 static cl::opt<bool> EnableSROA(
66   "amdgpu-sroa",
67   cl::desc("Run SROA after promote alloca pass"),
68   cl::ReallyHidden,
69   cl::init(true));
70 
71 static cl::opt<bool>
72 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
73                         cl::desc("Run early if-conversion"),
74                         cl::init(false));
75 
76 static cl::opt<bool>
77 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
78             cl::desc("Run pre-RA exec mask optimizations"),
79             cl::init(true));
80 
81 static cl::opt<bool> EnableR600IfConvert(
82   "r600-if-convert",
83   cl::desc("Use if conversion pass"),
84   cl::ReallyHidden,
85   cl::init(true));
86 
87 // Option to disable vectorizer for tests.
88 static cl::opt<bool> EnableLoadStoreVectorizer(
89   "amdgpu-load-store-vectorizer",
90   cl::desc("Enable load store vectorizer"),
91   cl::init(true),
92   cl::Hidden);
93 
94 // Option to control global loads scalarization
95 static cl::opt<bool> ScalarizeGlobal(
96   "amdgpu-scalarize-global-loads",
97   cl::desc("Enable global load scalarization"),
98   cl::init(true),
99   cl::Hidden);
100 
101 // Option to run internalize pass.
102 static cl::opt<bool> InternalizeSymbols(
103   "amdgpu-internalize-symbols",
104   cl::desc("Enable elimination of non-kernel functions and unused globals"),
105   cl::init(false),
106   cl::Hidden);
107 
108 // Option to inline all early.
109 static cl::opt<bool> EarlyInlineAll(
110   "amdgpu-early-inline-all",
111   cl::desc("Inline all functions early"),
112   cl::init(false),
113   cl::Hidden);
114 
115 static cl::opt<bool> EnableSDWAPeephole(
116   "amdgpu-sdwa-peephole",
117   cl::desc("Enable SDWA peepholer"),
118   cl::init(true));
119 
120 static cl::opt<bool> EnableDPPCombine(
121   "amdgpu-dpp-combine",
122   cl::desc("Enable DPP combiner"),
123   cl::init(true));
124 
125 // Enable address space based alias analysis
126 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
127   cl::desc("Enable AMDGPU Alias Analysis"),
128   cl::init(true));
129 
130 // Option to run late CFG structurizer
131 static cl::opt<bool, true> LateCFGStructurize(
132   "amdgpu-late-structurize",
133   cl::desc("Enable late CFG structurization"),
134   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
135   cl::Hidden);
136 
137 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
138   "amdgpu-function-calls",
139   cl::desc("Enable AMDGPU function call support"),
140   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
141   cl::init(true),
142   cl::Hidden);
143 
144 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
145   "amdgpu-fixed-function-abi",
146   cl::desc("Enable all implicit function arguments"),
147   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
148   cl::init(false),
149   cl::Hidden);
150 
151 // Enable lib calls simplifications
152 static cl::opt<bool> EnableLibCallSimplify(
153   "amdgpu-simplify-libcall",
154   cl::desc("Enable amdgpu library simplifications"),
155   cl::init(true),
156   cl::Hidden);
157 
158 static cl::opt<bool> EnableLowerKernelArguments(
159   "amdgpu-ir-lower-kernel-arguments",
160   cl::desc("Lower kernel argument loads in IR pass"),
161   cl::init(true),
162   cl::Hidden);
163 
164 static cl::opt<bool> EnableRegReassign(
165   "amdgpu-reassign-regs",
166   cl::desc("Enable register reassign optimizations on gfx10+"),
167   cl::init(true),
168   cl::Hidden);
169 
170 // Enable atomic optimization
171 static cl::opt<bool> EnableAtomicOptimizations(
172   "amdgpu-atomic-optimizations",
173   cl::desc("Enable atomic optimizations"),
174   cl::init(false),
175   cl::Hidden);
176 
177 // Enable Mode register optimization
178 static cl::opt<bool> EnableSIModeRegisterPass(
179   "amdgpu-mode-register",
180   cl::desc("Enable mode register pass"),
181   cl::init(true),
182   cl::Hidden);
183 
184 // Option is used in lit tests to prevent deadcoding of patterns inspected.
185 static cl::opt<bool>
186 EnableDCEInRA("amdgpu-dce-in-ra",
187     cl::init(true), cl::Hidden,
188     cl::desc("Enable machine DCE inside regalloc"));
189 
190 static cl::opt<bool> EnableScalarIRPasses(
191   "amdgpu-scalar-ir-passes",
192   cl::desc("Enable scalar IR passes"),
193   cl::init(true),
194   cl::Hidden);
195 
196 static cl::opt<bool> EnableStructurizerWorkarounds(
197     "amdgpu-enable-structurizer-workarounds",
198     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
199     cl::Hidden);
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFoldOperandsPass(*PR);
220   initializeSIPeepholeSDWAPass(*PR);
221   initializeSIShrinkInstructionsPass(*PR);
222   initializeSIOptimizeExecMaskingPreRAPass(*PR);
223   initializeSILoadStoreOptimizerPass(*PR);
224   initializeAMDGPUFixFunctionBitcastsPass(*PR);
225   initializeAMDGPUAlwaysInlinePass(*PR);
226   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
227   initializeAMDGPUAnnotateUniformValuesPass(*PR);
228   initializeAMDGPUArgumentUsageInfoPass(*PR);
229   initializeAMDGPUAtomicOptimizerPass(*PR);
230   initializeAMDGPULowerKernelArgumentsPass(*PR);
231   initializeAMDGPULowerKernelAttributesPass(*PR);
232   initializeAMDGPULowerIntrinsicsPass(*PR);
233   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
234   initializeAMDGPUPostLegalizerCombinerPass(*PR);
235   initializeAMDGPUPreLegalizerCombinerPass(*PR);
236   initializeAMDGPUPromoteAllocaPass(*PR);
237   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
238   initializeAMDGPUCodeGenPreparePass(*PR);
239   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
240   initializeAMDGPUPropagateAttributesLatePass(*PR);
241   initializeAMDGPURewriteOutArgumentsPass(*PR);
242   initializeAMDGPUUnifyMetadataPass(*PR);
243   initializeSIAnnotateControlFlowPass(*PR);
244   initializeSIInsertHardClausesPass(*PR);
245   initializeSIInsertWaitcntsPass(*PR);
246   initializeSIModeRegisterPass(*PR);
247   initializeSIWholeQuadModePass(*PR);
248   initializeSILowerControlFlowPass(*PR);
249   initializeSIRemoveShortExecBranchesPass(*PR);
250   initializeSIPreEmitPeepholePass(*PR);
251   initializeSIInsertSkipsPass(*PR);
252   initializeSIMemoryLegalizerPass(*PR);
253   initializeSIOptimizeExecMaskingPass(*PR);
254   initializeSIPreAllocateWWMRegsPass(*PR);
255   initializeSIFormMemoryClausesPass(*PR);
256   initializeSIPostRABundlerPass(*PR);
257   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
258   initializeAMDGPUAAWrapperPassPass(*PR);
259   initializeAMDGPUExternalAAWrapperPass(*PR);
260   initializeAMDGPUUseNativeCallsPass(*PR);
261   initializeAMDGPUSimplifyLibCallsPass(*PR);
262   initializeAMDGPUInlinerPass(*PR);
263   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
264   initializeGCNRegBankReassignPass(*PR);
265   initializeGCNNSAReassignPass(*PR);
266   initializeSIAddIMGInitPass(*PR);
267 }
268 
269 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
270   return std::make_unique<AMDGPUTargetObjectFile>();
271 }
272 
273 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
274   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
275 }
276 
277 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
278   return new SIScheduleDAGMI(C);
279 }
280 
281 static ScheduleDAGInstrs *
282 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
283   ScheduleDAGMILive *DAG =
284     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
285   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
286   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
287   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
288   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
289   return DAG;
290 }
291 
292 static ScheduleDAGInstrs *
293 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
294   auto DAG = new GCNIterativeScheduler(C,
295     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
296   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
297   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
298   return DAG;
299 }
300 
301 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
302   return new GCNIterativeScheduler(C,
303     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
304 }
305 
306 static ScheduleDAGInstrs *
307 createIterativeILPMachineScheduler(MachineSchedContext *C) {
308   auto DAG = new GCNIterativeScheduler(C,
309     GCNIterativeScheduler::SCHEDULE_ILP);
310   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
311   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
312   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
313   return DAG;
314 }
315 
316 static MachineSchedRegistry
317 R600SchedRegistry("r600", "Run R600's custom scheduler",
318                    createR600MachineScheduler);
319 
320 static MachineSchedRegistry
321 SISchedRegistry("si", "Run SI's custom scheduler",
322                 createSIMachineScheduler);
323 
324 static MachineSchedRegistry
325 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
326                              "Run GCN scheduler to maximize occupancy",
327                              createGCNMaxOccupancyMachineScheduler);
328 
329 static MachineSchedRegistry
330 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
331   "Run GCN scheduler to maximize occupancy (experimental)",
332   createIterativeGCNMaxOccupancyMachineScheduler);
333 
334 static MachineSchedRegistry
335 GCNMinRegSchedRegistry("gcn-minreg",
336   "Run GCN iterative scheduler for minimal register usage (experimental)",
337   createMinRegScheduler);
338 
339 static MachineSchedRegistry
340 GCNILPSchedRegistry("gcn-ilp",
341   "Run GCN iterative scheduler for ILP scheduling (experimental)",
342   createIterativeILPMachineScheduler);
343 
344 static StringRef computeDataLayout(const Triple &TT) {
345   if (TT.getArch() == Triple::r600) {
346     // 32-bit pointers.
347       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
348              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
349   }
350 
351   // 32-bit private, local, and region pointers. 64-bit global, constant and
352   // flat, non-integral buffer fat pointers.
353     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
354          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
355          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
356          "-ni:7";
357 }
358 
359 LLVM_READNONE
360 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
361   if (!GPU.empty())
362     return GPU;
363 
364   // Need to default to a target with flat support for HSA.
365   if (TT.getArch() == Triple::amdgcn)
366     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
367 
368   return "r600";
369 }
370 
371 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
372   // The AMDGPU toolchain only supports generating shared objects, so we
373   // must always use PIC.
374   return Reloc::PIC_;
375 }
376 
377 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
378                                          StringRef CPU, StringRef FS,
379                                          TargetOptions Options,
380                                          Optional<Reloc::Model> RM,
381                                          Optional<CodeModel::Model> CM,
382                                          CodeGenOpt::Level OptLevel)
383     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
384                         FS, Options, getEffectiveRelocModel(RM),
385                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
386       TLOF(createTLOF(getTargetTriple())) {
387   initAsmInfo();
388   if (TT.getArch() == Triple::amdgcn) {
389     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
390       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
391     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
392       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
393   }
394 }
395 
396 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
397 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
398 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
399 
400 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
401 
402 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
403   Attribute GPUAttr = F.getFnAttribute("target-cpu");
404   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
405 }
406 
407 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
408   Attribute FSAttr = F.getFnAttribute("target-features");
409 
410   return FSAttr.isValid() ? FSAttr.getValueAsString()
411                           : getTargetFeatureString();
412 }
413 
414 /// Predicate for Internalize pass.
415 static bool mustPreserveGV(const GlobalValue &GV) {
416   if (const Function *F = dyn_cast<Function>(&GV))
417     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
418 
419   return !GV.use_empty();
420 }
421 
422 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
423   Builder.DivergentTarget = true;
424 
425   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
426   bool Internalize = InternalizeSymbols;
427   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
428   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
429   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
430 
431   if (EnableFunctionCalls) {
432     delete Builder.Inliner;
433     Builder.Inliner = createAMDGPUFunctionInliningPass();
434   }
435 
436   Builder.addExtension(
437     PassManagerBuilder::EP_ModuleOptimizerEarly,
438     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
439                                                legacy::PassManagerBase &PM) {
440       if (AMDGPUAA) {
441         PM.add(createAMDGPUAAWrapperPass());
442         PM.add(createAMDGPUExternalAAWrapperPass());
443       }
444       PM.add(createAMDGPUUnifyMetadataPass());
445       PM.add(createAMDGPUPrintfRuntimeBinding());
446       if (Internalize)
447         PM.add(createInternalizePass(mustPreserveGV));
448       PM.add(createAMDGPUPropagateAttributesLatePass(this));
449       if (Internalize)
450         PM.add(createGlobalDCEPass());
451       if (EarlyInline)
452         PM.add(createAMDGPUAlwaysInlinePass(false));
453   });
454 
455   Builder.addExtension(
456     PassManagerBuilder::EP_EarlyAsPossible,
457     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
458                                       legacy::PassManagerBase &PM) {
459       if (AMDGPUAA) {
460         PM.add(createAMDGPUAAWrapperPass());
461         PM.add(createAMDGPUExternalAAWrapperPass());
462       }
463       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
464       PM.add(llvm::createAMDGPUUseNativeCallsPass());
465       if (LibCallSimplify)
466         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
467   });
468 
469   Builder.addExtension(
470     PassManagerBuilder::EP_CGSCCOptimizerLate,
471     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
472       // Add infer address spaces pass to the opt pipeline after inlining
473       // but before SROA to increase SROA opportunities.
474       PM.add(createInferAddressSpacesPass());
475 
476       // This should run after inlining to have any chance of doing anything,
477       // and before other cleanup optimizations.
478       PM.add(createAMDGPULowerKernelAttributesPass());
479 
480       // Promote alloca to vector before SROA and loop unroll. If we manage
481       // to eliminate allocas before unroll we may choose to unroll less.
482       if (EnableOpt)
483         PM.add(createAMDGPUPromoteAllocaToVector());
484   });
485 
486   Builder.addExtension(
487       PassManagerBuilder::EP_LoopOptimizerEnd,
488       [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
489         // Add SROA after loop unrolling as more promotable patterns are
490         // exposed after small loops are fully unrolled.
491         PM.add(createSROAPass());
492       });
493 }
494 
495 //===----------------------------------------------------------------------===//
496 // R600 Target Machine (R600 -> Cayman)
497 //===----------------------------------------------------------------------===//
498 
499 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
500                                      StringRef CPU, StringRef FS,
501                                      TargetOptions Options,
502                                      Optional<Reloc::Model> RM,
503                                      Optional<CodeModel::Model> CM,
504                                      CodeGenOpt::Level OL, bool JIT)
505     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
506   setRequiresStructuredCFG(true);
507 
508   // Override the default since calls aren't supported for r600.
509   if (EnableFunctionCalls &&
510       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
511     EnableFunctionCalls = false;
512 }
513 
514 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
515   const Function &F) const {
516   StringRef GPU = getGPUName(F);
517   StringRef FS = getFeatureString(F);
518 
519   SmallString<128> SubtargetKey(GPU);
520   SubtargetKey.append(FS);
521 
522   auto &I = SubtargetMap[SubtargetKey];
523   if (!I) {
524     // This needs to be done before we create a new subtarget since any
525     // creation will depend on the TM and the code generation flags on the
526     // function that reside in TargetOptions.
527     resetTargetOptions(F);
528     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
529   }
530 
531   return I.get();
532 }
533 
534 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
535                                               unsigned DestAS) const {
536   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
537          AMDGPU::isFlatGlobalAddrSpace(DestAS);
538 }
539 
540 TargetTransformInfo
541 R600TargetMachine::getTargetTransformInfo(const Function &F) {
542   return TargetTransformInfo(R600TTIImpl(this, F));
543 }
544 
545 //===----------------------------------------------------------------------===//
546 // GCN Target Machine (SI+)
547 //===----------------------------------------------------------------------===//
548 
549 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
550                                    StringRef CPU, StringRef FS,
551                                    TargetOptions Options,
552                                    Optional<Reloc::Model> RM,
553                                    Optional<CodeModel::Model> CM,
554                                    CodeGenOpt::Level OL, bool JIT)
555     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
556 
557 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
558   StringRef GPU = getGPUName(F);
559   StringRef FS = getFeatureString(F);
560 
561   SmallString<128> SubtargetKey(GPU);
562   SubtargetKey.append(FS);
563 
564   auto &I = SubtargetMap[SubtargetKey];
565   if (!I) {
566     // This needs to be done before we create a new subtarget since any
567     // creation will depend on the TM and the code generation flags on the
568     // function that reside in TargetOptions.
569     resetTargetOptions(F);
570     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
571   }
572 
573   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
574 
575   return I.get();
576 }
577 
578 TargetTransformInfo
579 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
580   return TargetTransformInfo(GCNTTIImpl(this, F));
581 }
582 
583 //===----------------------------------------------------------------------===//
584 // AMDGPU Pass Setup
585 //===----------------------------------------------------------------------===//
586 
587 namespace {
588 
589 class AMDGPUPassConfig : public TargetPassConfig {
590 public:
591   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
592     : TargetPassConfig(TM, PM) {
593     // Exceptions and StackMaps are not supported, so these passes will never do
594     // anything.
595     disablePass(&StackMapLivenessID);
596     disablePass(&FuncletLayoutID);
597   }
598 
599   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
600     return getTM<AMDGPUTargetMachine>();
601   }
602 
603   ScheduleDAGInstrs *
604   createMachineScheduler(MachineSchedContext *C) const override {
605     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
606     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
607     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
608     return DAG;
609   }
610 
611   void addEarlyCSEOrGVNPass();
612   void addStraightLineScalarOptimizationPasses();
613   void addIRPasses() override;
614   void addCodeGenPrepare() override;
615   bool addPreISel() override;
616   bool addInstSelector() override;
617   bool addGCPasses() override;
618 
619   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
620 };
621 
622 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
623   return getStandardCSEConfigForOpt(TM->getOptLevel());
624 }
625 
626 class R600PassConfig final : public AMDGPUPassConfig {
627 public:
628   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
629     : AMDGPUPassConfig(TM, PM) {}
630 
631   ScheduleDAGInstrs *createMachineScheduler(
632     MachineSchedContext *C) const override {
633     return createR600MachineScheduler(C);
634   }
635 
636   bool addPreISel() override;
637   bool addInstSelector() override;
638   void addPreRegAlloc() override;
639   void addPreSched2() override;
640   void addPreEmitPass() override;
641 };
642 
643 class GCNPassConfig final : public AMDGPUPassConfig {
644 public:
645   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
646     : AMDGPUPassConfig(TM, PM) {
647     // It is necessary to know the register usage of the entire call graph.  We
648     // allow calls without EnableAMDGPUFunctionCalls if they are marked
649     // noinline, so this is always required.
650     setRequiresCodeGenSCCOrder(true);
651   }
652 
653   GCNTargetMachine &getGCNTargetMachine() const {
654     return getTM<GCNTargetMachine>();
655   }
656 
657   ScheduleDAGInstrs *
658   createMachineScheduler(MachineSchedContext *C) const override;
659 
660   bool addPreISel() override;
661   void addMachineSSAOptimization() override;
662   bool addILPOpts() override;
663   bool addInstSelector() override;
664   bool addIRTranslator() override;
665   void addPreLegalizeMachineIR() override;
666   bool addLegalizeMachineIR() override;
667   void addPreRegBankSelect() override;
668   bool addRegBankSelect() override;
669   bool addGlobalInstructionSelect() override;
670   void addFastRegAlloc() override;
671   void addOptimizedRegAlloc() override;
672   void addPreRegAlloc() override;
673   bool addPreRewrite() override;
674   void addPostRegAlloc() override;
675   void addPreSched2() override;
676   void addPreEmitPass() override;
677 };
678 
679 } // end anonymous namespace
680 
681 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
682   if (getOptLevel() == CodeGenOpt::Aggressive)
683     addPass(createGVNPass());
684   else
685     addPass(createEarlyCSEPass());
686 }
687 
688 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
689   addPass(createLICMPass());
690   addPass(createSeparateConstOffsetFromGEPPass());
691   addPass(createSpeculativeExecutionPass());
692   // ReassociateGEPs exposes more opportunites for SLSR. See
693   // the example in reassociate-geps-and-slsr.ll.
694   addPass(createStraightLineStrengthReducePass());
695   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
696   // EarlyCSE can reuse.
697   addEarlyCSEOrGVNPass();
698   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
699   addPass(createNaryReassociatePass());
700   // NaryReassociate on GEPs creates redundant common expressions, so run
701   // EarlyCSE after it.
702   addPass(createEarlyCSEPass());
703 }
704 
705 void AMDGPUPassConfig::addIRPasses() {
706   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
707 
708   // There is no reason to run these.
709   disablePass(&StackMapLivenessID);
710   disablePass(&FuncletLayoutID);
711   disablePass(&PatchableFunctionID);
712 
713   addPass(createAMDGPUPrintfRuntimeBinding());
714 
715   // This must occur before inlining, as the inliner will not look through
716   // bitcast calls.
717   addPass(createAMDGPUFixFunctionBitcastsPass());
718 
719   // A call to propagate attributes pass in the backend in case opt was not run.
720   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
721 
722   addPass(createAtomicExpandPass());
723 
724 
725   addPass(createAMDGPULowerIntrinsicsPass());
726 
727   // Function calls are not supported, so make sure we inline everything.
728   addPass(createAMDGPUAlwaysInlinePass());
729   addPass(createAlwaysInlinerLegacyPass());
730   // We need to add the barrier noop pass, otherwise adding the function
731   // inlining pass will cause all of the PassConfigs passes to be run
732   // one function at a time, which means if we have a nodule with two
733   // functions, then we will generate code for the first function
734   // without ever running any passes on the second.
735   addPass(createBarrierNoopPass());
736 
737   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
738   if (TM.getTargetTriple().getArch() == Triple::r600)
739     addPass(createR600OpenCLImageTypeLoweringPass());
740 
741   // Replace OpenCL enqueued block function pointers with global variables.
742   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
743 
744   if (TM.getOptLevel() > CodeGenOpt::None) {
745     addPass(createInferAddressSpacesPass());
746     addPass(createAMDGPUPromoteAlloca());
747 
748     if (EnableSROA)
749       addPass(createSROAPass());
750 
751     if (EnableScalarIRPasses)
752       addStraightLineScalarOptimizationPasses();
753 
754     if (EnableAMDGPUAliasAnalysis) {
755       addPass(createAMDGPUAAWrapperPass());
756       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
757                                              AAResults &AAR) {
758         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
759           AAR.addAAResult(WrapperPass->getResult());
760         }));
761     }
762   }
763 
764   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
765     // TODO: May want to move later or split into an early and late one.
766     addPass(createAMDGPUCodeGenPreparePass());
767   }
768 
769   TargetPassConfig::addIRPasses();
770 
771   // EarlyCSE is not always strong enough to clean up what LSR produces. For
772   // example, GVN can combine
773   //
774   //   %0 = add %a, %b
775   //   %1 = add %b, %a
776   //
777   // and
778   //
779   //   %0 = shl nsw %a, 2
780   //   %1 = shl %a, 2
781   //
782   // but EarlyCSE can do neither of them.
783   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
784     addEarlyCSEOrGVNPass();
785 }
786 
787 void AMDGPUPassConfig::addCodeGenPrepare() {
788   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
789     addPass(createAMDGPUAnnotateKernelFeaturesPass());
790 
791   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
792       EnableLowerKernelArguments)
793     addPass(createAMDGPULowerKernelArgumentsPass());
794 
795   addPass(&AMDGPUPerfHintAnalysisID);
796 
797   TargetPassConfig::addCodeGenPrepare();
798 
799   if (EnableLoadStoreVectorizer)
800     addPass(createLoadStoreVectorizerPass());
801 
802   // LowerSwitch pass may introduce unreachable blocks that can
803   // cause unexpected behavior for subsequent passes. Placing it
804   // here seems better that these blocks would get cleaned up by
805   // UnreachableBlockElim inserted next in the pass flow.
806   addPass(createLowerSwitchPass());
807 }
808 
809 bool AMDGPUPassConfig::addPreISel() {
810   addPass(createFlattenCFGPass());
811   return false;
812 }
813 
814 bool AMDGPUPassConfig::addInstSelector() {
815   // Defer the verifier until FinalizeISel.
816   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
817   return false;
818 }
819 
820 bool AMDGPUPassConfig::addGCPasses() {
821   // Do nothing. GC is not supported.
822   return false;
823 }
824 
825 //===----------------------------------------------------------------------===//
826 // R600 Pass Setup
827 //===----------------------------------------------------------------------===//
828 
829 bool R600PassConfig::addPreISel() {
830   AMDGPUPassConfig::addPreISel();
831 
832   if (EnableR600StructurizeCFG)
833     addPass(createStructurizeCFGPass());
834   return false;
835 }
836 
837 bool R600PassConfig::addInstSelector() {
838   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
839   return false;
840 }
841 
842 void R600PassConfig::addPreRegAlloc() {
843   addPass(createR600VectorRegMerger());
844 }
845 
846 void R600PassConfig::addPreSched2() {
847   addPass(createR600EmitClauseMarkers(), false);
848   if (EnableR600IfConvert)
849     addPass(&IfConverterID, false);
850   addPass(createR600ClauseMergePass(), false);
851 }
852 
853 void R600PassConfig::addPreEmitPass() {
854   addPass(createAMDGPUCFGStructurizerPass(), false);
855   addPass(createR600ExpandSpecialInstrsPass(), false);
856   addPass(&FinalizeMachineBundlesID, false);
857   addPass(createR600Packetizer(), false);
858   addPass(createR600ControlFlowFinalizer(), false);
859 }
860 
861 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
862   return new R600PassConfig(*this, PM);
863 }
864 
865 //===----------------------------------------------------------------------===//
866 // GCN Pass Setup
867 //===----------------------------------------------------------------------===//
868 
869 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
870   MachineSchedContext *C) const {
871   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
872   if (ST.enableSIScheduler())
873     return createSIMachineScheduler(C);
874   return createGCNMaxOccupancyMachineScheduler(C);
875 }
876 
877 bool GCNPassConfig::addPreISel() {
878   AMDGPUPassConfig::addPreISel();
879 
880   if (EnableAtomicOptimizations) {
881     addPass(createAMDGPUAtomicOptimizerPass());
882   }
883 
884   // FIXME: We need to run a pass to propagate the attributes when calls are
885   // supported.
886 
887   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
888   // regions formed by them.
889   addPass(&AMDGPUUnifyDivergentExitNodesID);
890   if (!LateCFGStructurize) {
891     if (EnableStructurizerWorkarounds) {
892       addPass(createFixIrreduciblePass());
893       addPass(createUnifyLoopExitsPass());
894     }
895     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
896   }
897   addPass(createSinkingPass());
898   addPass(createAMDGPUAnnotateUniformValues());
899   if (!LateCFGStructurize) {
900     addPass(createSIAnnotateControlFlowPass());
901   }
902   addPass(createLCSSAPass());
903 
904   return false;
905 }
906 
907 void GCNPassConfig::addMachineSSAOptimization() {
908   TargetPassConfig::addMachineSSAOptimization();
909 
910   // We want to fold operands after PeepholeOptimizer has run (or as part of
911   // it), because it will eliminate extra copies making it easier to fold the
912   // real source operand. We want to eliminate dead instructions after, so that
913   // we see fewer uses of the copies. We then need to clean up the dead
914   // instructions leftover after the operands are folded as well.
915   //
916   // XXX - Can we get away without running DeadMachineInstructionElim again?
917   addPass(&SIFoldOperandsID);
918   if (EnableDPPCombine)
919     addPass(&GCNDPPCombineID);
920   addPass(&DeadMachineInstructionElimID);
921   addPass(&SILoadStoreOptimizerID);
922   if (EnableSDWAPeephole) {
923     addPass(&SIPeepholeSDWAID);
924     addPass(&EarlyMachineLICMID);
925     addPass(&MachineCSEID);
926     addPass(&SIFoldOperandsID);
927     addPass(&DeadMachineInstructionElimID);
928   }
929   addPass(createSIShrinkInstructionsPass());
930 }
931 
932 bool GCNPassConfig::addILPOpts() {
933   if (EnableEarlyIfConversion)
934     addPass(&EarlyIfConverterID);
935 
936   TargetPassConfig::addILPOpts();
937   return false;
938 }
939 
940 bool GCNPassConfig::addInstSelector() {
941   AMDGPUPassConfig::addInstSelector();
942   addPass(&SIFixSGPRCopiesID);
943   addPass(createSILowerI1CopiesPass());
944   addPass(createSIAddIMGInitPass());
945   return false;
946 }
947 
948 bool GCNPassConfig::addIRTranslator() {
949   addPass(new IRTranslator());
950   return false;
951 }
952 
953 void GCNPassConfig::addPreLegalizeMachineIR() {
954   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
955   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
956   addPass(new Localizer());
957 }
958 
959 bool GCNPassConfig::addLegalizeMachineIR() {
960   addPass(new Legalizer());
961   return false;
962 }
963 
964 void GCNPassConfig::addPreRegBankSelect() {
965   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
966   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
967 }
968 
969 bool GCNPassConfig::addRegBankSelect() {
970   addPass(new RegBankSelect());
971   return false;
972 }
973 
974 bool GCNPassConfig::addGlobalInstructionSelect() {
975   addPass(new InstructionSelect());
976   return false;
977 }
978 
979 void GCNPassConfig::addPreRegAlloc() {
980   if (LateCFGStructurize) {
981     addPass(createAMDGPUMachineCFGStructurizerPass());
982   }
983   addPass(createSIWholeQuadModePass());
984 }
985 
986 void GCNPassConfig::addFastRegAlloc() {
987   // FIXME: We have to disable the verifier here because of PHIElimination +
988   // TwoAddressInstructions disabling it.
989 
990   // This must be run immediately after phi elimination and before
991   // TwoAddressInstructions, otherwise the processing of the tied operand of
992   // SI_ELSE will introduce a copy of the tied operand source after the else.
993   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
994 
995   // This must be run just after RegisterCoalescing.
996   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
997 
998   TargetPassConfig::addFastRegAlloc();
999 }
1000 
1001 void GCNPassConfig::addOptimizedRegAlloc() {
1002   if (OptExecMaskPreRA)
1003     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1004   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1005 
1006   // This must be run immediately after phi elimination and before
1007   // TwoAddressInstructions, otherwise the processing of the tied operand of
1008   // SI_ELSE will introduce a copy of the tied operand source after the else.
1009   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1010 
1011   // This must be run just after RegisterCoalescing.
1012   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
1013 
1014   if (EnableDCEInRA)
1015     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1016 
1017   TargetPassConfig::addOptimizedRegAlloc();
1018 }
1019 
1020 bool GCNPassConfig::addPreRewrite() {
1021   if (EnableRegReassign) {
1022     addPass(&GCNNSAReassignID);
1023     addPass(&GCNRegBankReassignID);
1024   }
1025   return true;
1026 }
1027 
1028 void GCNPassConfig::addPostRegAlloc() {
1029   addPass(&SIFixVGPRCopiesID);
1030   if (getOptLevel() > CodeGenOpt::None)
1031     addPass(&SIOptimizeExecMaskingID);
1032   TargetPassConfig::addPostRegAlloc();
1033 
1034   // Equivalent of PEI for SGPRs.
1035   addPass(&SILowerSGPRSpillsID);
1036 }
1037 
1038 void GCNPassConfig::addPreSched2() {
1039   addPass(&SIPostRABundlerID);
1040 }
1041 
1042 void GCNPassConfig::addPreEmitPass() {
1043   addPass(createSIMemoryLegalizerPass());
1044   addPass(createSIInsertWaitcntsPass());
1045   addPass(createSIShrinkInstructionsPass());
1046   addPass(createSIModeRegisterPass());
1047 
1048   // The hazard recognizer that runs as part of the post-ra scheduler does not
1049   // guarantee to be able handle all hazards correctly. This is because if there
1050   // are multiple scheduling regions in a basic block, the regions are scheduled
1051   // bottom up, so when we begin to schedule a region we don't know what
1052   // instructions were emitted directly before it.
1053   //
1054   // Here we add a stand-alone hazard recognizer pass which can handle all
1055   // cases.
1056   //
1057   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
1058   // be better for it to emit S_NOP <N> when possible.
1059   addPass(&PostRAHazardRecognizerID);
1060   if (getOptLevel() > CodeGenOpt::None)
1061     addPass(&SIInsertHardClausesID);
1062 
1063   addPass(&SIRemoveShortExecBranchesID);
1064   addPass(&SIInsertSkipsPassID);
1065   addPass(&SIPreEmitPeepholeID);
1066   addPass(&BranchRelaxationPassID);
1067 }
1068 
1069 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1070   return new GCNPassConfig(*this, PM);
1071 }
1072 
1073 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1074   return new yaml::SIMachineFunctionInfo();
1075 }
1076 
1077 yaml::MachineFunctionInfo *
1078 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1079   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1080   return new yaml::SIMachineFunctionInfo(*MFI,
1081                                          *MF.getSubtarget().getRegisterInfo());
1082 }
1083 
1084 bool GCNTargetMachine::parseMachineFunctionInfo(
1085     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1086     SMDiagnostic &Error, SMRange &SourceRange) const {
1087   const yaml::SIMachineFunctionInfo &YamlMFI =
1088       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1089   MachineFunction &MF = PFS.MF;
1090   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1091 
1092   MFI->initializeBaseYamlFields(YamlMFI);
1093 
1094   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1095     Register TempReg;
1096     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1097       SourceRange = RegName.SourceRange;
1098       return true;
1099     }
1100     RegVal = TempReg;
1101 
1102     return false;
1103   };
1104 
1105   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1106     // Create a diagnostic for a the register string literal.
1107     const MemoryBuffer &Buffer =
1108         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1109     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1110                          RegName.Value.size(), SourceMgr::DK_Error,
1111                          "incorrect register class for field", RegName.Value,
1112                          None, None);
1113     SourceRange = RegName.SourceRange;
1114     return true;
1115   };
1116 
1117   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1118       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1119       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1120     return true;
1121 
1122   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1123       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1124     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1125   }
1126 
1127   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1128       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1129     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1130   }
1131 
1132   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1133       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1134     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1135   }
1136 
1137   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1138                                    const TargetRegisterClass &RC,
1139                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1140                                    unsigned SystemSGPRs) {
1141     // Skip parsing if it's not present.
1142     if (!A)
1143       return false;
1144 
1145     if (A->IsRegister) {
1146       Register Reg;
1147       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1148         SourceRange = A->RegisterName.SourceRange;
1149         return true;
1150       }
1151       if (!RC.contains(Reg))
1152         return diagnoseRegisterClass(A->RegisterName);
1153       Arg = ArgDescriptor::createRegister(Reg);
1154     } else
1155       Arg = ArgDescriptor::createStack(A->StackOffset);
1156     // Check and apply the optional mask.
1157     if (A->Mask)
1158       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1159 
1160     MFI->NumUserSGPRs += UserSGPRs;
1161     MFI->NumSystemSGPRs += SystemSGPRs;
1162     return false;
1163   };
1164 
1165   if (YamlMFI.ArgInfo &&
1166       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1167                              AMDGPU::SGPR_128RegClass,
1168                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1169        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1170                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1171                              2, 0) ||
1172        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1173                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1174        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1175                              AMDGPU::SReg_64RegClass,
1176                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1177        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1178                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1179                              2, 0) ||
1180        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1181                              AMDGPU::SReg_64RegClass,
1182                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1183        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1184                              AMDGPU::SGPR_32RegClass,
1185                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1186        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1187                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1188                              0, 1) ||
1189        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1190                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1191                              0, 1) ||
1192        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1193                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1194                              0, 1) ||
1195        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1196                              AMDGPU::SGPR_32RegClass,
1197                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1198        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1199                              AMDGPU::SGPR_32RegClass,
1200                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1201        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1202                              AMDGPU::SReg_64RegClass,
1203                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1204        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1205                              AMDGPU::SReg_64RegClass,
1206                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1207        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1208                              AMDGPU::VGPR_32RegClass,
1209                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1210        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1211                              AMDGPU::VGPR_32RegClass,
1212                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1213        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1214                              AMDGPU::VGPR_32RegClass,
1215                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1216     return true;
1217 
1218   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1219   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1220   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1221   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1222   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1223   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1224 
1225   return false;
1226 }
1227