1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600MachineScheduler.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIMachineScheduler.h"
27 #include "TargetInfo/AMDGPUTargetInfo.h"
28 #include "llvm/Analysis/CGSCCPassManager.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/Localizer.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MIRParser/MIParser.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/LegacyPassManager.h"
37 #include "llvm/IR/PassManager.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/Passes/PassBuilder.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Transforms/IPO.h"
42 #include "llvm/Transforms/IPO/AlwaysInliner.h"
43 #include "llvm/Transforms/IPO/GlobalDCE.h"
44 #include "llvm/Transforms/IPO/Internalize.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
49 #include "llvm/Transforms/Utils.h"
50 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
51 #include "llvm/Transforms/Vectorize.h"
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73             cl::desc("Run pre-RA exec mask optimizations"),
74             cl::init(true));
75 
76 static cl::opt<bool> EnableR600IfConvert(
77   "r600-if-convert",
78   cl::desc("Use if conversion pass"),
79   cl::ReallyHidden,
80   cl::init(true));
81 
82 // Option to disable vectorizer for tests.
83 static cl::opt<bool> EnableLoadStoreVectorizer(
84   "amdgpu-load-store-vectorizer",
85   cl::desc("Enable load store vectorizer"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to control global loads scalarization
90 static cl::opt<bool> ScalarizeGlobal(
91   "amdgpu-scalarize-global-loads",
92   cl::desc("Enable global load scalarization"),
93   cl::init(true),
94   cl::Hidden);
95 
96 // Option to run internalize pass.
97 static cl::opt<bool> InternalizeSymbols(
98   "amdgpu-internalize-symbols",
99   cl::desc("Enable elimination of non-kernel functions and unused globals"),
100   cl::init(false),
101   cl::Hidden);
102 
103 // Option to inline all early.
104 static cl::opt<bool> EarlyInlineAll(
105   "amdgpu-early-inline-all",
106   cl::desc("Inline all functions early"),
107   cl::init(false),
108   cl::Hidden);
109 
110 static cl::opt<bool> EnableSDWAPeephole(
111   "amdgpu-sdwa-peephole",
112   cl::desc("Enable SDWA peepholer"),
113   cl::init(true));
114 
115 static cl::opt<bool> EnableDPPCombine(
116   "amdgpu-dpp-combine",
117   cl::desc("Enable DPP combiner"),
118   cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122   cl::desc("Enable AMDGPU Alias Analysis"),
123   cl::init(true));
124 
125 // Option to run late CFG structurizer
126 static cl::opt<bool, true> LateCFGStructurize(
127   "amdgpu-late-structurize",
128   cl::desc("Enable late CFG structurization"),
129   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
130   cl::Hidden);
131 
132 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
133   "amdgpu-function-calls",
134   cl::desc("Enable AMDGPU function call support"),
135   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
136   cl::init(true),
137   cl::Hidden);
138 
139 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
140   "amdgpu-fixed-function-abi",
141   cl::desc("Enable all implicit function arguments"),
142   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
143   cl::init(false),
144   cl::Hidden);
145 
146 // Enable lib calls simplifications
147 static cl::opt<bool> EnableLibCallSimplify(
148   "amdgpu-simplify-libcall",
149   cl::desc("Enable amdgpu library simplifications"),
150   cl::init(true),
151   cl::Hidden);
152 
153 static cl::opt<bool> EnableLowerKernelArguments(
154   "amdgpu-ir-lower-kernel-arguments",
155   cl::desc("Lower kernel argument loads in IR pass"),
156   cl::init(true),
157   cl::Hidden);
158 
159 static cl::opt<bool> EnableRegReassign(
160   "amdgpu-reassign-regs",
161   cl::desc("Enable register reassign optimizations on gfx10+"),
162   cl::init(true),
163   cl::Hidden);
164 
165 // Enable atomic optimization
166 static cl::opt<bool> EnableAtomicOptimizations(
167   "amdgpu-atomic-optimizations",
168   cl::desc("Enable atomic optimizations"),
169   cl::init(false),
170   cl::Hidden);
171 
172 // Enable Mode register optimization
173 static cl::opt<bool> EnableSIModeRegisterPass(
174   "amdgpu-mode-register",
175   cl::desc("Enable mode register pass"),
176   cl::init(true),
177   cl::Hidden);
178 
179 // Option is used in lit tests to prevent deadcoding of patterns inspected.
180 static cl::opt<bool>
181 EnableDCEInRA("amdgpu-dce-in-ra",
182     cl::init(true), cl::Hidden,
183     cl::desc("Enable machine DCE inside regalloc"));
184 
185 static cl::opt<bool> EnableScalarIRPasses(
186   "amdgpu-scalar-ir-passes",
187   cl::desc("Enable scalar IR passes"),
188   cl::init(true),
189   cl::Hidden);
190 
191 static cl::opt<bool> EnableStructurizerWorkarounds(
192     "amdgpu-enable-structurizer-workarounds",
193     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
194     cl::Hidden);
195 
196 static cl::opt<bool>
197     DisableLowerModuleLDS("amdgpu-disable-lower-module-lds", cl::Hidden,
198                           cl::desc("Disable lower module lds pass"),
199                           cl::init(false));
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFoldOperandsPass(*PR);
220   initializeSIPeepholeSDWAPass(*PR);
221   initializeSIShrinkInstructionsPass(*PR);
222   initializeSIOptimizeExecMaskingPreRAPass(*PR);
223   initializeSILoadStoreOptimizerPass(*PR);
224   initializeAMDGPUFixFunctionBitcastsPass(*PR);
225   initializeAMDGPUAlwaysInlinePass(*PR);
226   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
227   initializeAMDGPUAnnotateUniformValuesPass(*PR);
228   initializeAMDGPUArgumentUsageInfoPass(*PR);
229   initializeAMDGPUAtomicOptimizerPass(*PR);
230   initializeAMDGPULowerKernelArgumentsPass(*PR);
231   initializeAMDGPULowerKernelAttributesPass(*PR);
232   initializeAMDGPULowerIntrinsicsPass(*PR);
233   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
234   initializeAMDGPUPostLegalizerCombinerPass(*PR);
235   initializeAMDGPUPreLegalizerCombinerPass(*PR);
236   initializeAMDGPURegBankCombinerPass(*PR);
237   initializeAMDGPUPromoteAllocaPass(*PR);
238   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
239   initializeAMDGPUCodeGenPreparePass(*PR);
240   initializeAMDGPULateCodeGenPreparePass(*PR);
241   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
242   initializeAMDGPUPropagateAttributesLatePass(*PR);
243   initializeAMDGPULowerModuleLDSPass(*PR);
244   initializeAMDGPURewriteOutArgumentsPass(*PR);
245   initializeAMDGPUUnifyMetadataPass(*PR);
246   initializeSIAnnotateControlFlowPass(*PR);
247   initializeSIInsertHardClausesPass(*PR);
248   initializeSIInsertWaitcntsPass(*PR);
249   initializeSIModeRegisterPass(*PR);
250   initializeSIWholeQuadModePass(*PR);
251   initializeSILowerControlFlowPass(*PR);
252   initializeSIPreEmitPeepholePass(*PR);
253   initializeSILateBranchLoweringPass(*PR);
254   initializeSIMemoryLegalizerPass(*PR);
255   initializeSIOptimizeExecMaskingPass(*PR);
256   initializeSIPreAllocateWWMRegsPass(*PR);
257   initializeSIFormMemoryClausesPass(*PR);
258   initializeSIPostRABundlerPass(*PR);
259   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
260   initializeAMDGPUAAWrapperPassPass(*PR);
261   initializeAMDGPUExternalAAWrapperPass(*PR);
262   initializeAMDGPUUseNativeCallsPass(*PR);
263   initializeAMDGPUSimplifyLibCallsPass(*PR);
264   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
265   initializeGCNRegBankReassignPass(*PR);
266   initializeGCNNSAReassignPass(*PR);
267 }
268 
269 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
270   return std::make_unique<AMDGPUTargetObjectFile>();
271 }
272 
273 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
274   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
275 }
276 
277 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
278   return new SIScheduleDAGMI(C);
279 }
280 
281 static ScheduleDAGInstrs *
282 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
283   ScheduleDAGMILive *DAG =
284     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
285   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
286   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
287   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
288   return DAG;
289 }
290 
291 static ScheduleDAGInstrs *
292 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
293   auto DAG = new GCNIterativeScheduler(C,
294     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
295   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
296   return DAG;
297 }
298 
299 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
300   return new GCNIterativeScheduler(C,
301     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
302 }
303 
304 static ScheduleDAGInstrs *
305 createIterativeILPMachineScheduler(MachineSchedContext *C) {
306   auto DAG = new GCNIterativeScheduler(C,
307     GCNIterativeScheduler::SCHEDULE_ILP);
308   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
309   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
310   return DAG;
311 }
312 
313 static MachineSchedRegistry
314 R600SchedRegistry("r600", "Run R600's custom scheduler",
315                    createR600MachineScheduler);
316 
317 static MachineSchedRegistry
318 SISchedRegistry("si", "Run SI's custom scheduler",
319                 createSIMachineScheduler);
320 
321 static MachineSchedRegistry
322 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
323                              "Run GCN scheduler to maximize occupancy",
324                              createGCNMaxOccupancyMachineScheduler);
325 
326 static MachineSchedRegistry
327 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
328   "Run GCN scheduler to maximize occupancy (experimental)",
329   createIterativeGCNMaxOccupancyMachineScheduler);
330 
331 static MachineSchedRegistry
332 GCNMinRegSchedRegistry("gcn-minreg",
333   "Run GCN iterative scheduler for minimal register usage (experimental)",
334   createMinRegScheduler);
335 
336 static MachineSchedRegistry
337 GCNILPSchedRegistry("gcn-ilp",
338   "Run GCN iterative scheduler for ILP scheduling (experimental)",
339   createIterativeILPMachineScheduler);
340 
341 static StringRef computeDataLayout(const Triple &TT) {
342   if (TT.getArch() == Triple::r600) {
343     // 32-bit pointers.
344     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
345            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
346   }
347 
348   // 32-bit private, local, and region pointers. 64-bit global, constant and
349   // flat, non-integral buffer fat pointers.
350   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
351          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
352          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
353          "-ni:7";
354 }
355 
356 LLVM_READNONE
357 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
358   if (!GPU.empty())
359     return GPU;
360 
361   // Need to default to a target with flat support for HSA.
362   if (TT.getArch() == Triple::amdgcn)
363     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
364 
365   return "r600";
366 }
367 
368 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
369   // The AMDGPU toolchain only supports generating shared objects, so we
370   // must always use PIC.
371   return Reloc::PIC_;
372 }
373 
374 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
375                                          StringRef CPU, StringRef FS,
376                                          TargetOptions Options,
377                                          Optional<Reloc::Model> RM,
378                                          Optional<CodeModel::Model> CM,
379                                          CodeGenOpt::Level OptLevel)
380     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
381                         FS, Options, getEffectiveRelocModel(RM),
382                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
383       TLOF(createTLOF(getTargetTriple())) {
384   initAsmInfo();
385   if (TT.getArch() == Triple::amdgcn) {
386     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
387       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
388     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
389       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
390   }
391 }
392 
393 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
394 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
395 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
396 
397 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
398 
399 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
400   Attribute GPUAttr = F.getFnAttribute("target-cpu");
401   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
402 }
403 
404 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
405   Attribute FSAttr = F.getFnAttribute("target-features");
406 
407   return FSAttr.isValid() ? FSAttr.getValueAsString()
408                           : getTargetFeatureString();
409 }
410 
411 /// Predicate for Internalize pass.
412 static bool mustPreserveGV(const GlobalValue &GV) {
413   if (const Function *F = dyn_cast<Function>(&GV))
414     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
415 
416   return !GV.use_empty();
417 }
418 
419 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
420   Builder.DivergentTarget = true;
421 
422   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
423   bool Internalize = InternalizeSymbols;
424   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
425   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
426   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
427 
428   if (EnableFunctionCalls) {
429     delete Builder.Inliner;
430     Builder.Inliner = createFunctionInliningPass();
431   }
432 
433   Builder.addExtension(
434     PassManagerBuilder::EP_ModuleOptimizerEarly,
435     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
436                                                legacy::PassManagerBase &PM) {
437       if (AMDGPUAA) {
438         PM.add(createAMDGPUAAWrapperPass());
439         PM.add(createAMDGPUExternalAAWrapperPass());
440       }
441       PM.add(createAMDGPUUnifyMetadataPass());
442       PM.add(createAMDGPUPrintfRuntimeBinding());
443       if (Internalize)
444         PM.add(createInternalizePass(mustPreserveGV));
445       PM.add(createAMDGPUPropagateAttributesLatePass(this));
446       if (Internalize)
447         PM.add(createGlobalDCEPass());
448       if (EarlyInline)
449         PM.add(createAMDGPUAlwaysInlinePass(false));
450   });
451 
452   Builder.addExtension(
453     PassManagerBuilder::EP_EarlyAsPossible,
454     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
455                                       legacy::PassManagerBase &PM) {
456       if (AMDGPUAA) {
457         PM.add(createAMDGPUAAWrapperPass());
458         PM.add(createAMDGPUExternalAAWrapperPass());
459       }
460       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
461       PM.add(llvm::createAMDGPUUseNativeCallsPass());
462       if (LibCallSimplify)
463         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
464   });
465 
466   Builder.addExtension(
467     PassManagerBuilder::EP_CGSCCOptimizerLate,
468     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
469       // Add infer address spaces pass to the opt pipeline after inlining
470       // but before SROA to increase SROA opportunities.
471       PM.add(createInferAddressSpacesPass());
472 
473       // This should run after inlining to have any chance of doing anything,
474       // and before other cleanup optimizations.
475       PM.add(createAMDGPULowerKernelAttributesPass());
476 
477       // Promote alloca to vector before SROA and loop unroll. If we manage
478       // to eliminate allocas before unroll we may choose to unroll less.
479       if (EnableOpt)
480         PM.add(createAMDGPUPromoteAllocaToVector());
481   });
482 }
483 
484 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
485   AAM.registerFunctionAnalysis<AMDGPUAA>();
486 }
487 
488 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
489                                                        bool DebugPassManager) {
490   PB.registerPipelineParsingCallback(
491       [this](StringRef PassName, ModulePassManager &PM,
492              ArrayRef<PassBuilder::PipelineElement>) {
493         if (PassName == "amdgpu-propagate-attributes-late") {
494           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
495           return true;
496         }
497         if (PassName == "amdgpu-unify-metadata") {
498           PM.addPass(AMDGPUUnifyMetadataPass());
499           return true;
500         }
501         if (PassName == "amdgpu-printf-runtime-binding") {
502           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
503           return true;
504         }
505         if (PassName == "amdgpu-always-inline") {
506           PM.addPass(AMDGPUAlwaysInlinePass());
507           return true;
508         }
509         if (PassName == "amdgpu-lower-module-lds") {
510           PM.addPass(AMDGPULowerModuleLDSPass());
511           return true;
512         }
513         return false;
514       });
515   PB.registerPipelineParsingCallback(
516       [this](StringRef PassName, FunctionPassManager &PM,
517              ArrayRef<PassBuilder::PipelineElement>) {
518         if (PassName == "amdgpu-simplifylib") {
519           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
520           return true;
521         }
522         if (PassName == "amdgpu-usenative") {
523           PM.addPass(AMDGPUUseNativeCallsPass());
524           return true;
525         }
526         if (PassName == "amdgpu-promote-alloca") {
527           PM.addPass(AMDGPUPromoteAllocaPass(*this));
528           return true;
529         }
530         if (PassName == "amdgpu-promote-alloca-to-vector") {
531           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
532           return true;
533         }
534         if (PassName == "amdgpu-lower-kernel-attributes") {
535           PM.addPass(AMDGPULowerKernelAttributesPass());
536           return true;
537         }
538         if (PassName == "amdgpu-propagate-attributes-early") {
539           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
540           return true;
541         }
542         return false;
543       });
544 
545   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
546     FAM.registerPass([&] { return AMDGPUAA(); });
547   });
548 
549   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
550     if (AAName == "amdgpu-aa") {
551       AAM.registerFunctionAnalysis<AMDGPUAA>();
552       return true;
553     }
554     return false;
555   });
556 
557   PB.registerPipelineStartEPCallback([this, DebugPassManager](
558                                          ModulePassManager &PM,
559                                          PassBuilder::OptimizationLevel Level) {
560     FunctionPassManager FPM(DebugPassManager);
561     FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
562     FPM.addPass(AMDGPUUseNativeCallsPass());
563     if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
564       FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
565     PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
566   });
567 
568   PB.registerPipelineEarlySimplificationEPCallback(
569       [this](ModulePassManager &PM, PassBuilder::OptimizationLevel Level) {
570         if (Level == PassBuilder::OptimizationLevel::O0)
571           return;
572 
573         PM.addPass(AMDGPUUnifyMetadataPass());
574         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
575 
576         if (InternalizeSymbols) {
577           PM.addPass(InternalizePass(mustPreserveGV));
578         }
579         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
580         if (InternalizeSymbols) {
581           PM.addPass(GlobalDCEPass());
582         }
583         if (EarlyInlineAll && !EnableFunctionCalls)
584           PM.addPass(AMDGPUAlwaysInlinePass());
585       });
586 
587   PB.registerCGSCCOptimizerLateEPCallback(
588       [this, DebugPassManager](CGSCCPassManager &PM,
589                                PassBuilder::OptimizationLevel Level) {
590         if (Level == PassBuilder::OptimizationLevel::O0)
591           return;
592 
593         FunctionPassManager FPM(DebugPassManager);
594 
595         // Add infer address spaces pass to the opt pipeline after inlining
596         // but before SROA to increase SROA opportunities.
597         FPM.addPass(InferAddressSpacesPass());
598 
599         // This should run after inlining to have any chance of doing
600         // anything, and before other cleanup optimizations.
601         FPM.addPass(AMDGPULowerKernelAttributesPass());
602 
603         if (Level != PassBuilder::OptimizationLevel::O0) {
604           // Promote alloca to vector before SROA and loop unroll. If we
605           // manage to eliminate allocas before unroll we may choose to unroll
606           // less.
607           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
608         }
609 
610         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
611       });
612 }
613 
614 //===----------------------------------------------------------------------===//
615 // R600 Target Machine (R600 -> Cayman)
616 //===----------------------------------------------------------------------===//
617 
618 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
619                                      StringRef CPU, StringRef FS,
620                                      TargetOptions Options,
621                                      Optional<Reloc::Model> RM,
622                                      Optional<CodeModel::Model> CM,
623                                      CodeGenOpt::Level OL, bool JIT)
624     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
625   setRequiresStructuredCFG(true);
626 
627   // Override the default since calls aren't supported for r600.
628   if (EnableFunctionCalls &&
629       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
630     EnableFunctionCalls = false;
631 }
632 
633 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
634   const Function &F) const {
635   StringRef GPU = getGPUName(F);
636   StringRef FS = getFeatureString(F);
637 
638   SmallString<128> SubtargetKey(GPU);
639   SubtargetKey.append(FS);
640 
641   auto &I = SubtargetMap[SubtargetKey];
642   if (!I) {
643     // This needs to be done before we create a new subtarget since any
644     // creation will depend on the TM and the code generation flags on the
645     // function that reside in TargetOptions.
646     resetTargetOptions(F);
647     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
648   }
649 
650   return I.get();
651 }
652 
653 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
654   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
655           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
656           AddrSpace == AMDGPUAS::REGION_ADDRESS)
657              ? -1
658              : 0;
659 }
660 
661 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
662                                               unsigned DestAS) const {
663   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
664          AMDGPU::isFlatGlobalAddrSpace(DestAS);
665 }
666 
667 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
668   const auto *LD = dyn_cast<LoadInst>(V);
669   if (!LD)
670     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
671 
672   // It must be a generic pointer loaded.
673   assert(V->getType()->isPointerTy() &&
674          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
675 
676   const auto *Ptr = LD->getPointerOperand();
677   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
678     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
679   // For a generic pointer loaded from the constant memory, it could be assumed
680   // as a global pointer since the constant memory is only populated on the
681   // host side. As implied by the offload programming model, only global
682   // pointers could be referenced on the host side.
683   return AMDGPUAS::GLOBAL_ADDRESS;
684 }
685 
686 TargetTransformInfo
687 R600TargetMachine::getTargetTransformInfo(const Function &F) {
688   return TargetTransformInfo(R600TTIImpl(this, F));
689 }
690 
691 //===----------------------------------------------------------------------===//
692 // GCN Target Machine (SI+)
693 //===----------------------------------------------------------------------===//
694 
695 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
696                                    StringRef CPU, StringRef FS,
697                                    TargetOptions Options,
698                                    Optional<Reloc::Model> RM,
699                                    Optional<CodeModel::Model> CM,
700                                    CodeGenOpt::Level OL, bool JIT)
701     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
702 
703 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
704   StringRef GPU = getGPUName(F);
705   StringRef FS = getFeatureString(F);
706 
707   SmallString<128> SubtargetKey(GPU);
708   SubtargetKey.append(FS);
709 
710   auto &I = SubtargetMap[SubtargetKey];
711   if (!I) {
712     // This needs to be done before we create a new subtarget since any
713     // creation will depend on the TM and the code generation flags on the
714     // function that reside in TargetOptions.
715     resetTargetOptions(F);
716     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
717   }
718 
719   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
720 
721   return I.get();
722 }
723 
724 TargetTransformInfo
725 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
726   return TargetTransformInfo(GCNTTIImpl(this, F));
727 }
728 
729 //===----------------------------------------------------------------------===//
730 // AMDGPU Pass Setup
731 //===----------------------------------------------------------------------===//
732 
733 namespace {
734 
735 class AMDGPUPassConfig : public TargetPassConfig {
736 public:
737   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
738     : TargetPassConfig(TM, PM) {
739     // Exceptions and StackMaps are not supported, so these passes will never do
740     // anything.
741     disablePass(&StackMapLivenessID);
742     disablePass(&FuncletLayoutID);
743   }
744 
745   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
746     return getTM<AMDGPUTargetMachine>();
747   }
748 
749   ScheduleDAGInstrs *
750   createMachineScheduler(MachineSchedContext *C) const override {
751     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
752     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
753     return DAG;
754   }
755 
756   void addEarlyCSEOrGVNPass();
757   void addStraightLineScalarOptimizationPasses();
758   void addIRPasses() override;
759   void addCodeGenPrepare() override;
760   bool addPreISel() override;
761   bool addInstSelector() override;
762   bool addGCPasses() override;
763 
764   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
765 };
766 
767 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
768   return getStandardCSEConfigForOpt(TM->getOptLevel());
769 }
770 
771 class R600PassConfig final : public AMDGPUPassConfig {
772 public:
773   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
774     : AMDGPUPassConfig(TM, PM) {}
775 
776   ScheduleDAGInstrs *createMachineScheduler(
777     MachineSchedContext *C) const override {
778     return createR600MachineScheduler(C);
779   }
780 
781   bool addPreISel() override;
782   bool addInstSelector() override;
783   void addPreRegAlloc() override;
784   void addPreSched2() override;
785   void addPreEmitPass() override;
786 };
787 
788 class GCNPassConfig final : public AMDGPUPassConfig {
789 public:
790   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
791     : AMDGPUPassConfig(TM, PM) {
792     // It is necessary to know the register usage of the entire call graph.  We
793     // allow calls without EnableAMDGPUFunctionCalls if they are marked
794     // noinline, so this is always required.
795     setRequiresCodeGenSCCOrder(true);
796   }
797 
798   GCNTargetMachine &getGCNTargetMachine() const {
799     return getTM<GCNTargetMachine>();
800   }
801 
802   ScheduleDAGInstrs *
803   createMachineScheduler(MachineSchedContext *C) const override;
804 
805   bool addPreISel() override;
806   void addMachineSSAOptimization() override;
807   bool addILPOpts() override;
808   bool addInstSelector() override;
809   bool addIRTranslator() override;
810   void addPreLegalizeMachineIR() override;
811   bool addLegalizeMachineIR() override;
812   void addPreRegBankSelect() override;
813   bool addRegBankSelect() override;
814   void addPreGlobalInstructionSelect() override;
815   bool addGlobalInstructionSelect() override;
816   void addFastRegAlloc() override;
817   void addOptimizedRegAlloc() override;
818   void addPreRegAlloc() override;
819   bool addPreRewrite() override;
820   void addPostRegAlloc() override;
821   void addPreSched2() override;
822   void addPreEmitPass() override;
823 };
824 
825 } // end anonymous namespace
826 
827 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
828   if (getOptLevel() == CodeGenOpt::Aggressive)
829     addPass(createGVNPass());
830   else
831     addPass(createEarlyCSEPass());
832 }
833 
834 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
835   addPass(createLICMPass());
836   addPass(createSeparateConstOffsetFromGEPPass());
837   addPass(createSpeculativeExecutionPass());
838   // ReassociateGEPs exposes more opportunites for SLSR. See
839   // the example in reassociate-geps-and-slsr.ll.
840   addPass(createStraightLineStrengthReducePass());
841   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
842   // EarlyCSE can reuse.
843   addEarlyCSEOrGVNPass();
844   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
845   addPass(createNaryReassociatePass());
846   // NaryReassociate on GEPs creates redundant common expressions, so run
847   // EarlyCSE after it.
848   addPass(createEarlyCSEPass());
849 }
850 
851 void AMDGPUPassConfig::addIRPasses() {
852   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
853 
854   // There is no reason to run these.
855   disablePass(&StackMapLivenessID);
856   disablePass(&FuncletLayoutID);
857   disablePass(&PatchableFunctionID);
858 
859   addPass(createAMDGPUPrintfRuntimeBinding());
860 
861   // This must occur before inlining, as the inliner will not look through
862   // bitcast calls.
863   addPass(createAMDGPUFixFunctionBitcastsPass());
864 
865   // A call to propagate attributes pass in the backend in case opt was not run.
866   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
867 
868   addPass(createAtomicExpandPass());
869 
870 
871   addPass(createAMDGPULowerIntrinsicsPass());
872 
873   // Function calls are not supported, so make sure we inline everything.
874   addPass(createAMDGPUAlwaysInlinePass());
875   addPass(createAlwaysInlinerLegacyPass());
876   // We need to add the barrier noop pass, otherwise adding the function
877   // inlining pass will cause all of the PassConfigs passes to be run
878   // one function at a time, which means if we have a nodule with two
879   // functions, then we will generate code for the first function
880   // without ever running any passes on the second.
881   addPass(createBarrierNoopPass());
882 
883   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
884   if (TM.getTargetTriple().getArch() == Triple::r600)
885     addPass(createR600OpenCLImageTypeLoweringPass());
886 
887   // Replace OpenCL enqueued block function pointers with global variables.
888   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
889 
890   // Can increase LDS used by kernel so runs before PromoteAlloca
891   if (!DisableLowerModuleLDS)
892     addPass(createAMDGPULowerModuleLDSPass());
893 
894   if (TM.getOptLevel() > CodeGenOpt::None) {
895     addPass(createInferAddressSpacesPass());
896     addPass(createAMDGPUPromoteAlloca());
897 
898     if (EnableSROA)
899       addPass(createSROAPass());
900 
901     if (EnableScalarIRPasses)
902       addStraightLineScalarOptimizationPasses();
903 
904     if (EnableAMDGPUAliasAnalysis) {
905       addPass(createAMDGPUAAWrapperPass());
906       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
907                                              AAResults &AAR) {
908         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
909           AAR.addAAResult(WrapperPass->getResult());
910         }));
911     }
912   }
913 
914   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
915     // TODO: May want to move later or split into an early and late one.
916     addPass(createAMDGPUCodeGenPreparePass());
917   }
918 
919   TargetPassConfig::addIRPasses();
920 
921   // EarlyCSE is not always strong enough to clean up what LSR produces. For
922   // example, GVN can combine
923   //
924   //   %0 = add %a, %b
925   //   %1 = add %b, %a
926   //
927   // and
928   //
929   //   %0 = shl nsw %a, 2
930   //   %1 = shl %a, 2
931   //
932   // but EarlyCSE can do neither of them.
933   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
934     addEarlyCSEOrGVNPass();
935 }
936 
937 void AMDGPUPassConfig::addCodeGenPrepare() {
938   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
939     addPass(createAMDGPUAnnotateKernelFeaturesPass());
940 
941   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
942       EnableLowerKernelArguments)
943     addPass(createAMDGPULowerKernelArgumentsPass());
944 
945   addPass(&AMDGPUPerfHintAnalysisID);
946 
947   TargetPassConfig::addCodeGenPrepare();
948 
949   if (EnableLoadStoreVectorizer)
950     addPass(createLoadStoreVectorizerPass());
951 
952   // LowerSwitch pass may introduce unreachable blocks that can
953   // cause unexpected behavior for subsequent passes. Placing it
954   // here seems better that these blocks would get cleaned up by
955   // UnreachableBlockElim inserted next in the pass flow.
956   addPass(createLowerSwitchPass());
957 }
958 
959 bool AMDGPUPassConfig::addPreISel() {
960   addPass(createFlattenCFGPass());
961   return false;
962 }
963 
964 bool AMDGPUPassConfig::addInstSelector() {
965   // Defer the verifier until FinalizeISel.
966   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
967   return false;
968 }
969 
970 bool AMDGPUPassConfig::addGCPasses() {
971   // Do nothing. GC is not supported.
972   return false;
973 }
974 
975 //===----------------------------------------------------------------------===//
976 // R600 Pass Setup
977 //===----------------------------------------------------------------------===//
978 
979 bool R600PassConfig::addPreISel() {
980   AMDGPUPassConfig::addPreISel();
981 
982   if (EnableR600StructurizeCFG)
983     addPass(createStructurizeCFGPass());
984   return false;
985 }
986 
987 bool R600PassConfig::addInstSelector() {
988   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
989   return false;
990 }
991 
992 void R600PassConfig::addPreRegAlloc() {
993   addPass(createR600VectorRegMerger());
994 }
995 
996 void R600PassConfig::addPreSched2() {
997   addPass(createR600EmitClauseMarkers(), false);
998   if (EnableR600IfConvert)
999     addPass(&IfConverterID, false);
1000   addPass(createR600ClauseMergePass(), false);
1001 }
1002 
1003 void R600PassConfig::addPreEmitPass() {
1004   addPass(createAMDGPUCFGStructurizerPass(), false);
1005   addPass(createR600ExpandSpecialInstrsPass(), false);
1006   addPass(&FinalizeMachineBundlesID, false);
1007   addPass(createR600Packetizer(), false);
1008   addPass(createR600ControlFlowFinalizer(), false);
1009 }
1010 
1011 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
1012   return new R600PassConfig(*this, PM);
1013 }
1014 
1015 //===----------------------------------------------------------------------===//
1016 // GCN Pass Setup
1017 //===----------------------------------------------------------------------===//
1018 
1019 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1020   MachineSchedContext *C) const {
1021   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1022   if (ST.enableSIScheduler())
1023     return createSIMachineScheduler(C);
1024   return createGCNMaxOccupancyMachineScheduler(C);
1025 }
1026 
1027 bool GCNPassConfig::addPreISel() {
1028   AMDGPUPassConfig::addPreISel();
1029 
1030   addPass(createAMDGPULateCodeGenPreparePass());
1031   if (EnableAtomicOptimizations) {
1032     addPass(createAMDGPUAtomicOptimizerPass());
1033   }
1034 
1035   // FIXME: We need to run a pass to propagate the attributes when calls are
1036   // supported.
1037 
1038   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1039   // regions formed by them.
1040   addPass(&AMDGPUUnifyDivergentExitNodesID);
1041   if (!LateCFGStructurize) {
1042     if (EnableStructurizerWorkarounds) {
1043       addPass(createFixIrreduciblePass());
1044       addPass(createUnifyLoopExitsPass());
1045     }
1046     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1047   }
1048   addPass(createSinkingPass());
1049   addPass(createAMDGPUAnnotateUniformValues());
1050   if (!LateCFGStructurize) {
1051     addPass(createSIAnnotateControlFlowPass());
1052   }
1053   addPass(createLCSSAPass());
1054 
1055   return false;
1056 }
1057 
1058 void GCNPassConfig::addMachineSSAOptimization() {
1059   TargetPassConfig::addMachineSSAOptimization();
1060 
1061   // We want to fold operands after PeepholeOptimizer has run (or as part of
1062   // it), because it will eliminate extra copies making it easier to fold the
1063   // real source operand. We want to eliminate dead instructions after, so that
1064   // we see fewer uses of the copies. We then need to clean up the dead
1065   // instructions leftover after the operands are folded as well.
1066   //
1067   // XXX - Can we get away without running DeadMachineInstructionElim again?
1068   addPass(&SIFoldOperandsID);
1069   if (EnableDPPCombine)
1070     addPass(&GCNDPPCombineID);
1071   addPass(&DeadMachineInstructionElimID);
1072   addPass(&SILoadStoreOptimizerID);
1073   if (EnableSDWAPeephole) {
1074     addPass(&SIPeepholeSDWAID);
1075     addPass(&EarlyMachineLICMID);
1076     addPass(&MachineCSEID);
1077     addPass(&SIFoldOperandsID);
1078     addPass(&DeadMachineInstructionElimID);
1079   }
1080   addPass(createSIShrinkInstructionsPass());
1081 }
1082 
1083 bool GCNPassConfig::addILPOpts() {
1084   if (EnableEarlyIfConversion)
1085     addPass(&EarlyIfConverterID);
1086 
1087   TargetPassConfig::addILPOpts();
1088   return false;
1089 }
1090 
1091 bool GCNPassConfig::addInstSelector() {
1092   AMDGPUPassConfig::addInstSelector();
1093   addPass(&SIFixSGPRCopiesID);
1094   addPass(createSILowerI1CopiesPass());
1095   return false;
1096 }
1097 
1098 bool GCNPassConfig::addIRTranslator() {
1099   addPass(new IRTranslator(getOptLevel()));
1100   return false;
1101 }
1102 
1103 void GCNPassConfig::addPreLegalizeMachineIR() {
1104   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1105   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1106   addPass(new Localizer());
1107 }
1108 
1109 bool GCNPassConfig::addLegalizeMachineIR() {
1110   addPass(new Legalizer());
1111   return false;
1112 }
1113 
1114 void GCNPassConfig::addPreRegBankSelect() {
1115   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1116   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1117 }
1118 
1119 bool GCNPassConfig::addRegBankSelect() {
1120   addPass(new RegBankSelect());
1121   return false;
1122 }
1123 
1124 void GCNPassConfig::addPreGlobalInstructionSelect() {
1125   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1126   addPass(createAMDGPURegBankCombiner(IsOptNone));
1127 }
1128 
1129 bool GCNPassConfig::addGlobalInstructionSelect() {
1130   addPass(new InstructionSelect(getOptLevel()));
1131   return false;
1132 }
1133 
1134 void GCNPassConfig::addPreRegAlloc() {
1135   if (LateCFGStructurize) {
1136     addPass(createAMDGPUMachineCFGStructurizerPass());
1137   }
1138 }
1139 
1140 void GCNPassConfig::addFastRegAlloc() {
1141   // FIXME: We have to disable the verifier here because of PHIElimination +
1142   // TwoAddressInstructions disabling it.
1143 
1144   // This must be run immediately after phi elimination and before
1145   // TwoAddressInstructions, otherwise the processing of the tied operand of
1146   // SI_ELSE will introduce a copy of the tied operand source after the else.
1147   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1148 
1149   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1150   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1151 
1152   TargetPassConfig::addFastRegAlloc();
1153 }
1154 
1155 void GCNPassConfig::addOptimizedRegAlloc() {
1156   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1157   // instructions that cause scheduling barriers.
1158   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1159   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1160 
1161   if (OptExecMaskPreRA)
1162     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1163   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1164 
1165   // This must be run immediately after phi elimination and before
1166   // TwoAddressInstructions, otherwise the processing of the tied operand of
1167   // SI_ELSE will introduce a copy of the tied operand source after the else.
1168   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1169 
1170   if (EnableDCEInRA)
1171     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1172 
1173   TargetPassConfig::addOptimizedRegAlloc();
1174 }
1175 
1176 bool GCNPassConfig::addPreRewrite() {
1177   if (EnableRegReassign) {
1178     addPass(&GCNNSAReassignID);
1179     addPass(createGCNRegBankReassignPass(AMDGPU::RM_BOTH));
1180   }
1181   return true;
1182 }
1183 
1184 void GCNPassConfig::addPostRegAlloc() {
1185   addPass(&SIFixVGPRCopiesID);
1186   if (getOptLevel() > CodeGenOpt::None)
1187     addPass(&SIOptimizeExecMaskingID);
1188   TargetPassConfig::addPostRegAlloc();
1189 
1190   // Equivalent of PEI for SGPRs.
1191   addPass(&SILowerSGPRSpillsID);
1192 }
1193 
1194 void GCNPassConfig::addPreSched2() {
1195   addPass(&SIPostRABundlerID);
1196 }
1197 
1198 void GCNPassConfig::addPreEmitPass() {
1199   addPass(createSIMemoryLegalizerPass());
1200   addPass(createSIInsertWaitcntsPass());
1201   addPass(createSIShrinkInstructionsPass());
1202   addPass(createSIModeRegisterPass());
1203 
1204   if (getOptLevel() > CodeGenOpt::None)
1205     addPass(&SIInsertHardClausesID);
1206 
1207   addPass(&SILateBranchLoweringPassID);
1208   if (getOptLevel() > CodeGenOpt::None)
1209     addPass(&SIPreEmitPeepholeID);
1210   // The hazard recognizer that runs as part of the post-ra scheduler does not
1211   // guarantee to be able handle all hazards correctly. This is because if there
1212   // are multiple scheduling regions in a basic block, the regions are scheduled
1213   // bottom up, so when we begin to schedule a region we don't know what
1214   // instructions were emitted directly before it.
1215   //
1216   // Here we add a stand-alone hazard recognizer pass which can handle all
1217   // cases.
1218   addPass(&PostRAHazardRecognizerID);
1219   addPass(&BranchRelaxationPassID);
1220 }
1221 
1222 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1223   return new GCNPassConfig(*this, PM);
1224 }
1225 
1226 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1227   return new yaml::SIMachineFunctionInfo();
1228 }
1229 
1230 yaml::MachineFunctionInfo *
1231 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1232   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1233   return new yaml::SIMachineFunctionInfo(*MFI,
1234                                          *MF.getSubtarget().getRegisterInfo());
1235 }
1236 
1237 bool GCNTargetMachine::parseMachineFunctionInfo(
1238     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1239     SMDiagnostic &Error, SMRange &SourceRange) const {
1240   const yaml::SIMachineFunctionInfo &YamlMFI =
1241       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1242   MachineFunction &MF = PFS.MF;
1243   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1244 
1245   MFI->initializeBaseYamlFields(YamlMFI);
1246 
1247   if (MFI->Occupancy == 0) {
1248     // Fixup the subtarget dependent default value.
1249     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1250     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1251   }
1252 
1253   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1254     Register TempReg;
1255     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1256       SourceRange = RegName.SourceRange;
1257       return true;
1258     }
1259     RegVal = TempReg;
1260 
1261     return false;
1262   };
1263 
1264   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1265     // Create a diagnostic for a the register string literal.
1266     const MemoryBuffer &Buffer =
1267         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1268     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1269                          RegName.Value.size(), SourceMgr::DK_Error,
1270                          "incorrect register class for field", RegName.Value,
1271                          None, None);
1272     SourceRange = RegName.SourceRange;
1273     return true;
1274   };
1275 
1276   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1277       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1278       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1279     return true;
1280 
1281   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1282       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1283     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1284   }
1285 
1286   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1287       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1288     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1289   }
1290 
1291   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1292       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1293     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1294   }
1295 
1296   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1297                                    const TargetRegisterClass &RC,
1298                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1299                                    unsigned SystemSGPRs) {
1300     // Skip parsing if it's not present.
1301     if (!A)
1302       return false;
1303 
1304     if (A->IsRegister) {
1305       Register Reg;
1306       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1307         SourceRange = A->RegisterName.SourceRange;
1308         return true;
1309       }
1310       if (!RC.contains(Reg))
1311         return diagnoseRegisterClass(A->RegisterName);
1312       Arg = ArgDescriptor::createRegister(Reg);
1313     } else
1314       Arg = ArgDescriptor::createStack(A->StackOffset);
1315     // Check and apply the optional mask.
1316     if (A->Mask)
1317       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1318 
1319     MFI->NumUserSGPRs += UserSGPRs;
1320     MFI->NumSystemSGPRs += SystemSGPRs;
1321     return false;
1322   };
1323 
1324   if (YamlMFI.ArgInfo &&
1325       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1326                              AMDGPU::SGPR_128RegClass,
1327                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1328        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1329                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1330                              2, 0) ||
1331        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1332                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1333        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1334                              AMDGPU::SReg_64RegClass,
1335                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1336        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1337                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1338                              2, 0) ||
1339        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1340                              AMDGPU::SReg_64RegClass,
1341                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1342        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1343                              AMDGPU::SGPR_32RegClass,
1344                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1345        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1346                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1347                              0, 1) ||
1348        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1349                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1350                              0, 1) ||
1351        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1352                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1353                              0, 1) ||
1354        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1355                              AMDGPU::SGPR_32RegClass,
1356                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1357        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1358                              AMDGPU::SGPR_32RegClass,
1359                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1360        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1361                              AMDGPU::SReg_64RegClass,
1362                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1363        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1364                              AMDGPU::SReg_64RegClass,
1365                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1366        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1367                              AMDGPU::VGPR_32RegClass,
1368                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1369        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1370                              AMDGPU::VGPR_32RegClass,
1371                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1372        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1373                              AMDGPU::VGPR_32RegClass,
1374                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1375     return true;
1376 
1377   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1378   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1379   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1380   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1381   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1382   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1383 
1384   return false;
1385 }
1386