1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUTargetObjectFile.h"
20 #include "AMDGPUTargetTransformInfo.h"
21 #include "GCNSchedStrategy.h"
22 #include "R600MachineScheduler.h"
23 #include "SIMachineScheduler.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/MachineScheduler.h"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/CodeGen/TargetPassConfig.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Transforms/IPO.h"
35 #include "llvm/Transforms/IPO/AlwaysInliner.h"
36 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
37 #include "llvm/Transforms/Scalar.h"
38 #include "llvm/Transforms/Scalar/GVN.h"
39 #include "llvm/Transforms/Vectorize.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/LegacyPassManager.h"
43 #include "llvm/Pass.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Target/TargetLoweringObjectFile.h"
47 #include <memory>
48 
49 using namespace llvm;
50 
51 static cl::opt<bool> EnableR600StructurizeCFG(
52   "r600-ir-structurize",
53   cl::desc("Use StructurizeCFG IR pass"),
54   cl::init(true));
55 
56 static cl::opt<bool> EnableSROA(
57   "amdgpu-sroa",
58   cl::desc("Run SROA after promote alloca pass"),
59   cl::ReallyHidden,
60   cl::init(true));
61 
62 static cl::opt<bool>
63 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
64                         cl::desc("Run early if-conversion"),
65                         cl::init(false));
66 
67 static cl::opt<bool> EnableR600IfConvert(
68   "r600-if-convert",
69   cl::desc("Use if conversion pass"),
70   cl::ReallyHidden,
71   cl::init(true));
72 
73 // Option to disable vectorizer for tests.
74 static cl::opt<bool> EnableLoadStoreVectorizer(
75   "amdgpu-load-store-vectorizer",
76   cl::desc("Enable load store vectorizer"),
77   cl::init(true),
78   cl::Hidden);
79 
80 // Option to to control global loads scalarization
81 static cl::opt<bool> ScalarizeGlobal(
82   "amdgpu-scalarize-global-loads",
83   cl::desc("Enable global load scalarization"),
84   cl::init(false),
85   cl::Hidden);
86 
87 extern "C" void LLVMInitializeAMDGPUTarget() {
88   // Register the target
89   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
90   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
91 
92   PassRegistry *PR = PassRegistry::getPassRegistry();
93   initializeSILowerI1CopiesPass(*PR);
94   initializeSIFixSGPRCopiesPass(*PR);
95   initializeSIFixVGPRCopiesPass(*PR);
96   initializeSIFoldOperandsPass(*PR);
97   initializeSIShrinkInstructionsPass(*PR);
98   initializeSIFixControlFlowLiveIntervalsPass(*PR);
99   initializeSILoadStoreOptimizerPass(*PR);
100   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
101   initializeAMDGPUAnnotateUniformValuesPass(*PR);
102   initializeAMDGPUPromoteAllocaPass(*PR);
103   initializeAMDGPUCodeGenPreparePass(*PR);
104   initializeAMDGPUUnifyMetadataPass(*PR);
105   initializeSIAnnotateControlFlowPass(*PR);
106   initializeSIInsertWaitsPass(*PR);
107   initializeSIWholeQuadModePass(*PR);
108   initializeSILowerControlFlowPass(*PR);
109   initializeSIInsertSkipsPass(*PR);
110   initializeSIDebuggerInsertNopsPass(*PR);
111   initializeSIOptimizeExecMaskingPass(*PR);
112 }
113 
114 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
115   return llvm::make_unique<AMDGPUTargetObjectFile>();
116 }
117 
118 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
119   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
120 }
121 
122 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
123   return new SIScheduleDAGMI(C);
124 }
125 
126 static ScheduleDAGInstrs *
127 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
128   ScheduleDAGMILive *DAG =
129       new ScheduleDAGMILive(C,
130                             llvm::make_unique<GCNMaxOccupancySchedStrategy>(C));
131   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
132   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
133   return DAG;
134 }
135 
136 static MachineSchedRegistry
137 R600SchedRegistry("r600", "Run R600's custom scheduler",
138                    createR600MachineScheduler);
139 
140 static MachineSchedRegistry
141 SISchedRegistry("si", "Run SI's custom scheduler",
142                 createSIMachineScheduler);
143 
144 static MachineSchedRegistry
145 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
146                              "Run GCN scheduler to maximize occupancy",
147                              createGCNMaxOccupancyMachineScheduler);
148 
149 static StringRef computeDataLayout(const Triple &TT) {
150   if (TT.getArch() == Triple::r600) {
151     // 32-bit pointers.
152     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
153             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
154   }
155 
156   // 32-bit private, local, and region pointers. 64-bit global, constant and
157   // flat.
158   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
159          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
160          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
161 }
162 
163 LLVM_READNONE
164 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
165   if (!GPU.empty())
166     return GPU;
167 
168   // HSA only supports CI+, so change the default GPU to a CI for HSA.
169   if (TT.getArch() == Triple::amdgcn)
170     return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
171 
172   return "r600";
173 }
174 
175 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
176   // The AMDGPU toolchain only supports generating shared objects, so we
177   // must always use PIC.
178   return Reloc::PIC_;
179 }
180 
181 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
182                                          StringRef CPU, StringRef FS,
183                                          TargetOptions Options,
184                                          Optional<Reloc::Model> RM,
185                                          CodeModel::Model CM,
186                                          CodeGenOpt::Level OptLevel)
187   : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
188                       FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
189     TLOF(createTLOF(getTargetTriple())) {
190   initAsmInfo();
191 }
192 
193 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
194 
195 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
196   Attribute GPUAttr = F.getFnAttribute("target-cpu");
197   return GPUAttr.hasAttribute(Attribute::None) ?
198     getTargetCPU() : GPUAttr.getValueAsString();
199 }
200 
201 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
202   Attribute FSAttr = F.getFnAttribute("target-features");
203 
204   return FSAttr.hasAttribute(Attribute::None) ?
205     getTargetFeatureString() :
206     FSAttr.getValueAsString();
207 }
208 
209 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
210   Builder.addExtension(
211     PassManagerBuilder::EP_ModuleOptimizerEarly,
212     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
213       PM.add(createAMDGPUUnifyMetadataPass());
214     });
215 }
216 
217 //===----------------------------------------------------------------------===//
218 // R600 Target Machine (R600 -> Cayman)
219 //===----------------------------------------------------------------------===//
220 
221 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
222                                      StringRef CPU, StringRef FS,
223                                      TargetOptions Options,
224                                      Optional<Reloc::Model> RM,
225                                      CodeModel::Model CM, CodeGenOpt::Level OL)
226   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
227   setRequiresStructuredCFG(true);
228 }
229 
230 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
231   const Function &F) const {
232   StringRef GPU = getGPUName(F);
233   StringRef FS = getFeatureString(F);
234 
235   SmallString<128> SubtargetKey(GPU);
236   SubtargetKey.append(FS);
237 
238   auto &I = SubtargetMap[SubtargetKey];
239   if (!I) {
240     // This needs to be done before we create a new subtarget since any
241     // creation will depend on the TM and the code generation flags on the
242     // function that reside in TargetOptions.
243     resetTargetOptions(F);
244     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
245   }
246 
247   return I.get();
248 }
249 
250 //===----------------------------------------------------------------------===//
251 // GCN Target Machine (SI+)
252 //===----------------------------------------------------------------------===//
253 
254 #ifdef LLVM_BUILD_GLOBAL_ISEL
255 namespace {
256 
257 struct SIGISelActualAccessor : public GISelAccessor {
258   std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
259   const AMDGPUCallLowering *getCallLowering() const override {
260     return CallLoweringInfo.get();
261   }
262 };
263 
264 } // end anonymous namespace
265 #endif
266 
267 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
268                                    StringRef CPU, StringRef FS,
269                                    TargetOptions Options,
270                                    Optional<Reloc::Model> RM,
271                                    CodeModel::Model CM, CodeGenOpt::Level OL)
272   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
273 
274 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
275   StringRef GPU = getGPUName(F);
276   StringRef FS = getFeatureString(F);
277 
278   SmallString<128> SubtargetKey(GPU);
279   SubtargetKey.append(FS);
280 
281   auto &I = SubtargetMap[SubtargetKey];
282   if (!I) {
283     // This needs to be done before we create a new subtarget since any
284     // creation will depend on the TM and the code generation flags on the
285     // function that reside in TargetOptions.
286     resetTargetOptions(F);
287     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
288 
289 #ifndef LLVM_BUILD_GLOBAL_ISEL
290     GISelAccessor *GISel = new GISelAccessor();
291 #else
292     SIGISelActualAccessor *GISel = new SIGISelActualAccessor();
293     GISel->CallLoweringInfo.reset(
294       new AMDGPUCallLowering(*I->getTargetLowering()));
295 #endif
296 
297     I->setGISelAccessor(*GISel);
298   }
299 
300   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
301 
302   return I.get();
303 }
304 
305 //===----------------------------------------------------------------------===//
306 // AMDGPU Pass Setup
307 //===----------------------------------------------------------------------===//
308 
309 namespace {
310 
311 class AMDGPUPassConfig : public TargetPassConfig {
312 public:
313   AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
314     : TargetPassConfig(TM, PM) {
315     // Exceptions and StackMaps are not supported, so these passes will never do
316     // anything.
317     disablePass(&StackMapLivenessID);
318     disablePass(&FuncletLayoutID);
319   }
320 
321   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
322     return getTM<AMDGPUTargetMachine>();
323   }
324 
325   ScheduleDAGInstrs *
326   createMachineScheduler(MachineSchedContext *C) const override {
327     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
328     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
329     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
330     return DAG;
331   }
332 
333   void addEarlyCSEOrGVNPass();
334   void addStraightLineScalarOptimizationPasses();
335   void addIRPasses() override;
336   void addCodeGenPrepare() override;
337   bool addPreISel() override;
338   bool addInstSelector() override;
339   bool addGCPasses() override;
340 };
341 
342 class R600PassConfig final : public AMDGPUPassConfig {
343 public:
344   R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
345     : AMDGPUPassConfig(TM, PM) {}
346 
347   ScheduleDAGInstrs *createMachineScheduler(
348     MachineSchedContext *C) const override {
349     return createR600MachineScheduler(C);
350   }
351 
352   bool addPreISel() override;
353   void addPreRegAlloc() override;
354   void addPreSched2() override;
355   void addPreEmitPass() override;
356 };
357 
358 class GCNPassConfig final : public AMDGPUPassConfig {
359 public:
360   GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
361     : AMDGPUPassConfig(TM, PM) {}
362 
363   GCNTargetMachine &getGCNTargetMachine() const {
364     return getTM<GCNTargetMachine>();
365   }
366 
367   ScheduleDAGInstrs *
368   createMachineScheduler(MachineSchedContext *C) const override;
369 
370   void addIRPasses() override;
371   bool addPreISel() override;
372   void addMachineSSAOptimization() override;
373   bool addILPOpts() override;
374   bool addInstSelector() override;
375 #ifdef LLVM_BUILD_GLOBAL_ISEL
376   bool addIRTranslator() override;
377   bool addLegalizeMachineIR() override;
378   bool addRegBankSelect() override;
379   bool addGlobalInstructionSelect() override;
380 #endif
381   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
382   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
383   void addPreRegAlloc() override;
384   void addPostRegAlloc() override;
385   void addPreSched2() override;
386   void addPreEmitPass() override;
387 };
388 
389 } // end anonymous namespace
390 
391 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
392   return TargetIRAnalysis([this](const Function &F) {
393     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
394   });
395 }
396 
397 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
398   if (getOptLevel() == CodeGenOpt::Aggressive)
399     addPass(createGVNPass());
400   else
401     addPass(createEarlyCSEPass());
402 }
403 
404 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
405   addPass(createSeparateConstOffsetFromGEPPass());
406   addPass(createSpeculativeExecutionPass());
407   // ReassociateGEPs exposes more opportunites for SLSR. See
408   // the example in reassociate-geps-and-slsr.ll.
409   addPass(createStraightLineStrengthReducePass());
410   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
411   // EarlyCSE can reuse.
412   addEarlyCSEOrGVNPass();
413   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
414   addPass(createNaryReassociatePass());
415   // NaryReassociate on GEPs creates redundant common expressions, so run
416   // EarlyCSE after it.
417   addPass(createEarlyCSEPass());
418 }
419 
420 void AMDGPUPassConfig::addIRPasses() {
421   // There is no reason to run these.
422   disablePass(&StackMapLivenessID);
423   disablePass(&FuncletLayoutID);
424   disablePass(&PatchableFunctionID);
425 
426   // Function calls are not supported, so make sure we inline everything.
427   addPass(createAMDGPUAlwaysInlinePass());
428   addPass(createAlwaysInlinerLegacyPass());
429   // We need to add the barrier noop pass, otherwise adding the function
430   // inlining pass will cause all of the PassConfigs passes to be run
431   // one function at a time, which means if we have a nodule with two
432   // functions, then we will generate code for the first function
433   // without ever running any passes on the second.
434   addPass(createBarrierNoopPass());
435 
436   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
437   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
438 
439   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
440   if (TM.getOptLevel() > CodeGenOpt::None) {
441     addPass(createAMDGPUPromoteAlloca(&TM));
442 
443     if (EnableSROA)
444       addPass(createSROAPass());
445 
446     addStraightLineScalarOptimizationPasses();
447   }
448 
449   TargetPassConfig::addIRPasses();
450 
451   // EarlyCSE is not always strong enough to clean up what LSR produces. For
452   // example, GVN can combine
453   //
454   //   %0 = add %a, %b
455   //   %1 = add %b, %a
456   //
457   // and
458   //
459   //   %0 = shl nsw %a, 2
460   //   %1 = shl %a, 2
461   //
462   // but EarlyCSE can do neither of them.
463   if (getOptLevel() != CodeGenOpt::None)
464     addEarlyCSEOrGVNPass();
465 }
466 
467 void AMDGPUPassConfig::addCodeGenPrepare() {
468   TargetPassConfig::addCodeGenPrepare();
469 
470   if (EnableLoadStoreVectorizer)
471     addPass(createLoadStoreVectorizerPass());
472 }
473 
474 bool AMDGPUPassConfig::addPreISel() {
475   addPass(createFlattenCFGPass());
476   return false;
477 }
478 
479 bool AMDGPUPassConfig::addInstSelector() {
480   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));
481   return false;
482 }
483 
484 bool AMDGPUPassConfig::addGCPasses() {
485   // Do nothing. GC is not supported.
486   return false;
487 }
488 
489 //===----------------------------------------------------------------------===//
490 // R600 Pass Setup
491 //===----------------------------------------------------------------------===//
492 
493 bool R600PassConfig::addPreISel() {
494   AMDGPUPassConfig::addPreISel();
495 
496   if (EnableR600StructurizeCFG)
497     addPass(createStructurizeCFGPass());
498   return false;
499 }
500 
501 void R600PassConfig::addPreRegAlloc() {
502   addPass(createR600VectorRegMerger(*TM));
503 }
504 
505 void R600PassConfig::addPreSched2() {
506   addPass(createR600EmitClauseMarkers(), false);
507   if (EnableR600IfConvert)
508     addPass(&IfConverterID, false);
509   addPass(createR600ClauseMergePass(*TM), false);
510 }
511 
512 void R600PassConfig::addPreEmitPass() {
513   addPass(createAMDGPUCFGStructurizerPass(), false);
514   addPass(createR600ExpandSpecialInstrsPass(*TM), false);
515   addPass(&FinalizeMachineBundlesID, false);
516   addPass(createR600Packetizer(*TM), false);
517   addPass(createR600ControlFlowFinalizer(*TM), false);
518 }
519 
520 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
521   return new R600PassConfig(this, PM);
522 }
523 
524 //===----------------------------------------------------------------------===//
525 // GCN Pass Setup
526 //===----------------------------------------------------------------------===//
527 
528 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
529   MachineSchedContext *C) const {
530   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
531   if (ST.enableSIScheduler())
532     return createSIMachineScheduler(C);
533   return createGCNMaxOccupancyMachineScheduler(C);
534 }
535 
536 bool GCNPassConfig::addPreISel() {
537   AMDGPUPassConfig::addPreISel();
538 
539   // FIXME: We need to run a pass to propagate the attributes when calls are
540   // supported.
541   addPass(&AMDGPUAnnotateKernelFeaturesID);
542   addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
543   addPass(createSinkingPass());
544   addPass(createSITypeRewriter());
545   addPass(createAMDGPUAnnotateUniformValues());
546   addPass(createSIAnnotateControlFlowPass());
547 
548   return false;
549 }
550 
551 void GCNPassConfig::addMachineSSAOptimization() {
552   TargetPassConfig::addMachineSSAOptimization();
553 
554   // We want to fold operands after PeepholeOptimizer has run (or as part of
555   // it), because it will eliminate extra copies making it easier to fold the
556   // real source operand. We want to eliminate dead instructions after, so that
557   // we see fewer uses of the copies. We then need to clean up the dead
558   // instructions leftover after the operands are folded as well.
559   //
560   // XXX - Can we get away without running DeadMachineInstructionElim again?
561   addPass(&SIFoldOperandsID);
562   addPass(&DeadMachineInstructionElimID);
563   addPass(&SILoadStoreOptimizerID);
564 }
565 
566 bool GCNPassConfig::addILPOpts() {
567   if (EnableEarlyIfConversion)
568     addPass(&EarlyIfConverterID);
569 
570   TargetPassConfig::addILPOpts();
571   return false;
572 }
573 
574 void GCNPassConfig::addIRPasses() {
575   // TODO: May want to move later or split into an early and late one.
576   addPass(createAMDGPUCodeGenPreparePass(&getGCNTargetMachine()));
577 
578   AMDGPUPassConfig::addIRPasses();
579 }
580 
581 bool GCNPassConfig::addInstSelector() {
582   AMDGPUPassConfig::addInstSelector();
583   addPass(createSILowerI1CopiesPass());
584   addPass(&SIFixSGPRCopiesID);
585   return false;
586 }
587 
588 #ifdef LLVM_BUILD_GLOBAL_ISEL
589 bool GCNPassConfig::addIRTranslator() {
590   addPass(new IRTranslator());
591   return false;
592 }
593 
594 bool GCNPassConfig::addLegalizeMachineIR() {
595   return false;
596 }
597 
598 bool GCNPassConfig::addRegBankSelect() {
599   return false;
600 }
601 
602 bool GCNPassConfig::addGlobalInstructionSelect() {
603   return false;
604 }
605 #endif
606 
607 void GCNPassConfig::addPreRegAlloc() {
608   addPass(createSIShrinkInstructionsPass());
609   addPass(createSIWholeQuadModePass());
610 }
611 
612 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
613   // FIXME: We have to disable the verifier here because of PHIElimination +
614   // TwoAddressInstructions disabling it.
615 
616   // This must be run immediately after phi elimination and before
617   // TwoAddressInstructions, otherwise the processing of the tied operand of
618   // SI_ELSE will introduce a copy of the tied operand source after the else.
619   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
620 
621   TargetPassConfig::addFastRegAlloc(RegAllocPass);
622 }
623 
624 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
625   // This needs to be run directly before register allocation because earlier
626   // passes might recompute live intervals.
627   insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
628 
629   // This must be run immediately after phi elimination and before
630   // TwoAddressInstructions, otherwise the processing of the tied operand of
631   // SI_ELSE will introduce a copy of the tied operand source after the else.
632   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
633 
634   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
635 }
636 
637 void GCNPassConfig::addPostRegAlloc() {
638   addPass(&SIFixVGPRCopiesID);
639   addPass(&SIOptimizeExecMaskingID);
640   TargetPassConfig::addPostRegAlloc();
641 }
642 
643 void GCNPassConfig::addPreSched2() {
644 }
645 
646 void GCNPassConfig::addPreEmitPass() {
647   // The hazard recognizer that runs as part of the post-ra scheduler does not
648   // guarantee to be able handle all hazards correctly. This is because if there
649   // are multiple scheduling regions in a basic block, the regions are scheduled
650   // bottom up, so when we begin to schedule a region we don't know what
651   // instructions were emitted directly before it.
652   //
653   // Here we add a stand-alone hazard recognizer pass which can handle all
654   // cases.
655   addPass(&PostRAHazardRecognizerID);
656 
657   addPass(createSIInsertWaitsPass());
658   addPass(createSIShrinkInstructionsPass());
659   addPass(&SIInsertSkipsPassID);
660   addPass(createSIDebuggerInsertNopsPass());
661   addPass(&BranchRelaxationPassID);
662 }
663 
664 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
665   return new GCNPassConfig(this, PM);
666 }
667