1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110   cl::desc("Enable AMDGPU Alias Analysis"),
111   cl::init(true));
112 
113 // Option to enable new waitcnt insertion pass.
114 static cl::opt<bool> EnableSIInsertWaitcntsPass(
115   "enable-si-insert-waitcnts",
116   cl::desc("Use new waitcnt insertion pass"),
117   cl::init(true));
118 
119 // Option to run late CFG structurizer
120 static cl::opt<bool, true> LateCFGStructurize(
121   "amdgpu-late-structurize",
122   cl::desc("Enable late CFG structurization"),
123   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
124   cl::Hidden);
125 
126 static cl::opt<bool> EnableAMDGPUFunctionCalls(
127   "amdgpu-function-calls",
128   cl::Hidden,
129   cl::desc("Enable AMDGPU function call support"),
130   cl::init(false));
131 
132 // Enable lib calls simplifications
133 static cl::opt<bool> EnableLibCallSimplify(
134   "amdgpu-simplify-libcall",
135   cl::desc("Enable mdgpu library simplifications"),
136   cl::init(true),
137   cl::Hidden);
138 
139 extern "C" void LLVMInitializeAMDGPUTarget() {
140   // Register the target
141   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
142   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
143 
144   PassRegistry *PR = PassRegistry::getPassRegistry();
145   initializeR600ClauseMergePassPass(*PR);
146   initializeR600ControlFlowFinalizerPass(*PR);
147   initializeR600PacketizerPass(*PR);
148   initializeR600ExpandSpecialInstrsPassPass(*PR);
149   initializeR600VectorRegMergerPass(*PR);
150   initializeAMDGPUDAGToDAGISelPass(*PR);
151   initializeSILowerI1CopiesPass(*PR);
152   initializeSIFixSGPRCopiesPass(*PR);
153   initializeSIFixVGPRCopiesPass(*PR);
154   initializeSIFoldOperandsPass(*PR);
155   initializeSIPeepholeSDWAPass(*PR);
156   initializeSIShrinkInstructionsPass(*PR);
157   initializeSIOptimizeExecMaskingPreRAPass(*PR);
158   initializeSILoadStoreOptimizerPass(*PR);
159   initializeAMDGPUAlwaysInlinePass(*PR);
160   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
161   initializeAMDGPUAnnotateUniformValuesPass(*PR);
162   initializeAMDGPUArgumentUsageInfoPass(*PR);
163   initializeAMDGPULowerIntrinsicsPass(*PR);
164   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
165   initializeAMDGPUPromoteAllocaPass(*PR);
166   initializeAMDGPUCodeGenPreparePass(*PR);
167   initializeAMDGPURewriteOutArgumentsPass(*PR);
168   initializeAMDGPUUnifyMetadataPass(*PR);
169   initializeSIAnnotateControlFlowPass(*PR);
170   initializeSIInsertWaitsPass(*PR);
171   initializeSIInsertWaitcntsPass(*PR);
172   initializeSIWholeQuadModePass(*PR);
173   initializeSILowerControlFlowPass(*PR);
174   initializeSIInsertSkipsPass(*PR);
175   initializeSIMemoryLegalizerPass(*PR);
176   initializeSIDebuggerInsertNopsPass(*PR);
177   initializeSIOptimizeExecMaskingPass(*PR);
178   initializeSIFixWWMLivenessPass(*PR);
179   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
180   initializeAMDGPUAAWrapperPassPass(*PR);
181   initializeAMDGPUUseNativeCallsPass(*PR);
182   initializeAMDGPUSimplifyLibCallsPass(*PR);
183   initializeAMDGPUInlinerPass(*PR);
184 }
185 
186 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
187   return llvm::make_unique<AMDGPUTargetObjectFile>();
188 }
189 
190 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
191   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
192 }
193 
194 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
195   return new SIScheduleDAGMI(C);
196 }
197 
198 static ScheduleDAGInstrs *
199 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
200   ScheduleDAGMILive *DAG =
201     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
202   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
203   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
204   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
205   return DAG;
206 }
207 
208 static ScheduleDAGInstrs *
209 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
210   auto DAG = new GCNIterativeScheduler(C,
211     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
212   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
213   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
214   return DAG;
215 }
216 
217 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
218   return new GCNIterativeScheduler(C,
219     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
220 }
221 
222 static MachineSchedRegistry
223 R600SchedRegistry("r600", "Run R600's custom scheduler",
224                    createR600MachineScheduler);
225 
226 static MachineSchedRegistry
227 SISchedRegistry("si", "Run SI's custom scheduler",
228                 createSIMachineScheduler);
229 
230 static MachineSchedRegistry
231 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
232                              "Run GCN scheduler to maximize occupancy",
233                              createGCNMaxOccupancyMachineScheduler);
234 
235 static MachineSchedRegistry
236 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
237   "Run GCN scheduler to maximize occupancy (experimental)",
238   createIterativeGCNMaxOccupancyMachineScheduler);
239 
240 static MachineSchedRegistry
241 GCNMinRegSchedRegistry("gcn-minreg",
242   "Run GCN iterative scheduler for minimal register usage (experimental)",
243   createMinRegScheduler);
244 
245 static StringRef computeDataLayout(const Triple &TT) {
246   if (TT.getArch() == Triple::r600) {
247     // 32-bit pointers.
248     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
249             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
250   }
251 
252   // 32-bit private, local, and region pointers. 64-bit global, constant and
253   // flat.
254   if (TT.getEnvironmentName() == "amdgiz" ||
255       TT.getEnvironmentName() == "amdgizcl")
256     return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
257          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
258          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
259   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
260       "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
261       "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
262 }
263 
264 LLVM_READNONE
265 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
266   if (!GPU.empty())
267     return GPU;
268 
269   if (TT.getArch() == Triple::amdgcn)
270     return "generic";
271 
272   return "r600";
273 }
274 
275 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
276   // The AMDGPU toolchain only supports generating shared objects, so we
277   // must always use PIC.
278   return Reloc::PIC_;
279 }
280 
281 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
282   if (CM)
283     return *CM;
284   return CodeModel::Small;
285 }
286 
287 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
288                                          StringRef CPU, StringRef FS,
289                                          TargetOptions Options,
290                                          Optional<Reloc::Model> RM,
291                                          Optional<CodeModel::Model> CM,
292                                          CodeGenOpt::Level OptLevel)
293     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
294                         FS, Options, getEffectiveRelocModel(RM),
295                         getEffectiveCodeModel(CM), OptLevel),
296       TLOF(createTLOF(getTargetTriple())) {
297   AS = AMDGPU::getAMDGPUAS(TT);
298   initAsmInfo();
299 }
300 
301 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
302 
303 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
304 
305 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
306   Attribute GPUAttr = F.getFnAttribute("target-cpu");
307   return GPUAttr.hasAttribute(Attribute::None) ?
308     getTargetCPU() : GPUAttr.getValueAsString();
309 }
310 
311 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
312   Attribute FSAttr = F.getFnAttribute("target-features");
313 
314   return FSAttr.hasAttribute(Attribute::None) ?
315     getTargetFeatureString() :
316     FSAttr.getValueAsString();
317 }
318 
319 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
320   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
321       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
322         AAR.addAAResult(WrapperPass->getResult());
323       });
324 }
325 
326 /// Predicate for Internalize pass.
327 bool mustPreserveGV(const GlobalValue &GV) {
328   if (const Function *F = dyn_cast<Function>(&GV))
329     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
330 
331   return !GV.use_empty();
332 }
333 
334 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
335   Builder.DivergentTarget = true;
336 
337   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
338   bool Internalize = InternalizeSymbols;
339   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
340   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
341   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
342 
343   if (EnableAMDGPUFunctionCalls) {
344     delete Builder.Inliner;
345     Builder.Inliner = createAMDGPUFunctionInliningPass();
346   }
347 
348   if (Internalize) {
349     // If we're generating code, we always have the whole program available. The
350     // relocations expected for externally visible functions aren't supported,
351     // so make sure every non-entry function is hidden.
352     Builder.addExtension(
353       PassManagerBuilder::EP_EnabledOnOptLevel0,
354       [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
355         PM.add(createInternalizePass(mustPreserveGV));
356       });
357   }
358 
359   Builder.addExtension(
360     PassManagerBuilder::EP_ModuleOptimizerEarly,
361     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
362                                          legacy::PassManagerBase &PM) {
363       if (AMDGPUAA) {
364         PM.add(createAMDGPUAAWrapperPass());
365         PM.add(createAMDGPUExternalAAWrapperPass());
366       }
367       PM.add(createAMDGPUUnifyMetadataPass());
368       if (Internalize) {
369         PM.add(createInternalizePass(mustPreserveGV));
370         PM.add(createGlobalDCEPass());
371       }
372       if (EarlyInline)
373         PM.add(createAMDGPUAlwaysInlinePass(false));
374   });
375 
376   const auto &Opt = Options;
377   Builder.addExtension(
378     PassManagerBuilder::EP_EarlyAsPossible,
379     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
380                                       legacy::PassManagerBase &PM) {
381       if (AMDGPUAA) {
382         PM.add(createAMDGPUAAWrapperPass());
383         PM.add(createAMDGPUExternalAAWrapperPass());
384       }
385       PM.add(llvm::createAMDGPUUseNativeCallsPass());
386       if (LibCallSimplify)
387         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
388   });
389 
390   Builder.addExtension(
391     PassManagerBuilder::EP_CGSCCOptimizerLate,
392     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
393       // Add infer address spaces pass to the opt pipeline after inlining
394       // but before SROA to increase SROA opportunities.
395       PM.add(createInferAddressSpacesPass());
396   });
397 }
398 
399 //===----------------------------------------------------------------------===//
400 // R600 Target Machine (R600 -> Cayman)
401 //===----------------------------------------------------------------------===//
402 
403 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
404                                      StringRef CPU, StringRef FS,
405                                      TargetOptions Options,
406                                      Optional<Reloc::Model> RM,
407                                      Optional<CodeModel::Model> CM,
408                                      CodeGenOpt::Level OL, bool JIT)
409     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
410   setRequiresStructuredCFG(true);
411 }
412 
413 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
414   const Function &F) const {
415   StringRef GPU = getGPUName(F);
416   StringRef FS = getFeatureString(F);
417 
418   SmallString<128> SubtargetKey(GPU);
419   SubtargetKey.append(FS);
420 
421   auto &I = SubtargetMap[SubtargetKey];
422   if (!I) {
423     // This needs to be done before we create a new subtarget since any
424     // creation will depend on the TM and the code generation flags on the
425     // function that reside in TargetOptions.
426     resetTargetOptions(F);
427     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
428   }
429 
430   return I.get();
431 }
432 
433 //===----------------------------------------------------------------------===//
434 // GCN Target Machine (SI+)
435 //===----------------------------------------------------------------------===//
436 
437 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
438                                    StringRef CPU, StringRef FS,
439                                    TargetOptions Options,
440                                    Optional<Reloc::Model> RM,
441                                    Optional<CodeModel::Model> CM,
442                                    CodeGenOpt::Level OL, bool JIT)
443     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
444 
445 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
446   StringRef GPU = getGPUName(F);
447   StringRef FS = getFeatureString(F);
448 
449   SmallString<128> SubtargetKey(GPU);
450   SubtargetKey.append(FS);
451 
452   auto &I = SubtargetMap[SubtargetKey];
453   if (!I) {
454     // This needs to be done before we create a new subtarget since any
455     // creation will depend on the TM and the code generation flags on the
456     // function that reside in TargetOptions.
457     resetTargetOptions(F);
458     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
459   }
460 
461   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
462 
463   return I.get();
464 }
465 
466 //===----------------------------------------------------------------------===//
467 // AMDGPU Pass Setup
468 //===----------------------------------------------------------------------===//
469 
470 namespace {
471 
472 class AMDGPUPassConfig : public TargetPassConfig {
473 public:
474   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
475     : TargetPassConfig(TM, PM) {
476     // Exceptions and StackMaps are not supported, so these passes will never do
477     // anything.
478     disablePass(&StackMapLivenessID);
479     disablePass(&FuncletLayoutID);
480   }
481 
482   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
483     return getTM<AMDGPUTargetMachine>();
484   }
485 
486   ScheduleDAGInstrs *
487   createMachineScheduler(MachineSchedContext *C) const override {
488     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
489     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
490     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
491     return DAG;
492   }
493 
494   void addEarlyCSEOrGVNPass();
495   void addStraightLineScalarOptimizationPasses();
496   void addIRPasses() override;
497   void addCodeGenPrepare() override;
498   bool addPreISel() override;
499   bool addInstSelector() override;
500   bool addGCPasses() override;
501 };
502 
503 class R600PassConfig final : public AMDGPUPassConfig {
504 public:
505   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
506     : AMDGPUPassConfig(TM, PM) {}
507 
508   ScheduleDAGInstrs *createMachineScheduler(
509     MachineSchedContext *C) const override {
510     return createR600MachineScheduler(C);
511   }
512 
513   bool addPreISel() override;
514   bool addInstSelector() override;
515   void addPreRegAlloc() override;
516   void addPreSched2() override;
517   void addPreEmitPass() override;
518 };
519 
520 class GCNPassConfig final : public AMDGPUPassConfig {
521 public:
522   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
523     : AMDGPUPassConfig(TM, PM) {
524     // It is necessary to know the register usage of the entire call graph.  We
525     // allow calls without EnableAMDGPUFunctionCalls if they are marked
526     // noinline, so this is always required.
527     setRequiresCodeGenSCCOrder(true);
528   }
529 
530   GCNTargetMachine &getGCNTargetMachine() const {
531     return getTM<GCNTargetMachine>();
532   }
533 
534   ScheduleDAGInstrs *
535   createMachineScheduler(MachineSchedContext *C) const override;
536 
537   bool addPreISel() override;
538   void addMachineSSAOptimization() override;
539   bool addILPOpts() override;
540   bool addInstSelector() override;
541   bool addIRTranslator() override;
542   bool addLegalizeMachineIR() override;
543   bool addRegBankSelect() override;
544   bool addGlobalInstructionSelect() override;
545   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
546   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
547   void addPreRegAlloc() override;
548   void addPostRegAlloc() override;
549   void addPreSched2() override;
550   void addPreEmitPass() override;
551 };
552 
553 } // end anonymous namespace
554 
555 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
556   return TargetIRAnalysis([this](const Function &F) {
557     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
558   });
559 }
560 
561 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
562   if (getOptLevel() == CodeGenOpt::Aggressive)
563     addPass(createGVNPass());
564   else
565     addPass(createEarlyCSEPass());
566 }
567 
568 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
569   addPass(createSeparateConstOffsetFromGEPPass());
570   addPass(createSpeculativeExecutionPass());
571   // ReassociateGEPs exposes more opportunites for SLSR. See
572   // the example in reassociate-geps-and-slsr.ll.
573   addPass(createStraightLineStrengthReducePass());
574   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
575   // EarlyCSE can reuse.
576   addEarlyCSEOrGVNPass();
577   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
578   addPass(createNaryReassociatePass());
579   // NaryReassociate on GEPs creates redundant common expressions, so run
580   // EarlyCSE after it.
581   addPass(createEarlyCSEPass());
582 }
583 
584 void AMDGPUPassConfig::addIRPasses() {
585   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
586 
587   // There is no reason to run these.
588   disablePass(&StackMapLivenessID);
589   disablePass(&FuncletLayoutID);
590   disablePass(&PatchableFunctionID);
591 
592   addPass(createAMDGPULowerIntrinsicsPass());
593 
594   if (TM.getTargetTriple().getArch() == Triple::r600 ||
595       !EnableAMDGPUFunctionCalls) {
596     // Function calls are not supported, so make sure we inline everything.
597     addPass(createAMDGPUAlwaysInlinePass());
598     addPass(createAlwaysInlinerLegacyPass());
599     // We need to add the barrier noop pass, otherwise adding the function
600     // inlining pass will cause all of the PassConfigs passes to be run
601     // one function at a time, which means if we have a nodule with two
602     // functions, then we will generate code for the first function
603     // without ever running any passes on the second.
604     addPass(createBarrierNoopPass());
605   }
606 
607   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
608     // TODO: May want to move later or split into an early and late one.
609 
610     addPass(createAMDGPUCodeGenPreparePass());
611   }
612 
613   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
614   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
615 
616   // Replace OpenCL enqueued block function pointers with global variables.
617   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
618 
619   if (TM.getOptLevel() > CodeGenOpt::None) {
620     addPass(createInferAddressSpacesPass());
621     addPass(createAMDGPUPromoteAlloca());
622 
623     if (EnableSROA)
624       addPass(createSROAPass());
625 
626     addStraightLineScalarOptimizationPasses();
627 
628     if (EnableAMDGPUAliasAnalysis) {
629       addPass(createAMDGPUAAWrapperPass());
630       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
631                                              AAResults &AAR) {
632         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
633           AAR.addAAResult(WrapperPass->getResult());
634         }));
635     }
636   }
637 
638   TargetPassConfig::addIRPasses();
639 
640   // EarlyCSE is not always strong enough to clean up what LSR produces. For
641   // example, GVN can combine
642   //
643   //   %0 = add %a, %b
644   //   %1 = add %b, %a
645   //
646   // and
647   //
648   //   %0 = shl nsw %a, 2
649   //   %1 = shl %a, 2
650   //
651   // but EarlyCSE can do neither of them.
652   if (getOptLevel() != CodeGenOpt::None)
653     addEarlyCSEOrGVNPass();
654 }
655 
656 void AMDGPUPassConfig::addCodeGenPrepare() {
657   TargetPassConfig::addCodeGenPrepare();
658 
659   if (EnableLoadStoreVectorizer)
660     addPass(createLoadStoreVectorizerPass());
661 }
662 
663 bool AMDGPUPassConfig::addPreISel() {
664   addPass(createFlattenCFGPass());
665   return false;
666 }
667 
668 bool AMDGPUPassConfig::addInstSelector() {
669   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
670   return false;
671 }
672 
673 bool AMDGPUPassConfig::addGCPasses() {
674   // Do nothing. GC is not supported.
675   return false;
676 }
677 
678 //===----------------------------------------------------------------------===//
679 // R600 Pass Setup
680 //===----------------------------------------------------------------------===//
681 
682 bool R600PassConfig::addPreISel() {
683   AMDGPUPassConfig::addPreISel();
684 
685   if (EnableR600StructurizeCFG)
686     addPass(createStructurizeCFGPass());
687   return false;
688 }
689 
690 bool R600PassConfig::addInstSelector() {
691   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
692   return false;
693 }
694 
695 void R600PassConfig::addPreRegAlloc() {
696   addPass(createR600VectorRegMerger());
697 }
698 
699 void R600PassConfig::addPreSched2() {
700   addPass(createR600EmitClauseMarkers(), false);
701   if (EnableR600IfConvert)
702     addPass(&IfConverterID, false);
703   addPass(createR600ClauseMergePass(), false);
704 }
705 
706 void R600PassConfig::addPreEmitPass() {
707   addPass(createAMDGPUCFGStructurizerPass(), false);
708   addPass(createR600ExpandSpecialInstrsPass(), false);
709   addPass(&FinalizeMachineBundlesID, false);
710   addPass(createR600Packetizer(), false);
711   addPass(createR600ControlFlowFinalizer(), false);
712 }
713 
714 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
715   return new R600PassConfig(*this, PM);
716 }
717 
718 //===----------------------------------------------------------------------===//
719 // GCN Pass Setup
720 //===----------------------------------------------------------------------===//
721 
722 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
723   MachineSchedContext *C) const {
724   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
725   if (ST.enableSIScheduler())
726     return createSIMachineScheduler(C);
727   return createGCNMaxOccupancyMachineScheduler(C);
728 }
729 
730 bool GCNPassConfig::addPreISel() {
731   AMDGPUPassConfig::addPreISel();
732 
733   // FIXME: We need to run a pass to propagate the attributes when calls are
734   // supported.
735   addPass(createAMDGPUAnnotateKernelFeaturesPass());
736 
737   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
738   // regions formed by them.
739   addPass(&AMDGPUUnifyDivergentExitNodesID);
740   if (!LateCFGStructurize) {
741     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
742   }
743   addPass(createSinkingPass());
744   addPass(createAMDGPUAnnotateUniformValues());
745   if (!LateCFGStructurize) {
746     addPass(createSIAnnotateControlFlowPass());
747   }
748 
749   return false;
750 }
751 
752 void GCNPassConfig::addMachineSSAOptimization() {
753   TargetPassConfig::addMachineSSAOptimization();
754 
755   // We want to fold operands after PeepholeOptimizer has run (or as part of
756   // it), because it will eliminate extra copies making it easier to fold the
757   // real source operand. We want to eliminate dead instructions after, so that
758   // we see fewer uses of the copies. We then need to clean up the dead
759   // instructions leftover after the operands are folded as well.
760   //
761   // XXX - Can we get away without running DeadMachineInstructionElim again?
762   addPass(&SIFoldOperandsID);
763   addPass(&DeadMachineInstructionElimID);
764   addPass(&SILoadStoreOptimizerID);
765   if (EnableSDWAPeephole) {
766     addPass(&SIPeepholeSDWAID);
767     addPass(&MachineLICMID);
768     addPass(&MachineCSEID);
769     addPass(&SIFoldOperandsID);
770     addPass(&DeadMachineInstructionElimID);
771   }
772   addPass(createSIShrinkInstructionsPass());
773 }
774 
775 bool GCNPassConfig::addILPOpts() {
776   if (EnableEarlyIfConversion)
777     addPass(&EarlyIfConverterID);
778 
779   TargetPassConfig::addILPOpts();
780   return false;
781 }
782 
783 bool GCNPassConfig::addInstSelector() {
784   AMDGPUPassConfig::addInstSelector();
785   addPass(createSILowerI1CopiesPass());
786   addPass(&SIFixSGPRCopiesID);
787   return false;
788 }
789 
790 bool GCNPassConfig::addIRTranslator() {
791   addPass(new IRTranslator());
792   return false;
793 }
794 
795 bool GCNPassConfig::addLegalizeMachineIR() {
796   addPass(new Legalizer());
797   return false;
798 }
799 
800 bool GCNPassConfig::addRegBankSelect() {
801   addPass(new RegBankSelect());
802   return false;
803 }
804 
805 bool GCNPassConfig::addGlobalInstructionSelect() {
806   addPass(new InstructionSelect());
807   return false;
808 }
809 
810 void GCNPassConfig::addPreRegAlloc() {
811   if (LateCFGStructurize) {
812     addPass(createAMDGPUMachineCFGStructurizerPass());
813   }
814   addPass(createSIWholeQuadModePass());
815 }
816 
817 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
818   // FIXME: We have to disable the verifier here because of PHIElimination +
819   // TwoAddressInstructions disabling it.
820 
821   // This must be run immediately after phi elimination and before
822   // TwoAddressInstructions, otherwise the processing of the tied operand of
823   // SI_ELSE will introduce a copy of the tied operand source after the else.
824   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
825 
826   // This must be run after SILowerControlFlow, since it needs to use the
827   // machine-level CFG, but before register allocation.
828   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
829 
830   TargetPassConfig::addFastRegAlloc(RegAllocPass);
831 }
832 
833 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
834   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
835 
836   // This must be run immediately after phi elimination and before
837   // TwoAddressInstructions, otherwise the processing of the tied operand of
838   // SI_ELSE will introduce a copy of the tied operand source after the else.
839   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
840 
841   // This must be run after SILowerControlFlow, since it needs to use the
842   // machine-level CFG, but before register allocation.
843   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
844 
845   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
846 }
847 
848 void GCNPassConfig::addPostRegAlloc() {
849   addPass(&SIFixVGPRCopiesID);
850   addPass(&SIOptimizeExecMaskingID);
851   TargetPassConfig::addPostRegAlloc();
852 }
853 
854 void GCNPassConfig::addPreSched2() {
855 }
856 
857 void GCNPassConfig::addPreEmitPass() {
858   // The hazard recognizer that runs as part of the post-ra scheduler does not
859   // guarantee to be able handle all hazards correctly. This is because if there
860   // are multiple scheduling regions in a basic block, the regions are scheduled
861   // bottom up, so when we begin to schedule a region we don't know what
862   // instructions were emitted directly before it.
863   //
864   // Here we add a stand-alone hazard recognizer pass which can handle all
865   // cases.
866   addPass(&PostRAHazardRecognizerID);
867 
868   if (EnableSIInsertWaitcntsPass)
869     addPass(createSIInsertWaitcntsPass());
870   else
871     addPass(createSIInsertWaitsPass());
872   addPass(createSIShrinkInstructionsPass());
873   addPass(&SIInsertSkipsPassID);
874   addPass(createSIMemoryLegalizerPass());
875   addPass(createSIDebuggerInsertNopsPass());
876   addPass(&BranchRelaxationPassID);
877 }
878 
879 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
880   return new GCNPassConfig(*this, PM);
881 }
882 
883