1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUInstructionSelector.h"
20 #include "AMDGPULegalizerInfo.h"
21 #include "AMDGPUMacroFusion.h"
22 #include "AMDGPUTargetObjectFile.h"
23 #include "AMDGPUTargetTransformInfo.h"
24 #include "GCNIterativeScheduler.h"
25 #include "GCNSchedStrategy.h"
26 #include "R600MachineScheduler.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIMachineScheduler.h"
29 #include "TargetInfo/AMDGPUTargetInfo.h"
30 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
31 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
32 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MIRParser/MIParser.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/TargetPassConfig.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/LegacyPassManager.h"
40 #include "llvm/Pass.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/TargetRegistry.h"
44 #include "llvm/Target/TargetLoweringObjectFile.h"
45 #include "llvm/Transforms/IPO.h"
46 #include "llvm/Transforms/IPO/AlwaysInliner.h"
47 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
48 #include "llvm/Transforms/Scalar.h"
49 #include "llvm/Transforms/Scalar/GVN.h"
50 #include "llvm/Transforms/Utils.h"
51 #include "llvm/Transforms/Vectorize.h"
52 #include <memory>
53 
54 using namespace llvm;
55 
56 static cl::opt<bool> EnableR600StructurizeCFG(
57   "r600-ir-structurize",
58   cl::desc("Use StructurizeCFG IR pass"),
59   cl::init(true));
60 
61 static cl::opt<bool> EnableSROA(
62   "amdgpu-sroa",
63   cl::desc("Run SROA after promote alloca pass"),
64   cl::ReallyHidden,
65   cl::init(true));
66 
67 static cl::opt<bool>
68 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
69                         cl::desc("Run early if-conversion"),
70                         cl::init(false));
71 
72 static cl::opt<bool>
73 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
74             cl::desc("Run pre-RA exec mask optimizations"),
75             cl::init(true));
76 
77 static cl::opt<bool> EnableR600IfConvert(
78   "r600-if-convert",
79   cl::desc("Use if conversion pass"),
80   cl::ReallyHidden,
81   cl::init(true));
82 
83 // Option to disable vectorizer for tests.
84 static cl::opt<bool> EnableLoadStoreVectorizer(
85   "amdgpu-load-store-vectorizer",
86   cl::desc("Enable load store vectorizer"),
87   cl::init(true),
88   cl::Hidden);
89 
90 // Option to control global loads scalarization
91 static cl::opt<bool> ScalarizeGlobal(
92   "amdgpu-scalarize-global-loads",
93   cl::desc("Enable global load scalarization"),
94   cl::init(true),
95   cl::Hidden);
96 
97 // Option to run internalize pass.
98 static cl::opt<bool> InternalizeSymbols(
99   "amdgpu-internalize-symbols",
100   cl::desc("Enable elimination of non-kernel functions and unused globals"),
101   cl::init(false),
102   cl::Hidden);
103 
104 // Option to inline all early.
105 static cl::opt<bool> EarlyInlineAll(
106   "amdgpu-early-inline-all",
107   cl::desc("Inline all functions early"),
108   cl::init(false),
109   cl::Hidden);
110 
111 static cl::opt<bool> EnableSDWAPeephole(
112   "amdgpu-sdwa-peephole",
113   cl::desc("Enable SDWA peepholer"),
114   cl::init(true));
115 
116 static cl::opt<bool> EnableDPPCombine(
117   "amdgpu-dpp-combine",
118   cl::desc("Enable DPP combiner"),
119   cl::init(true));
120 
121 // Enable address space based alias analysis
122 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
123   cl::desc("Enable AMDGPU Alias Analysis"),
124   cl::init(true));
125 
126 // Option to run late CFG structurizer
127 static cl::opt<bool, true> LateCFGStructurize(
128   "amdgpu-late-structurize",
129   cl::desc("Enable late CFG structurization"),
130   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
131   cl::Hidden);
132 
133 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
134   "amdgpu-function-calls",
135   cl::desc("Enable AMDGPU function call support"),
136   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
137   cl::init(true),
138   cl::Hidden);
139 
140 // Enable lib calls simplifications
141 static cl::opt<bool> EnableLibCallSimplify(
142   "amdgpu-simplify-libcall",
143   cl::desc("Enable amdgpu library simplifications"),
144   cl::init(true),
145   cl::Hidden);
146 
147 static cl::opt<bool> EnableLowerKernelArguments(
148   "amdgpu-ir-lower-kernel-arguments",
149   cl::desc("Lower kernel argument loads in IR pass"),
150   cl::init(true),
151   cl::Hidden);
152 
153 static cl::opt<bool> EnableRegReassign(
154   "amdgpu-reassign-regs",
155   cl::desc("Enable register reassign optimizations on gfx10+"),
156   cl::init(true),
157   cl::Hidden);
158 
159 // Enable atomic optimization
160 static cl::opt<bool> EnableAtomicOptimizations(
161   "amdgpu-atomic-optimizations",
162   cl::desc("Enable atomic optimizations"),
163   cl::init(false),
164   cl::Hidden);
165 
166 // Enable Mode register optimization
167 static cl::opt<bool> EnableSIModeRegisterPass(
168   "amdgpu-mode-register",
169   cl::desc("Enable mode register pass"),
170   cl::init(true),
171   cl::Hidden);
172 
173 // Option is used in lit tests to prevent deadcoding of patterns inspected.
174 static cl::opt<bool>
175 EnableDCEInRA("amdgpu-dce-in-ra",
176     cl::init(true), cl::Hidden,
177     cl::desc("Enable machine DCE inside regalloc"));
178 
179 static cl::opt<bool> EnableScalarIRPasses(
180   "amdgpu-scalar-ir-passes",
181   cl::desc("Enable scalar IR passes"),
182   cl::init(true),
183   cl::Hidden);
184 
185 extern "C" void LLVMInitializeAMDGPUTarget() {
186   // Register the target
187   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
188   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
189 
190   PassRegistry *PR = PassRegistry::getPassRegistry();
191   initializeR600ClauseMergePassPass(*PR);
192   initializeR600ControlFlowFinalizerPass(*PR);
193   initializeR600PacketizerPass(*PR);
194   initializeR600ExpandSpecialInstrsPassPass(*PR);
195   initializeR600VectorRegMergerPass(*PR);
196   initializeGlobalISel(*PR);
197   initializeAMDGPUDAGToDAGISelPass(*PR);
198   initializeGCNDPPCombinePass(*PR);
199   initializeSILowerI1CopiesPass(*PR);
200   initializeSILowerSGPRSpillsPass(*PR);
201   initializeSIFixSGPRCopiesPass(*PR);
202   initializeSIFixVGPRCopiesPass(*PR);
203   initializeSIFixupVectorISelPass(*PR);
204   initializeSIFoldOperandsPass(*PR);
205   initializeSIPeepholeSDWAPass(*PR);
206   initializeSIShrinkInstructionsPass(*PR);
207   initializeSIOptimizeExecMaskingPreRAPass(*PR);
208   initializeSILoadStoreOptimizerPass(*PR);
209   initializeAMDGPUFixFunctionBitcastsPass(*PR);
210   initializeAMDGPUAlwaysInlinePass(*PR);
211   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
212   initializeAMDGPUAnnotateUniformValuesPass(*PR);
213   initializeAMDGPUArgumentUsageInfoPass(*PR);
214   initializeAMDGPUAtomicOptimizerPass(*PR);
215   initializeAMDGPULowerKernelArgumentsPass(*PR);
216   initializeAMDGPULowerKernelAttributesPass(*PR);
217   initializeAMDGPULowerIntrinsicsPass(*PR);
218   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
219   initializeAMDGPUPromoteAllocaPass(*PR);
220   initializeAMDGPUCodeGenPreparePass(*PR);
221   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
222   initializeAMDGPUPropagateAttributesLatePass(*PR);
223   initializeAMDGPURewriteOutArgumentsPass(*PR);
224   initializeAMDGPUUnifyMetadataPass(*PR);
225   initializeSIAnnotateControlFlowPass(*PR);
226   initializeSIInsertWaitcntsPass(*PR);
227   initializeSIModeRegisterPass(*PR);
228   initializeSIWholeQuadModePass(*PR);
229   initializeSILowerControlFlowPass(*PR);
230   initializeSIInsertSkipsPass(*PR);
231   initializeSIMemoryLegalizerPass(*PR);
232   initializeSIOptimizeExecMaskingPass(*PR);
233   initializeSIPreAllocateWWMRegsPass(*PR);
234   initializeSIFormMemoryClausesPass(*PR);
235   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
236   initializeAMDGPUAAWrapperPassPass(*PR);
237   initializeAMDGPUExternalAAWrapperPass(*PR);
238   initializeAMDGPUUseNativeCallsPass(*PR);
239   initializeAMDGPUSimplifyLibCallsPass(*PR);
240   initializeAMDGPUInlinerPass(*PR);
241   initializeGCNRegBankReassignPass(*PR);
242   initializeGCNNSAReassignPass(*PR);
243 }
244 
245 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
246   return llvm::make_unique<AMDGPUTargetObjectFile>();
247 }
248 
249 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
250   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
251 }
252 
253 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
254   return new SIScheduleDAGMI(C);
255 }
256 
257 static ScheduleDAGInstrs *
258 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
259   ScheduleDAGMILive *DAG =
260     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
261   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
262   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
263   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
264   return DAG;
265 }
266 
267 static ScheduleDAGInstrs *
268 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
269   auto DAG = new GCNIterativeScheduler(C,
270     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
271   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
272   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
273   return DAG;
274 }
275 
276 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
277   return new GCNIterativeScheduler(C,
278     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
279 }
280 
281 static ScheduleDAGInstrs *
282 createIterativeILPMachineScheduler(MachineSchedContext *C) {
283   auto DAG = new GCNIterativeScheduler(C,
284     GCNIterativeScheduler::SCHEDULE_ILP);
285   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
286   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
287   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
288   return DAG;
289 }
290 
291 static MachineSchedRegistry
292 R600SchedRegistry("r600", "Run R600's custom scheduler",
293                    createR600MachineScheduler);
294 
295 static MachineSchedRegistry
296 SISchedRegistry("si", "Run SI's custom scheduler",
297                 createSIMachineScheduler);
298 
299 static MachineSchedRegistry
300 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
301                              "Run GCN scheduler to maximize occupancy",
302                              createGCNMaxOccupancyMachineScheduler);
303 
304 static MachineSchedRegistry
305 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
306   "Run GCN scheduler to maximize occupancy (experimental)",
307   createIterativeGCNMaxOccupancyMachineScheduler);
308 
309 static MachineSchedRegistry
310 GCNMinRegSchedRegistry("gcn-minreg",
311   "Run GCN iterative scheduler for minimal register usage (experimental)",
312   createMinRegScheduler);
313 
314 static MachineSchedRegistry
315 GCNILPSchedRegistry("gcn-ilp",
316   "Run GCN iterative scheduler for ILP scheduling (experimental)",
317   createIterativeILPMachineScheduler);
318 
319 static StringRef computeDataLayout(const Triple &TT) {
320   if (TT.getArch() == Triple::r600) {
321     // 32-bit pointers.
322       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
323              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
324   }
325 
326   // 32-bit private, local, and region pointers. 64-bit global, constant and
327   // flat, non-integral buffer fat pointers.
328     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
329          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
330          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
331          "-ni:7";
332 }
333 
334 LLVM_READNONE
335 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
336   if (!GPU.empty())
337     return GPU;
338 
339   // Need to default to a target with flat support for HSA.
340   if (TT.getArch() == Triple::amdgcn)
341     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
342 
343   return "r600";
344 }
345 
346 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
347   // The AMDGPU toolchain only supports generating shared objects, so we
348   // must always use PIC.
349   return Reloc::PIC_;
350 }
351 
352 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
353                                          StringRef CPU, StringRef FS,
354                                          TargetOptions Options,
355                                          Optional<Reloc::Model> RM,
356                                          Optional<CodeModel::Model> CM,
357                                          CodeGenOpt::Level OptLevel)
358     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
359                         FS, Options, getEffectiveRelocModel(RM),
360                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
361       TLOF(createTLOF(getTargetTriple())) {
362   initAsmInfo();
363 }
364 
365 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
366 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
367 
368 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
369 
370 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
371   Attribute GPUAttr = F.getFnAttribute("target-cpu");
372   return GPUAttr.hasAttribute(Attribute::None) ?
373     getTargetCPU() : GPUAttr.getValueAsString();
374 }
375 
376 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
377   Attribute FSAttr = F.getFnAttribute("target-features");
378 
379   return FSAttr.hasAttribute(Attribute::None) ?
380     getTargetFeatureString() :
381     FSAttr.getValueAsString();
382 }
383 
384 /// Predicate for Internalize pass.
385 static bool mustPreserveGV(const GlobalValue &GV) {
386   if (const Function *F = dyn_cast<Function>(&GV))
387     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
388 
389   return !GV.use_empty();
390 }
391 
392 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
393   Builder.DivergentTarget = true;
394 
395   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
396   bool Internalize = InternalizeSymbols;
397   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
398   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
399   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
400 
401   if (EnableFunctionCalls) {
402     delete Builder.Inliner;
403     Builder.Inliner = createAMDGPUFunctionInliningPass();
404   }
405 
406   Builder.addExtension(
407     PassManagerBuilder::EP_ModuleOptimizerEarly,
408     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
409                                                legacy::PassManagerBase &PM) {
410       if (AMDGPUAA) {
411         PM.add(createAMDGPUAAWrapperPass());
412         PM.add(createAMDGPUExternalAAWrapperPass());
413       }
414       PM.add(createAMDGPUUnifyMetadataPass());
415       PM.add(createAMDGPUPropagateAttributesLatePass(this));
416       if (Internalize) {
417         PM.add(createInternalizePass(mustPreserveGV));
418         PM.add(createGlobalDCEPass());
419       }
420       if (EarlyInline)
421         PM.add(createAMDGPUAlwaysInlinePass(false));
422   });
423 
424   const auto &Opt = Options;
425   Builder.addExtension(
426     PassManagerBuilder::EP_EarlyAsPossible,
427     [AMDGPUAA, LibCallSimplify, &Opt, this](const PassManagerBuilder &,
428                                             legacy::PassManagerBase &PM) {
429       if (AMDGPUAA) {
430         PM.add(createAMDGPUAAWrapperPass());
431         PM.add(createAMDGPUExternalAAWrapperPass());
432       }
433       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
434       PM.add(llvm::createAMDGPUUseNativeCallsPass());
435       if (LibCallSimplify)
436         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt, this));
437   });
438 
439   Builder.addExtension(
440     PassManagerBuilder::EP_CGSCCOptimizerLate,
441     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
442       // Add infer address spaces pass to the opt pipeline after inlining
443       // but before SROA to increase SROA opportunities.
444       PM.add(createInferAddressSpacesPass());
445 
446       // This should run after inlining to have any chance of doing anything,
447       // and before other cleanup optimizations.
448       PM.add(createAMDGPULowerKernelAttributesPass());
449   });
450 }
451 
452 //===----------------------------------------------------------------------===//
453 // R600 Target Machine (R600 -> Cayman)
454 //===----------------------------------------------------------------------===//
455 
456 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
457                                      StringRef CPU, StringRef FS,
458                                      TargetOptions Options,
459                                      Optional<Reloc::Model> RM,
460                                      Optional<CodeModel::Model> CM,
461                                      CodeGenOpt::Level OL, bool JIT)
462     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
463   setRequiresStructuredCFG(true);
464 
465   // Override the default since calls aren't supported for r600.
466   if (EnableFunctionCalls &&
467       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
468     EnableFunctionCalls = false;
469 }
470 
471 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
472   const Function &F) const {
473   StringRef GPU = getGPUName(F);
474   StringRef FS = getFeatureString(F);
475 
476   SmallString<128> SubtargetKey(GPU);
477   SubtargetKey.append(FS);
478 
479   auto &I = SubtargetMap[SubtargetKey];
480   if (!I) {
481     // This needs to be done before we create a new subtarget since any
482     // creation will depend on the TM and the code generation flags on the
483     // function that reside in TargetOptions.
484     resetTargetOptions(F);
485     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
486   }
487 
488   return I.get();
489 }
490 
491 TargetTransformInfo
492 R600TargetMachine::getTargetTransformInfo(const Function &F) {
493   return TargetTransformInfo(R600TTIImpl(this, F));
494 }
495 
496 //===----------------------------------------------------------------------===//
497 // GCN Target Machine (SI+)
498 //===----------------------------------------------------------------------===//
499 
500 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
501                                    StringRef CPU, StringRef FS,
502                                    TargetOptions Options,
503                                    Optional<Reloc::Model> RM,
504                                    Optional<CodeModel::Model> CM,
505                                    CodeGenOpt::Level OL, bool JIT)
506     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
507 
508 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
509   StringRef GPU = getGPUName(F);
510   StringRef FS = getFeatureString(F);
511 
512   SmallString<128> SubtargetKey(GPU);
513   SubtargetKey.append(FS);
514 
515   auto &I = SubtargetMap[SubtargetKey];
516   if (!I) {
517     // This needs to be done before we create a new subtarget since any
518     // creation will depend on the TM and the code generation flags on the
519     // function that reside in TargetOptions.
520     resetTargetOptions(F);
521     I = llvm::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
522   }
523 
524   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
525 
526   return I.get();
527 }
528 
529 TargetTransformInfo
530 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
531   return TargetTransformInfo(GCNTTIImpl(this, F));
532 }
533 
534 //===----------------------------------------------------------------------===//
535 // AMDGPU Pass Setup
536 //===----------------------------------------------------------------------===//
537 
538 namespace {
539 
540 class AMDGPUPassConfig : public TargetPassConfig {
541 public:
542   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
543     : TargetPassConfig(TM, PM) {
544     // Exceptions and StackMaps are not supported, so these passes will never do
545     // anything.
546     disablePass(&StackMapLivenessID);
547     disablePass(&FuncletLayoutID);
548   }
549 
550   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
551     return getTM<AMDGPUTargetMachine>();
552   }
553 
554   ScheduleDAGInstrs *
555   createMachineScheduler(MachineSchedContext *C) const override {
556     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
557     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
558     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
559     return DAG;
560   }
561 
562   void addEarlyCSEOrGVNPass();
563   void addStraightLineScalarOptimizationPasses();
564   void addIRPasses() override;
565   void addCodeGenPrepare() override;
566   bool addPreISel() override;
567   bool addInstSelector() override;
568   bool addGCPasses() override;
569 
570   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
571 };
572 
573 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
574   return getStandardCSEConfigForOpt(TM->getOptLevel());
575 }
576 
577 class R600PassConfig final : public AMDGPUPassConfig {
578 public:
579   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
580     : AMDGPUPassConfig(TM, PM) {}
581 
582   ScheduleDAGInstrs *createMachineScheduler(
583     MachineSchedContext *C) const override {
584     return createR600MachineScheduler(C);
585   }
586 
587   bool addPreISel() override;
588   bool addInstSelector() override;
589   void addPreRegAlloc() override;
590   void addPreSched2() override;
591   void addPreEmitPass() override;
592 };
593 
594 class GCNPassConfig final : public AMDGPUPassConfig {
595 public:
596   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
597     : AMDGPUPassConfig(TM, PM) {
598     // It is necessary to know the register usage of the entire call graph.  We
599     // allow calls without EnableAMDGPUFunctionCalls if they are marked
600     // noinline, so this is always required.
601     setRequiresCodeGenSCCOrder(true);
602   }
603 
604   GCNTargetMachine &getGCNTargetMachine() const {
605     return getTM<GCNTargetMachine>();
606   }
607 
608   ScheduleDAGInstrs *
609   createMachineScheduler(MachineSchedContext *C) const override;
610 
611   bool addPreISel() override;
612   void addMachineSSAOptimization() override;
613   bool addILPOpts() override;
614   bool addInstSelector() override;
615   bool addIRTranslator() override;
616   bool addLegalizeMachineIR() override;
617   bool addRegBankSelect() override;
618   bool addGlobalInstructionSelect() override;
619   void addFastRegAlloc() override;
620   void addOptimizedRegAlloc() override;
621   void addPreRegAlloc() override;
622   bool addPreRewrite() override;
623   void addPostRegAlloc() override;
624   void addPreSched2() override;
625   void addPreEmitPass() override;
626 };
627 
628 } // end anonymous namespace
629 
630 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
631   if (getOptLevel() == CodeGenOpt::Aggressive)
632     addPass(createGVNPass());
633   else
634     addPass(createEarlyCSEPass());
635 }
636 
637 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
638   addPass(createLICMPass());
639   addPass(createSeparateConstOffsetFromGEPPass());
640   addPass(createSpeculativeExecutionPass());
641   // ReassociateGEPs exposes more opportunites for SLSR. See
642   // the example in reassociate-geps-and-slsr.ll.
643   addPass(createStraightLineStrengthReducePass());
644   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
645   // EarlyCSE can reuse.
646   addEarlyCSEOrGVNPass();
647   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
648   addPass(createNaryReassociatePass());
649   // NaryReassociate on GEPs creates redundant common expressions, so run
650   // EarlyCSE after it.
651   addPass(createEarlyCSEPass());
652 }
653 
654 void AMDGPUPassConfig::addIRPasses() {
655   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
656 
657   // There is no reason to run these.
658   disablePass(&StackMapLivenessID);
659   disablePass(&FuncletLayoutID);
660   disablePass(&PatchableFunctionID);
661 
662   // This must occur before inlining, as the inliner will not look through
663   // bitcast calls.
664   addPass(createAMDGPUFixFunctionBitcastsPass());
665 
666   // A call to propagate attributes pass in the backend in case opt was not run.
667   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
668 
669   addPass(createAtomicExpandPass());
670 
671 
672   addPass(createAMDGPULowerIntrinsicsPass());
673 
674   // Function calls are not supported, so make sure we inline everything.
675   addPass(createAMDGPUAlwaysInlinePass());
676   addPass(createAlwaysInlinerLegacyPass());
677   // We need to add the barrier noop pass, otherwise adding the function
678   // inlining pass will cause all of the PassConfigs passes to be run
679   // one function at a time, which means if we have a nodule with two
680   // functions, then we will generate code for the first function
681   // without ever running any passes on the second.
682   addPass(createBarrierNoopPass());
683 
684   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
685     // TODO: May want to move later or split into an early and late one.
686 
687     addPass(createAMDGPUCodeGenPreparePass());
688   }
689 
690   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
691   if (TM.getTargetTriple().getArch() == Triple::r600)
692     addPass(createR600OpenCLImageTypeLoweringPass());
693 
694   // Replace OpenCL enqueued block function pointers with global variables.
695   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
696 
697   if (TM.getOptLevel() > CodeGenOpt::None) {
698     addPass(createInferAddressSpacesPass());
699     addPass(createAMDGPUPromoteAlloca());
700 
701     if (EnableSROA)
702       addPass(createSROAPass());
703 
704     if (EnableScalarIRPasses)
705       addStraightLineScalarOptimizationPasses();
706 
707     if (EnableAMDGPUAliasAnalysis) {
708       addPass(createAMDGPUAAWrapperPass());
709       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
710                                              AAResults &AAR) {
711         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
712           AAR.addAAResult(WrapperPass->getResult());
713         }));
714     }
715   }
716 
717   TargetPassConfig::addIRPasses();
718 
719   // EarlyCSE is not always strong enough to clean up what LSR produces. For
720   // example, GVN can combine
721   //
722   //   %0 = add %a, %b
723   //   %1 = add %b, %a
724   //
725   // and
726   //
727   //   %0 = shl nsw %a, 2
728   //   %1 = shl %a, 2
729   //
730   // but EarlyCSE can do neither of them.
731   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
732     addEarlyCSEOrGVNPass();
733 }
734 
735 void AMDGPUPassConfig::addCodeGenPrepare() {
736   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
737     addPass(createAMDGPUAnnotateKernelFeaturesPass());
738 
739   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
740       EnableLowerKernelArguments)
741     addPass(createAMDGPULowerKernelArgumentsPass());
742 
743   TargetPassConfig::addCodeGenPrepare();
744 
745   if (EnableLoadStoreVectorizer)
746     addPass(createLoadStoreVectorizerPass());
747 }
748 
749 bool AMDGPUPassConfig::addPreISel() {
750   addPass(createLowerSwitchPass());
751   addPass(createFlattenCFGPass());
752   return false;
753 }
754 
755 bool AMDGPUPassConfig::addInstSelector() {
756   // Defer the verifier until FinalizeISel.
757   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
758   return false;
759 }
760 
761 bool AMDGPUPassConfig::addGCPasses() {
762   // Do nothing. GC is not supported.
763   return false;
764 }
765 
766 //===----------------------------------------------------------------------===//
767 // R600 Pass Setup
768 //===----------------------------------------------------------------------===//
769 
770 bool R600PassConfig::addPreISel() {
771   AMDGPUPassConfig::addPreISel();
772 
773   if (EnableR600StructurizeCFG)
774     addPass(createStructurizeCFGPass());
775   return false;
776 }
777 
778 bool R600PassConfig::addInstSelector() {
779   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
780   return false;
781 }
782 
783 void R600PassConfig::addPreRegAlloc() {
784   addPass(createR600VectorRegMerger());
785 }
786 
787 void R600PassConfig::addPreSched2() {
788   addPass(createR600EmitClauseMarkers(), false);
789   if (EnableR600IfConvert)
790     addPass(&IfConverterID, false);
791   addPass(createR600ClauseMergePass(), false);
792 }
793 
794 void R600PassConfig::addPreEmitPass() {
795   addPass(createAMDGPUCFGStructurizerPass(), false);
796   addPass(createR600ExpandSpecialInstrsPass(), false);
797   addPass(&FinalizeMachineBundlesID, false);
798   addPass(createR600Packetizer(), false);
799   addPass(createR600ControlFlowFinalizer(), false);
800 }
801 
802 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
803   return new R600PassConfig(*this, PM);
804 }
805 
806 //===----------------------------------------------------------------------===//
807 // GCN Pass Setup
808 //===----------------------------------------------------------------------===//
809 
810 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
811   MachineSchedContext *C) const {
812   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
813   if (ST.enableSIScheduler())
814     return createSIMachineScheduler(C);
815   return createGCNMaxOccupancyMachineScheduler(C);
816 }
817 
818 bool GCNPassConfig::addPreISel() {
819   AMDGPUPassConfig::addPreISel();
820 
821   if (EnableAtomicOptimizations) {
822     addPass(createAMDGPUAtomicOptimizerPass());
823   }
824 
825   // FIXME: We need to run a pass to propagate the attributes when calls are
826   // supported.
827 
828   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
829   // regions formed by them.
830   addPass(&AMDGPUUnifyDivergentExitNodesID);
831   if (!LateCFGStructurize) {
832     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
833   }
834   addPass(createSinkingPass());
835   addPass(createAMDGPUAnnotateUniformValues());
836   if (!LateCFGStructurize) {
837     addPass(createSIAnnotateControlFlowPass());
838   }
839   addPass(createLCSSAPass());
840 
841   return false;
842 }
843 
844 void GCNPassConfig::addMachineSSAOptimization() {
845   TargetPassConfig::addMachineSSAOptimization();
846 
847   // We want to fold operands after PeepholeOptimizer has run (or as part of
848   // it), because it will eliminate extra copies making it easier to fold the
849   // real source operand. We want to eliminate dead instructions after, so that
850   // we see fewer uses of the copies. We then need to clean up the dead
851   // instructions leftover after the operands are folded as well.
852   //
853   // XXX - Can we get away without running DeadMachineInstructionElim again?
854   addPass(&SIFoldOperandsID);
855   if (EnableDPPCombine)
856     addPass(&GCNDPPCombineID);
857   addPass(&DeadMachineInstructionElimID);
858   addPass(&SILoadStoreOptimizerID);
859   if (EnableSDWAPeephole) {
860     addPass(&SIPeepholeSDWAID);
861     addPass(&EarlyMachineLICMID);
862     addPass(&MachineCSEID);
863     addPass(&SIFoldOperandsID);
864     addPass(&DeadMachineInstructionElimID);
865   }
866   addPass(createSIShrinkInstructionsPass());
867 }
868 
869 bool GCNPassConfig::addILPOpts() {
870   if (EnableEarlyIfConversion)
871     addPass(&EarlyIfConverterID);
872 
873   TargetPassConfig::addILPOpts();
874   return false;
875 }
876 
877 bool GCNPassConfig::addInstSelector() {
878   AMDGPUPassConfig::addInstSelector();
879   addPass(&SIFixSGPRCopiesID);
880   addPass(createSILowerI1CopiesPass());
881   addPass(createSIFixupVectorISelPass());
882   addPass(createSIAddIMGInitPass());
883   return false;
884 }
885 
886 bool GCNPassConfig::addIRTranslator() {
887   addPass(new IRTranslator());
888   return false;
889 }
890 
891 bool GCNPassConfig::addLegalizeMachineIR() {
892   addPass(new Legalizer());
893   return false;
894 }
895 
896 bool GCNPassConfig::addRegBankSelect() {
897   addPass(new RegBankSelect());
898   return false;
899 }
900 
901 bool GCNPassConfig::addGlobalInstructionSelect() {
902   addPass(new InstructionSelect());
903   return false;
904 }
905 
906 void GCNPassConfig::addPreRegAlloc() {
907   if (LateCFGStructurize) {
908     addPass(createAMDGPUMachineCFGStructurizerPass());
909   }
910   addPass(createSIWholeQuadModePass());
911 }
912 
913 void GCNPassConfig::addFastRegAlloc() {
914   // FIXME: We have to disable the verifier here because of PHIElimination +
915   // TwoAddressInstructions disabling it.
916 
917   // This must be run immediately after phi elimination and before
918   // TwoAddressInstructions, otherwise the processing of the tied operand of
919   // SI_ELSE will introduce a copy of the tied operand source after the else.
920   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
921 
922   // This must be run just after RegisterCoalescing.
923   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
924 
925   TargetPassConfig::addFastRegAlloc();
926 }
927 
928 void GCNPassConfig::addOptimizedRegAlloc() {
929   if (OptExecMaskPreRA) {
930     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
931     insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
932   } else {
933     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
934   }
935 
936   // This must be run immediately after phi elimination and before
937   // TwoAddressInstructions, otherwise the processing of the tied operand of
938   // SI_ELSE will introduce a copy of the tied operand source after the else.
939   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
940 
941   // This must be run just after RegisterCoalescing.
942   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
943 
944   if (EnableDCEInRA)
945     insertPass(&RenameIndependentSubregsID, &DeadMachineInstructionElimID);
946 
947   TargetPassConfig::addOptimizedRegAlloc();
948 }
949 
950 bool GCNPassConfig::addPreRewrite() {
951   if (EnableRegReassign) {
952     addPass(&GCNNSAReassignID);
953     addPass(&GCNRegBankReassignID);
954   }
955   return true;
956 }
957 
958 void GCNPassConfig::addPostRegAlloc() {
959   addPass(&SIFixVGPRCopiesID);
960   if (getOptLevel() > CodeGenOpt::None)
961     addPass(&SIOptimizeExecMaskingID);
962   TargetPassConfig::addPostRegAlloc();
963 
964   // Equivalent of PEI for SGPRs.
965   addPass(&SILowerSGPRSpillsID);
966 }
967 
968 void GCNPassConfig::addPreSched2() {
969 }
970 
971 void GCNPassConfig::addPreEmitPass() {
972   addPass(createSIMemoryLegalizerPass());
973   addPass(createSIInsertWaitcntsPass());
974   addPass(createSIShrinkInstructionsPass());
975   addPass(createSIModeRegisterPass());
976 
977   // The hazard recognizer that runs as part of the post-ra scheduler does not
978   // guarantee to be able handle all hazards correctly. This is because if there
979   // are multiple scheduling regions in a basic block, the regions are scheduled
980   // bottom up, so when we begin to schedule a region we don't know what
981   // instructions were emitted directly before it.
982   //
983   // Here we add a stand-alone hazard recognizer pass which can handle all
984   // cases.
985   //
986   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
987   // be better for it to emit S_NOP <N> when possible.
988   addPass(&PostRAHazardRecognizerID);
989 
990   addPass(&SIInsertSkipsPassID);
991   addPass(&BranchRelaxationPassID);
992 }
993 
994 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
995   return new GCNPassConfig(*this, PM);
996 }
997 
998 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
999   return new yaml::SIMachineFunctionInfo();
1000 }
1001 
1002 yaml::MachineFunctionInfo *
1003 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1004   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1005   return new yaml::SIMachineFunctionInfo(*MFI,
1006                                          *MF.getSubtarget().getRegisterInfo());
1007 }
1008 
1009 bool GCNTargetMachine::parseMachineFunctionInfo(
1010     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1011     SMDiagnostic &Error, SMRange &SourceRange) const {
1012   const yaml::SIMachineFunctionInfo &YamlMFI =
1013       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1014   MachineFunction &MF = PFS.MF;
1015   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1016 
1017   MFI->initializeBaseYamlFields(YamlMFI);
1018 
1019   auto parseRegister = [&](const yaml::StringValue &RegName, unsigned &RegVal) {
1020     if (parseNamedRegisterReference(PFS, RegVal, RegName.Value, Error)) {
1021       SourceRange = RegName.SourceRange;
1022       return true;
1023     }
1024 
1025     return false;
1026   };
1027 
1028   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1029     // Create a diagnostic for a the register string literal.
1030     const MemoryBuffer &Buffer =
1031         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1032     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1033                          RegName.Value.size(), SourceMgr::DK_Error,
1034                          "incorrect register class for field", RegName.Value,
1035                          None, None);
1036     SourceRange = RegName.SourceRange;
1037     return true;
1038   };
1039 
1040   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1041       parseRegister(YamlMFI.ScratchWaveOffsetReg, MFI->ScratchWaveOffsetReg) ||
1042       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1043       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1044     return true;
1045 
1046   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1047       !AMDGPU::SReg_128RegClass.contains(MFI->ScratchRSrcReg)) {
1048     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1049   }
1050 
1051   if (MFI->ScratchWaveOffsetReg != AMDGPU::SCRATCH_WAVE_OFFSET_REG &&
1052       !AMDGPU::SGPR_32RegClass.contains(MFI->ScratchWaveOffsetReg)) {
1053     return diagnoseRegisterClass(YamlMFI.ScratchWaveOffsetReg);
1054   }
1055 
1056   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1057       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1058     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1059   }
1060 
1061   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1062       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1063     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1064   }
1065 
1066   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1067                                    const TargetRegisterClass &RC,
1068                                    ArgDescriptor &Arg) {
1069     // Skip parsing if it's not present.
1070     if (!A)
1071       return false;
1072 
1073     if (A->IsRegister) {
1074       unsigned Reg;
1075       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value,
1076                                       Error)) {
1077         SourceRange = A->RegisterName.SourceRange;
1078         return true;
1079       }
1080       if (!RC.contains(Reg))
1081         return diagnoseRegisterClass(A->RegisterName);
1082       Arg = ArgDescriptor::createRegister(Reg);
1083     } else
1084       Arg = ArgDescriptor::createStack(A->StackOffset);
1085     // Check and apply the optional mask.
1086     if (A->Mask)
1087       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1088 
1089     return false;
1090   };
1091 
1092   if (YamlMFI.ArgInfo &&
1093       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1094                              AMDGPU::SReg_128RegClass,
1095                              MFI->ArgInfo.PrivateSegmentBuffer) ||
1096        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1097                              AMDGPU::SReg_64RegClass,
1098                              MFI->ArgInfo.DispatchPtr) ||
1099        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1100                              MFI->ArgInfo.QueuePtr) ||
1101        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1102                              AMDGPU::SReg_64RegClass,
1103                              MFI->ArgInfo.KernargSegmentPtr) ||
1104        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1105                              AMDGPU::SReg_64RegClass,
1106                              MFI->ArgInfo.DispatchID) ||
1107        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1108                              AMDGPU::SReg_64RegClass,
1109                              MFI->ArgInfo.FlatScratchInit) ||
1110        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1111                              AMDGPU::SGPR_32RegClass,
1112                              MFI->ArgInfo.PrivateSegmentSize) ||
1113        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1114                              AMDGPU::SGPR_32RegClass,
1115                              MFI->ArgInfo.WorkGroupIDX) ||
1116        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1117                              AMDGPU::SGPR_32RegClass,
1118                              MFI->ArgInfo.WorkGroupIDY) ||
1119        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1120                              AMDGPU::SGPR_32RegClass,
1121                              MFI->ArgInfo.WorkGroupIDZ) ||
1122        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1123                              AMDGPU::SGPR_32RegClass,
1124                              MFI->ArgInfo.WorkGroupInfo) ||
1125        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1126                              AMDGPU::SGPR_32RegClass,
1127                              MFI->ArgInfo.PrivateSegmentWaveByteOffset) ||
1128        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1129                              AMDGPU::SReg_64RegClass,
1130                              MFI->ArgInfo.ImplicitArgPtr) ||
1131        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1132                              AMDGPU::SReg_64RegClass,
1133                              MFI->ArgInfo.ImplicitBufferPtr) ||
1134        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1135                              AMDGPU::VGPR_32RegClass,
1136                              MFI->ArgInfo.WorkItemIDX) ||
1137        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1138                              AMDGPU::VGPR_32RegClass,
1139                              MFI->ArgInfo.WorkItemIDY) ||
1140        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1141                              AMDGPU::VGPR_32RegClass,
1142                              MFI->ArgInfo.WorkItemIDZ)))
1143     return true;
1144 
1145   return false;
1146 }
1147