1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110   cl::desc("Enable AMDGPU Alias Analysis"),
111   cl::init(true));
112 
113 // Option to enable new waitcnt insertion pass.
114 static cl::opt<bool> EnableSIInsertWaitcntsPass(
115   "enable-si-insert-waitcnts",
116   cl::desc("Use new waitcnt insertion pass"),
117   cl::init(true));
118 
119 // Option to run late CFG structurizer
120 static cl::opt<bool> LateCFGStructurize(
121   "amdgpu-late-structurize",
122   cl::desc("Enable late CFG structurization"),
123   cl::init(false),
124   cl::Hidden);
125 
126 static cl::opt<bool> EnableAMDGPUFunctionCalls(
127   "amdgpu-function-calls",
128   cl::Hidden,
129   cl::desc("Enable AMDGPU function call support"),
130   cl::init(false));
131 
132 // Enable lib calls simplifications
133 static cl::opt<bool> EnableLibCallSimplify(
134   "amdgpu-simplify-libcall",
135   cl::desc("Enable mdgpu library simplifications"),
136   cl::init(true),
137   cl::Hidden);
138 
139 extern "C" void LLVMInitializeAMDGPUTarget() {
140   // Register the target
141   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
142   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
143 
144   PassRegistry *PR = PassRegistry::getPassRegistry();
145   initializeR600ClauseMergePassPass(*PR);
146   initializeR600ControlFlowFinalizerPass(*PR);
147   initializeR600PacketizerPass(*PR);
148   initializeR600ExpandSpecialInstrsPassPass(*PR);
149   initializeR600VectorRegMergerPass(*PR);
150   initializeAMDGPUDAGToDAGISelPass(*PR);
151   initializeSILowerI1CopiesPass(*PR);
152   initializeSIFixSGPRCopiesPass(*PR);
153   initializeSIFixVGPRCopiesPass(*PR);
154   initializeSIFoldOperandsPass(*PR);
155   initializeSIPeepholeSDWAPass(*PR);
156   initializeSIShrinkInstructionsPass(*PR);
157   initializeSIOptimizeExecMaskingPreRAPass(*PR);
158   initializeSILoadStoreOptimizerPass(*PR);
159   initializeAMDGPUAlwaysInlinePass(*PR);
160   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
161   initializeAMDGPUAnnotateUniformValuesPass(*PR);
162   initializeAMDGPUArgumentUsageInfoPass(*PR);
163   initializeAMDGPULowerIntrinsicsPass(*PR);
164   initializeAMDGPUPromoteAllocaPass(*PR);
165   initializeAMDGPUCodeGenPreparePass(*PR);
166   initializeAMDGPURewriteOutArgumentsPass(*PR);
167   initializeAMDGPUUnifyMetadataPass(*PR);
168   initializeSIAnnotateControlFlowPass(*PR);
169   initializeSIInsertWaitsPass(*PR);
170   initializeSIInsertWaitcntsPass(*PR);
171   initializeSIWholeQuadModePass(*PR);
172   initializeSILowerControlFlowPass(*PR);
173   initializeSIInsertSkipsPass(*PR);
174   initializeSIMemoryLegalizerPass(*PR);
175   initializeSIDebuggerInsertNopsPass(*PR);
176   initializeSIOptimizeExecMaskingPass(*PR);
177   initializeSIFixWWMLivenessPass(*PR);
178   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
179   initializeAMDGPUAAWrapperPassPass(*PR);
180   initializeAMDGPUUseNativeCallsPass(*PR);
181   initializeAMDGPUSimplifyLibCallsPass(*PR);
182   initializeAMDGPUInlinerPass(*PR);
183 }
184 
185 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
186   return llvm::make_unique<AMDGPUTargetObjectFile>();
187 }
188 
189 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
190   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
191 }
192 
193 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
194   return new SIScheduleDAGMI(C);
195 }
196 
197 static ScheduleDAGInstrs *
198 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
199   ScheduleDAGMILive *DAG =
200     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
201   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
202   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
203   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
204   return DAG;
205 }
206 
207 static ScheduleDAGInstrs *
208 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
209   auto DAG = new GCNIterativeScheduler(C,
210     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
211   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
212   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
213   return DAG;
214 }
215 
216 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
217   return new GCNIterativeScheduler(C,
218     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
219 }
220 
221 static MachineSchedRegistry
222 R600SchedRegistry("r600", "Run R600's custom scheduler",
223                    createR600MachineScheduler);
224 
225 static MachineSchedRegistry
226 SISchedRegistry("si", "Run SI's custom scheduler",
227                 createSIMachineScheduler);
228 
229 static MachineSchedRegistry
230 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
231                              "Run GCN scheduler to maximize occupancy",
232                              createGCNMaxOccupancyMachineScheduler);
233 
234 static MachineSchedRegistry
235 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
236   "Run GCN scheduler to maximize occupancy (experimental)",
237   createIterativeGCNMaxOccupancyMachineScheduler);
238 
239 static MachineSchedRegistry
240 GCNMinRegSchedRegistry("gcn-minreg",
241   "Run GCN iterative scheduler for minimal register usage (experimental)",
242   createMinRegScheduler);
243 
244 static StringRef computeDataLayout(const Triple &TT) {
245   if (TT.getArch() == Triple::r600) {
246     // 32-bit pointers.
247     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
248             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
249   }
250 
251   // 32-bit private, local, and region pointers. 64-bit global, constant and
252   // flat.
253   if (TT.getEnvironmentName() == "amdgiz" ||
254       TT.getEnvironmentName() == "amdgizcl")
255     return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
256          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
257          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
258   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
259       "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
260       "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
261 }
262 
263 LLVM_READNONE
264 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
265   if (!GPU.empty())
266     return GPU;
267 
268   if (TT.getArch() == Triple::amdgcn)
269     return "generic";
270 
271   return "r600";
272 }
273 
274 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
275   // The AMDGPU toolchain only supports generating shared objects, so we
276   // must always use PIC.
277   return Reloc::PIC_;
278 }
279 
280 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
281   if (CM)
282     return *CM;
283   return CodeModel::Small;
284 }
285 
286 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
287                                          StringRef CPU, StringRef FS,
288                                          TargetOptions Options,
289                                          Optional<Reloc::Model> RM,
290                                          Optional<CodeModel::Model> CM,
291                                          CodeGenOpt::Level OptLevel)
292     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
293                         FS, Options, getEffectiveRelocModel(RM),
294                         getEffectiveCodeModel(CM), OptLevel),
295       TLOF(createTLOF(getTargetTriple())) {
296   AS = AMDGPU::getAMDGPUAS(TT);
297   initAsmInfo();
298 }
299 
300 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
301 
302 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
303   Attribute GPUAttr = F.getFnAttribute("target-cpu");
304   return GPUAttr.hasAttribute(Attribute::None) ?
305     getTargetCPU() : GPUAttr.getValueAsString();
306 }
307 
308 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
309   Attribute FSAttr = F.getFnAttribute("target-features");
310 
311   return FSAttr.hasAttribute(Attribute::None) ?
312     getTargetFeatureString() :
313     FSAttr.getValueAsString();
314 }
315 
316 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
317   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
318       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
319         AAR.addAAResult(WrapperPass->getResult());
320       });
321 }
322 
323 /// Predicate for Internalize pass.
324 bool mustPreserveGV(const GlobalValue &GV) {
325   if (const Function *F = dyn_cast<Function>(&GV))
326     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
327 
328   return !GV.use_empty();
329 }
330 
331 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
332   Builder.DivergentTarget = true;
333 
334   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
335   bool Internalize = InternalizeSymbols;
336   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
337   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
338   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
339 
340   if (EnableAMDGPUFunctionCalls) {
341     delete Builder.Inliner;
342     Builder.Inliner = createAMDGPUFunctionInliningPass();
343   }
344 
345   if (Internalize) {
346     // If we're generating code, we always have the whole program available. The
347     // relocations expected for externally visible functions aren't supported,
348     // so make sure every non-entry function is hidden.
349     Builder.addExtension(
350       PassManagerBuilder::EP_EnabledOnOptLevel0,
351       [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
352         PM.add(createInternalizePass(mustPreserveGV));
353       });
354   }
355 
356   Builder.addExtension(
357     PassManagerBuilder::EP_ModuleOptimizerEarly,
358     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
359                                          legacy::PassManagerBase &PM) {
360       if (AMDGPUAA) {
361         PM.add(createAMDGPUAAWrapperPass());
362         PM.add(createAMDGPUExternalAAWrapperPass());
363       }
364       PM.add(createAMDGPUUnifyMetadataPass());
365       if (Internalize) {
366         PM.add(createInternalizePass(mustPreserveGV));
367         PM.add(createGlobalDCEPass());
368       }
369       if (EarlyInline)
370         PM.add(createAMDGPUAlwaysInlinePass(false));
371   });
372 
373   const auto &Opt = Options;
374   Builder.addExtension(
375     PassManagerBuilder::EP_EarlyAsPossible,
376     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
377                                       legacy::PassManagerBase &PM) {
378       if (AMDGPUAA) {
379         PM.add(createAMDGPUAAWrapperPass());
380         PM.add(createAMDGPUExternalAAWrapperPass());
381       }
382       PM.add(llvm::createAMDGPUUseNativeCallsPass());
383       if (LibCallSimplify)
384         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
385   });
386 
387   Builder.addExtension(
388     PassManagerBuilder::EP_CGSCCOptimizerLate,
389     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
390       // Add infer address spaces pass to the opt pipeline after inlining
391       // but before SROA to increase SROA opportunities.
392       PM.add(createInferAddressSpacesPass());
393   });
394 }
395 
396 //===----------------------------------------------------------------------===//
397 // R600 Target Machine (R600 -> Cayman)
398 //===----------------------------------------------------------------------===//
399 
400 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
401                                      StringRef CPU, StringRef FS,
402                                      TargetOptions Options,
403                                      Optional<Reloc::Model> RM,
404                                      Optional<CodeModel::Model> CM,
405                                      CodeGenOpt::Level OL, bool JIT)
406     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
407   setRequiresStructuredCFG(true);
408 }
409 
410 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
411   const Function &F) const {
412   StringRef GPU = getGPUName(F);
413   StringRef FS = getFeatureString(F);
414 
415   SmallString<128> SubtargetKey(GPU);
416   SubtargetKey.append(FS);
417 
418   auto &I = SubtargetMap[SubtargetKey];
419   if (!I) {
420     // This needs to be done before we create a new subtarget since any
421     // creation will depend on the TM and the code generation flags on the
422     // function that reside in TargetOptions.
423     resetTargetOptions(F);
424     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
425   }
426 
427   return I.get();
428 }
429 
430 //===----------------------------------------------------------------------===//
431 // GCN Target Machine (SI+)
432 //===----------------------------------------------------------------------===//
433 
434 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
435                                    StringRef CPU, StringRef FS,
436                                    TargetOptions Options,
437                                    Optional<Reloc::Model> RM,
438                                    Optional<CodeModel::Model> CM,
439                                    CodeGenOpt::Level OL, bool JIT)
440     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
441 
442 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
443   StringRef GPU = getGPUName(F);
444   StringRef FS = getFeatureString(F);
445 
446   SmallString<128> SubtargetKey(GPU);
447   SubtargetKey.append(FS);
448 
449   auto &I = SubtargetMap[SubtargetKey];
450   if (!I) {
451     // This needs to be done before we create a new subtarget since any
452     // creation will depend on the TM and the code generation flags on the
453     // function that reside in TargetOptions.
454     resetTargetOptions(F);
455     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
456   }
457 
458   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
459 
460   return I.get();
461 }
462 
463 //===----------------------------------------------------------------------===//
464 // AMDGPU Pass Setup
465 //===----------------------------------------------------------------------===//
466 
467 namespace {
468 
469 class AMDGPUPassConfig : public TargetPassConfig {
470 public:
471   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
472     : TargetPassConfig(TM, PM) {
473     // Exceptions and StackMaps are not supported, so these passes will never do
474     // anything.
475     disablePass(&StackMapLivenessID);
476     disablePass(&FuncletLayoutID);
477   }
478 
479   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
480     return getTM<AMDGPUTargetMachine>();
481   }
482 
483   ScheduleDAGInstrs *
484   createMachineScheduler(MachineSchedContext *C) const override {
485     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
486     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
487     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
488     return DAG;
489   }
490 
491   void addEarlyCSEOrGVNPass();
492   void addStraightLineScalarOptimizationPasses();
493   void addIRPasses() override;
494   void addCodeGenPrepare() override;
495   bool addPreISel() override;
496   bool addInstSelector() override;
497   bool addGCPasses() override;
498 };
499 
500 class R600PassConfig final : public AMDGPUPassConfig {
501 public:
502   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
503     : AMDGPUPassConfig(TM, PM) {}
504 
505   ScheduleDAGInstrs *createMachineScheduler(
506     MachineSchedContext *C) const override {
507     return createR600MachineScheduler(C);
508   }
509 
510   bool addPreISel() override;
511   bool addInstSelector() override;
512   void addPreRegAlloc() override;
513   void addPreSched2() override;
514   void addPreEmitPass() override;
515 };
516 
517 class GCNPassConfig final : public AMDGPUPassConfig {
518 public:
519   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
520     : AMDGPUPassConfig(TM, PM) {
521     // It is necessary to know the register usage of the entire call graph.  We
522     // allow calls without EnableAMDGPUFunctionCalls if they are marked
523     // noinline, so this is always required.
524     setRequiresCodeGenSCCOrder(true);
525   }
526 
527   GCNTargetMachine &getGCNTargetMachine() const {
528     return getTM<GCNTargetMachine>();
529   }
530 
531   ScheduleDAGInstrs *
532   createMachineScheduler(MachineSchedContext *C) const override;
533 
534   bool addPreISel() override;
535   void addMachineSSAOptimization() override;
536   bool addILPOpts() override;
537   bool addInstSelector() override;
538   bool addIRTranslator() override;
539   bool addLegalizeMachineIR() override;
540   bool addRegBankSelect() override;
541   bool addGlobalInstructionSelect() override;
542   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
543   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
544   void addPreRegAlloc() override;
545   void addPostRegAlloc() override;
546   void addPreSched2() override;
547   void addPreEmitPass() override;
548 };
549 
550 } // end anonymous namespace
551 
552 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
553   return TargetIRAnalysis([this](const Function &F) {
554     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
555   });
556 }
557 
558 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
559   if (getOptLevel() == CodeGenOpt::Aggressive)
560     addPass(createGVNPass());
561   else
562     addPass(createEarlyCSEPass());
563 }
564 
565 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
566   addPass(createSeparateConstOffsetFromGEPPass());
567   addPass(createSpeculativeExecutionPass());
568   // ReassociateGEPs exposes more opportunites for SLSR. See
569   // the example in reassociate-geps-and-slsr.ll.
570   addPass(createStraightLineStrengthReducePass());
571   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
572   // EarlyCSE can reuse.
573   addEarlyCSEOrGVNPass();
574   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
575   addPass(createNaryReassociatePass());
576   // NaryReassociate on GEPs creates redundant common expressions, so run
577   // EarlyCSE after it.
578   addPass(createEarlyCSEPass());
579 }
580 
581 void AMDGPUPassConfig::addIRPasses() {
582   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
583 
584   // There is no reason to run these.
585   disablePass(&StackMapLivenessID);
586   disablePass(&FuncletLayoutID);
587   disablePass(&PatchableFunctionID);
588 
589   addPass(createAMDGPULowerIntrinsicsPass());
590 
591   if (TM.getTargetTriple().getArch() == Triple::r600 ||
592       !EnableAMDGPUFunctionCalls) {
593     // Function calls are not supported, so make sure we inline everything.
594     addPass(createAMDGPUAlwaysInlinePass());
595     addPass(createAlwaysInlinerLegacyPass());
596     // We need to add the barrier noop pass, otherwise adding the function
597     // inlining pass will cause all of the PassConfigs passes to be run
598     // one function at a time, which means if we have a nodule with two
599     // functions, then we will generate code for the first function
600     // without ever running any passes on the second.
601     addPass(createBarrierNoopPass());
602   }
603 
604   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
605     // TODO: May want to move later or split into an early and late one.
606 
607     addPass(createAMDGPUCodeGenPreparePass());
608   }
609 
610   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
611   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
612 
613   if (TM.getOptLevel() > CodeGenOpt::None) {
614     addPass(createInferAddressSpacesPass());
615     addPass(createAMDGPUPromoteAlloca());
616 
617     if (EnableSROA)
618       addPass(createSROAPass());
619 
620     addStraightLineScalarOptimizationPasses();
621 
622     if (EnableAMDGPUAliasAnalysis) {
623       addPass(createAMDGPUAAWrapperPass());
624       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
625                                              AAResults &AAR) {
626         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
627           AAR.addAAResult(WrapperPass->getResult());
628         }));
629     }
630   }
631 
632   TargetPassConfig::addIRPasses();
633 
634   // EarlyCSE is not always strong enough to clean up what LSR produces. For
635   // example, GVN can combine
636   //
637   //   %0 = add %a, %b
638   //   %1 = add %b, %a
639   //
640   // and
641   //
642   //   %0 = shl nsw %a, 2
643   //   %1 = shl %a, 2
644   //
645   // but EarlyCSE can do neither of them.
646   if (getOptLevel() != CodeGenOpt::None)
647     addEarlyCSEOrGVNPass();
648 }
649 
650 void AMDGPUPassConfig::addCodeGenPrepare() {
651   TargetPassConfig::addCodeGenPrepare();
652 
653   if (EnableLoadStoreVectorizer)
654     addPass(createLoadStoreVectorizerPass());
655 }
656 
657 bool AMDGPUPassConfig::addPreISel() {
658   addPass(createFlattenCFGPass());
659   return false;
660 }
661 
662 bool AMDGPUPassConfig::addInstSelector() {
663   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
664   return false;
665 }
666 
667 bool AMDGPUPassConfig::addGCPasses() {
668   // Do nothing. GC is not supported.
669   return false;
670 }
671 
672 //===----------------------------------------------------------------------===//
673 // R600 Pass Setup
674 //===----------------------------------------------------------------------===//
675 
676 bool R600PassConfig::addPreISel() {
677   AMDGPUPassConfig::addPreISel();
678 
679   if (EnableR600StructurizeCFG)
680     addPass(createStructurizeCFGPass());
681   return false;
682 }
683 
684 bool R600PassConfig::addInstSelector() {
685   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
686   return false;
687 }
688 
689 void R600PassConfig::addPreRegAlloc() {
690   addPass(createR600VectorRegMerger());
691 }
692 
693 void R600PassConfig::addPreSched2() {
694   addPass(createR600EmitClauseMarkers(), false);
695   if (EnableR600IfConvert)
696     addPass(&IfConverterID, false);
697   addPass(createR600ClauseMergePass(), false);
698 }
699 
700 void R600PassConfig::addPreEmitPass() {
701   addPass(createAMDGPUCFGStructurizerPass(), false);
702   addPass(createR600ExpandSpecialInstrsPass(), false);
703   addPass(&FinalizeMachineBundlesID, false);
704   addPass(createR600Packetizer(), false);
705   addPass(createR600ControlFlowFinalizer(), false);
706 }
707 
708 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
709   return new R600PassConfig(*this, PM);
710 }
711 
712 //===----------------------------------------------------------------------===//
713 // GCN Pass Setup
714 //===----------------------------------------------------------------------===//
715 
716 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
717   MachineSchedContext *C) const {
718   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
719   if (ST.enableSIScheduler())
720     return createSIMachineScheduler(C);
721   return createGCNMaxOccupancyMachineScheduler(C);
722 }
723 
724 bool GCNPassConfig::addPreISel() {
725   AMDGPUPassConfig::addPreISel();
726 
727   // FIXME: We need to run a pass to propagate the attributes when calls are
728   // supported.
729   addPass(createAMDGPUAnnotateKernelFeaturesPass());
730 
731   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
732   // regions formed by them.
733   addPass(&AMDGPUUnifyDivergentExitNodesID);
734   if (!LateCFGStructurize) {
735     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
736   }
737   addPass(createSinkingPass());
738   addPass(createAMDGPUAnnotateUniformValues());
739   if (!LateCFGStructurize) {
740     addPass(createSIAnnotateControlFlowPass());
741   }
742 
743   return false;
744 }
745 
746 void GCNPassConfig::addMachineSSAOptimization() {
747   TargetPassConfig::addMachineSSAOptimization();
748 
749   // We want to fold operands after PeepholeOptimizer has run (or as part of
750   // it), because it will eliminate extra copies making it easier to fold the
751   // real source operand. We want to eliminate dead instructions after, so that
752   // we see fewer uses of the copies. We then need to clean up the dead
753   // instructions leftover after the operands are folded as well.
754   //
755   // XXX - Can we get away without running DeadMachineInstructionElim again?
756   addPass(&SIFoldOperandsID);
757   addPass(&DeadMachineInstructionElimID);
758   addPass(&SILoadStoreOptimizerID);
759   if (EnableSDWAPeephole) {
760     addPass(&SIPeepholeSDWAID);
761     addPass(&MachineLICMID);
762     addPass(&MachineCSEID);
763     addPass(&SIFoldOperandsID);
764     addPass(&DeadMachineInstructionElimID);
765   }
766   addPass(createSIShrinkInstructionsPass());
767 }
768 
769 bool GCNPassConfig::addILPOpts() {
770   if (EnableEarlyIfConversion)
771     addPass(&EarlyIfConverterID);
772 
773   TargetPassConfig::addILPOpts();
774   return false;
775 }
776 
777 bool GCNPassConfig::addInstSelector() {
778   AMDGPUPassConfig::addInstSelector();
779   addPass(createSILowerI1CopiesPass());
780   addPass(&SIFixSGPRCopiesID);
781   return false;
782 }
783 
784 bool GCNPassConfig::addIRTranslator() {
785   addPass(new IRTranslator());
786   return false;
787 }
788 
789 bool GCNPassConfig::addLegalizeMachineIR() {
790   addPass(new Legalizer());
791   return false;
792 }
793 
794 bool GCNPassConfig::addRegBankSelect() {
795   addPass(new RegBankSelect());
796   return false;
797 }
798 
799 bool GCNPassConfig::addGlobalInstructionSelect() {
800   addPass(new InstructionSelect());
801   return false;
802 }
803 
804 void GCNPassConfig::addPreRegAlloc() {
805   if (LateCFGStructurize) {
806     addPass(createAMDGPUMachineCFGStructurizerPass());
807   }
808   addPass(createSIWholeQuadModePass());
809 }
810 
811 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
812   // FIXME: We have to disable the verifier here because of PHIElimination +
813   // TwoAddressInstructions disabling it.
814 
815   // This must be run immediately after phi elimination and before
816   // TwoAddressInstructions, otherwise the processing of the tied operand of
817   // SI_ELSE will introduce a copy of the tied operand source after the else.
818   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
819 
820   // This must be run after SILowerControlFlow, since it needs to use the
821   // machine-level CFG, but before register allocation.
822   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
823 
824   TargetPassConfig::addFastRegAlloc(RegAllocPass);
825 }
826 
827 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
828   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
829 
830   // This must be run immediately after phi elimination and before
831   // TwoAddressInstructions, otherwise the processing of the tied operand of
832   // SI_ELSE will introduce a copy of the tied operand source after the else.
833   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
834 
835   // This must be run after SILowerControlFlow, since it needs to use the
836   // machine-level CFG, but before register allocation.
837   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
838 
839   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
840 }
841 
842 void GCNPassConfig::addPostRegAlloc() {
843   addPass(&SIFixVGPRCopiesID);
844   addPass(&SIOptimizeExecMaskingID);
845   TargetPassConfig::addPostRegAlloc();
846 }
847 
848 void GCNPassConfig::addPreSched2() {
849 }
850 
851 void GCNPassConfig::addPreEmitPass() {
852   // The hazard recognizer that runs as part of the post-ra scheduler does not
853   // guarantee to be able handle all hazards correctly. This is because if there
854   // are multiple scheduling regions in a basic block, the regions are scheduled
855   // bottom up, so when we begin to schedule a region we don't know what
856   // instructions were emitted directly before it.
857   //
858   // Here we add a stand-alone hazard recognizer pass which can handle all
859   // cases.
860   addPass(&PostRAHazardRecognizerID);
861 
862   if (EnableSIInsertWaitcntsPass)
863     addPass(createSIInsertWaitcntsPass());
864   else
865     addPass(createSIInsertWaitsPass());
866   addPass(createSIShrinkInstructionsPass());
867   addPass(&SIInsertSkipsPassID);
868   addPass(createSIMemoryLegalizerPass());
869   addPass(createSIDebuggerInsertNopsPass());
870   addPass(&BranchRelaxationPassID);
871 }
872 
873 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
874   return new GCNPassConfig(*this, PM);
875 }
876 
877