1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600MachineScheduler.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIMachineScheduler.h"
27 #include "TargetInfo/AMDGPUTargetInfo.h"
28 #include "llvm/Analysis/CGSCCPassManager.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/Localizer.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MIRParser/MIParser.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/LegacyPassManager.h"
37 #include "llvm/IR/PassManager.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/Passes/PassBuilder.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Transforms/IPO.h"
42 #include "llvm/Transforms/IPO/AlwaysInliner.h"
43 #include "llvm/Transforms/IPO/GlobalDCE.h"
44 #include "llvm/Transforms/IPO/Internalize.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
49 #include "llvm/Transforms/Utils.h"
50 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
51 #include "llvm/Transforms/Vectorize.h"
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73             cl::desc("Run pre-RA exec mask optimizations"),
74             cl::init(true));
75 
76 static cl::opt<bool> EnableR600IfConvert(
77   "r600-if-convert",
78   cl::desc("Use if conversion pass"),
79   cl::ReallyHidden,
80   cl::init(true));
81 
82 // Option to disable vectorizer for tests.
83 static cl::opt<bool> EnableLoadStoreVectorizer(
84   "amdgpu-load-store-vectorizer",
85   cl::desc("Enable load store vectorizer"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to control global loads scalarization
90 static cl::opt<bool> ScalarizeGlobal(
91   "amdgpu-scalarize-global-loads",
92   cl::desc("Enable global load scalarization"),
93   cl::init(true),
94   cl::Hidden);
95 
96 // Option to run internalize pass.
97 static cl::opt<bool> InternalizeSymbols(
98   "amdgpu-internalize-symbols",
99   cl::desc("Enable elimination of non-kernel functions and unused globals"),
100   cl::init(false),
101   cl::Hidden);
102 
103 // Option to inline all early.
104 static cl::opt<bool> EarlyInlineAll(
105   "amdgpu-early-inline-all",
106   cl::desc("Inline all functions early"),
107   cl::init(false),
108   cl::Hidden);
109 
110 static cl::opt<bool> EnableSDWAPeephole(
111   "amdgpu-sdwa-peephole",
112   cl::desc("Enable SDWA peepholer"),
113   cl::init(true));
114 
115 static cl::opt<bool> EnableDPPCombine(
116   "amdgpu-dpp-combine",
117   cl::desc("Enable DPP combiner"),
118   cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122   cl::desc("Enable AMDGPU Alias Analysis"),
123   cl::init(true));
124 
125 // Option to run late CFG structurizer
126 static cl::opt<bool, true> LateCFGStructurize(
127   "amdgpu-late-structurize",
128   cl::desc("Enable late CFG structurization"),
129   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
130   cl::Hidden);
131 
132 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
133   "amdgpu-function-calls",
134   cl::desc("Enable AMDGPU function call support"),
135   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
136   cl::init(true),
137   cl::Hidden);
138 
139 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
140   "amdgpu-fixed-function-abi",
141   cl::desc("Enable all implicit function arguments"),
142   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
143   cl::init(false),
144   cl::Hidden);
145 
146 // Enable lib calls simplifications
147 static cl::opt<bool> EnableLibCallSimplify(
148   "amdgpu-simplify-libcall",
149   cl::desc("Enable amdgpu library simplifications"),
150   cl::init(true),
151   cl::Hidden);
152 
153 static cl::opt<bool> EnableLowerKernelArguments(
154   "amdgpu-ir-lower-kernel-arguments",
155   cl::desc("Lower kernel argument loads in IR pass"),
156   cl::init(true),
157   cl::Hidden);
158 
159 static cl::opt<bool> EnableRegReassign(
160   "amdgpu-reassign-regs",
161   cl::desc("Enable register reassign optimizations on gfx10+"),
162   cl::init(true),
163   cl::Hidden);
164 
165 // Enable atomic optimization
166 static cl::opt<bool> EnableAtomicOptimizations(
167   "amdgpu-atomic-optimizations",
168   cl::desc("Enable atomic optimizations"),
169   cl::init(false),
170   cl::Hidden);
171 
172 // Enable Mode register optimization
173 static cl::opt<bool> EnableSIModeRegisterPass(
174   "amdgpu-mode-register",
175   cl::desc("Enable mode register pass"),
176   cl::init(true),
177   cl::Hidden);
178 
179 // Option is used in lit tests to prevent deadcoding of patterns inspected.
180 static cl::opt<bool>
181 EnableDCEInRA("amdgpu-dce-in-ra",
182     cl::init(true), cl::Hidden,
183     cl::desc("Enable machine DCE inside regalloc"));
184 
185 static cl::opt<bool> EnableScalarIRPasses(
186   "amdgpu-scalar-ir-passes",
187   cl::desc("Enable scalar IR passes"),
188   cl::init(true),
189   cl::Hidden);
190 
191 static cl::opt<bool> EnableStructurizerWorkarounds(
192     "amdgpu-enable-structurizer-workarounds",
193     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
194     cl::Hidden);
195 
196 static cl::opt<bool>
197     DisableLowerModuleLDS("amdgpu-disable-lower-module-lds", cl::Hidden,
198                           cl::desc("Disable lower module lds pass"),
199                           cl::init(false));
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFoldOperandsPass(*PR);
220   initializeSIPeepholeSDWAPass(*PR);
221   initializeSIShrinkInstructionsPass(*PR);
222   initializeSIOptimizeExecMaskingPreRAPass(*PR);
223   initializeSILoadStoreOptimizerPass(*PR);
224   initializeAMDGPUFixFunctionBitcastsPass(*PR);
225   initializeAMDGPUAlwaysInlinePass(*PR);
226   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
227   initializeAMDGPUAnnotateUniformValuesPass(*PR);
228   initializeAMDGPUArgumentUsageInfoPass(*PR);
229   initializeAMDGPUAtomicOptimizerPass(*PR);
230   initializeAMDGPULowerKernelArgumentsPass(*PR);
231   initializeAMDGPULowerKernelAttributesPass(*PR);
232   initializeAMDGPULowerIntrinsicsPass(*PR);
233   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
234   initializeAMDGPUPostLegalizerCombinerPass(*PR);
235   initializeAMDGPUPreLegalizerCombinerPass(*PR);
236   initializeAMDGPURegBankCombinerPass(*PR);
237   initializeAMDGPUPromoteAllocaPass(*PR);
238   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
239   initializeAMDGPUCodeGenPreparePass(*PR);
240   initializeAMDGPULateCodeGenPreparePass(*PR);
241   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
242   initializeAMDGPUPropagateAttributesLatePass(*PR);
243   initializeAMDGPULowerModuleLDSPass(*PR);
244   initializeAMDGPURewriteOutArgumentsPass(*PR);
245   initializeAMDGPUUnifyMetadataPass(*PR);
246   initializeSIAnnotateControlFlowPass(*PR);
247   initializeSIInsertHardClausesPass(*PR);
248   initializeSIInsertWaitcntsPass(*PR);
249   initializeSIModeRegisterPass(*PR);
250   initializeSIWholeQuadModePass(*PR);
251   initializeSILowerControlFlowPass(*PR);
252   initializeSIRemoveShortExecBranchesPass(*PR);
253   initializeSIPreEmitPeepholePass(*PR);
254   initializeSIInsertSkipsPass(*PR);
255   initializeSIMemoryLegalizerPass(*PR);
256   initializeSIOptimizeExecMaskingPass(*PR);
257   initializeSIPreAllocateWWMRegsPass(*PR);
258   initializeSIFormMemoryClausesPass(*PR);
259   initializeSIPostRABundlerPass(*PR);
260   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
261   initializeAMDGPUAAWrapperPassPass(*PR);
262   initializeAMDGPUExternalAAWrapperPass(*PR);
263   initializeAMDGPUUseNativeCallsPass(*PR);
264   initializeAMDGPUSimplifyLibCallsPass(*PR);
265   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
266   initializeGCNRegBankReassignPass(*PR);
267   initializeGCNNSAReassignPass(*PR);
268   initializeSIAddIMGInitPass(*PR);
269 }
270 
271 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
272   return std::make_unique<AMDGPUTargetObjectFile>();
273 }
274 
275 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
276   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
277 }
278 
279 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
280   return new SIScheduleDAGMI(C);
281 }
282 
283 static ScheduleDAGInstrs *
284 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
285   ScheduleDAGMILive *DAG =
286     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
287   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
288   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
289   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
290   return DAG;
291 }
292 
293 static ScheduleDAGInstrs *
294 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
295   auto DAG = new GCNIterativeScheduler(C,
296     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
297   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
298   return DAG;
299 }
300 
301 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
302   return new GCNIterativeScheduler(C,
303     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
304 }
305 
306 static ScheduleDAGInstrs *
307 createIterativeILPMachineScheduler(MachineSchedContext *C) {
308   auto DAG = new GCNIterativeScheduler(C,
309     GCNIterativeScheduler::SCHEDULE_ILP);
310   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
311   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
312   return DAG;
313 }
314 
315 static MachineSchedRegistry
316 R600SchedRegistry("r600", "Run R600's custom scheduler",
317                    createR600MachineScheduler);
318 
319 static MachineSchedRegistry
320 SISchedRegistry("si", "Run SI's custom scheduler",
321                 createSIMachineScheduler);
322 
323 static MachineSchedRegistry
324 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
325                              "Run GCN scheduler to maximize occupancy",
326                              createGCNMaxOccupancyMachineScheduler);
327 
328 static MachineSchedRegistry
329 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
330   "Run GCN scheduler to maximize occupancy (experimental)",
331   createIterativeGCNMaxOccupancyMachineScheduler);
332 
333 static MachineSchedRegistry
334 GCNMinRegSchedRegistry("gcn-minreg",
335   "Run GCN iterative scheduler for minimal register usage (experimental)",
336   createMinRegScheduler);
337 
338 static MachineSchedRegistry
339 GCNILPSchedRegistry("gcn-ilp",
340   "Run GCN iterative scheduler for ILP scheduling (experimental)",
341   createIterativeILPMachineScheduler);
342 
343 static StringRef computeDataLayout(const Triple &TT) {
344   if (TT.getArch() == Triple::r600) {
345     // 32-bit pointers.
346     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
347            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
348   }
349 
350   // 32-bit private, local, and region pointers. 64-bit global, constant and
351   // flat, non-integral buffer fat pointers.
352   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
353          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
354          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
355          "-ni:7";
356 }
357 
358 LLVM_READNONE
359 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
360   if (!GPU.empty())
361     return GPU;
362 
363   // Need to default to a target with flat support for HSA.
364   if (TT.getArch() == Triple::amdgcn)
365     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
366 
367   return "r600";
368 }
369 
370 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
371   // The AMDGPU toolchain only supports generating shared objects, so we
372   // must always use PIC.
373   return Reloc::PIC_;
374 }
375 
376 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
377                                          StringRef CPU, StringRef FS,
378                                          TargetOptions Options,
379                                          Optional<Reloc::Model> RM,
380                                          Optional<CodeModel::Model> CM,
381                                          CodeGenOpt::Level OptLevel)
382     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
383                         FS, Options, getEffectiveRelocModel(RM),
384                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
385       TLOF(createTLOF(getTargetTriple())) {
386   initAsmInfo();
387   if (TT.getArch() == Triple::amdgcn) {
388     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
389       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
390     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
391       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
392   }
393   // Set -fixed-function-abi to true if not provided..
394   if (TT.getOS() == Triple::AMDHSA &&
395       EnableAMDGPUFixedFunctionABIOpt.getNumOccurrences() == 0)
396     EnableFixedFunctionABI = true;
397 }
398 
399 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
400 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
401 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
402 
403 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
404 
405 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
406   Attribute GPUAttr = F.getFnAttribute("target-cpu");
407   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
408 }
409 
410 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
411   Attribute FSAttr = F.getFnAttribute("target-features");
412 
413   return FSAttr.isValid() ? FSAttr.getValueAsString()
414                           : getTargetFeatureString();
415 }
416 
417 /// Predicate for Internalize pass.
418 static bool mustPreserveGV(const GlobalValue &GV) {
419   if (const Function *F = dyn_cast<Function>(&GV))
420     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
421 
422   return !GV.use_empty();
423 }
424 
425 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
426   Builder.DivergentTarget = true;
427 
428   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
429   bool Internalize = InternalizeSymbols;
430   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
431   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
432   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
433 
434   if (EnableFunctionCalls) {
435     delete Builder.Inliner;
436     Builder.Inliner = createFunctionInliningPass();
437   }
438 
439   Builder.addExtension(
440     PassManagerBuilder::EP_ModuleOptimizerEarly,
441     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
442                                                legacy::PassManagerBase &PM) {
443       if (AMDGPUAA) {
444         PM.add(createAMDGPUAAWrapperPass());
445         PM.add(createAMDGPUExternalAAWrapperPass());
446       }
447       PM.add(createAMDGPUUnifyMetadataPass());
448       PM.add(createAMDGPUPrintfRuntimeBinding());
449       if (Internalize)
450         PM.add(createInternalizePass(mustPreserveGV));
451       PM.add(createAMDGPUPropagateAttributesLatePass(this));
452       if (Internalize)
453         PM.add(createGlobalDCEPass());
454       if (EarlyInline)
455         PM.add(createAMDGPUAlwaysInlinePass(false));
456   });
457 
458   Builder.addExtension(
459     PassManagerBuilder::EP_EarlyAsPossible,
460     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
461                                       legacy::PassManagerBase &PM) {
462       if (AMDGPUAA) {
463         PM.add(createAMDGPUAAWrapperPass());
464         PM.add(createAMDGPUExternalAAWrapperPass());
465       }
466       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
467       PM.add(llvm::createAMDGPUUseNativeCallsPass());
468       if (LibCallSimplify)
469         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
470   });
471 
472   Builder.addExtension(
473     PassManagerBuilder::EP_CGSCCOptimizerLate,
474     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
475       // Add infer address spaces pass to the opt pipeline after inlining
476       // but before SROA to increase SROA opportunities.
477       PM.add(createInferAddressSpacesPass());
478 
479       // This should run after inlining to have any chance of doing anything,
480       // and before other cleanup optimizations.
481       PM.add(createAMDGPULowerKernelAttributesPass());
482 
483       // Promote alloca to vector before SROA and loop unroll. If we manage
484       // to eliminate allocas before unroll we may choose to unroll less.
485       if (EnableOpt)
486         PM.add(createAMDGPUPromoteAllocaToVector());
487   });
488 }
489 
490 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
491   AAM.registerFunctionAnalysis<AMDGPUAA>();
492 }
493 
494 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
495                                                        bool DebugPassManager) {
496   PB.registerPipelineParsingCallback(
497       [this](StringRef PassName, ModulePassManager &PM,
498              ArrayRef<PassBuilder::PipelineElement>) {
499         if (PassName == "amdgpu-propagate-attributes-late") {
500           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
501           return true;
502         }
503         if (PassName == "amdgpu-unify-metadata") {
504           PM.addPass(AMDGPUUnifyMetadataPass());
505           return true;
506         }
507         if (PassName == "amdgpu-printf-runtime-binding") {
508           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
509           return true;
510         }
511         if (PassName == "amdgpu-always-inline") {
512           PM.addPass(AMDGPUAlwaysInlinePass());
513           return true;
514         }
515         if (PassName == "amdgpu-lower-module-lds") {
516           PM.addPass(AMDGPULowerModuleLDSPass());
517           return true;
518         }
519         return false;
520       });
521   PB.registerPipelineParsingCallback(
522       [this](StringRef PassName, FunctionPassManager &PM,
523              ArrayRef<PassBuilder::PipelineElement>) {
524         if (PassName == "amdgpu-simplifylib") {
525           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
526           return true;
527         }
528         if (PassName == "amdgpu-usenative") {
529           PM.addPass(AMDGPUUseNativeCallsPass());
530           return true;
531         }
532         if (PassName == "amdgpu-promote-alloca") {
533           PM.addPass(AMDGPUPromoteAllocaPass(*this));
534           return true;
535         }
536         if (PassName == "amdgpu-promote-alloca-to-vector") {
537           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
538           return true;
539         }
540         if (PassName == "amdgpu-lower-kernel-attributes") {
541           PM.addPass(AMDGPULowerKernelAttributesPass());
542           return true;
543         }
544         if (PassName == "amdgpu-propagate-attributes-early") {
545           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
546           return true;
547         }
548         return false;
549       });
550 
551   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
552     FAM.registerPass([&] { return AMDGPUAA(); });
553   });
554 
555   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
556     if (AAName == "amdgpu-aa") {
557       AAM.registerFunctionAnalysis<AMDGPUAA>();
558       return true;
559     }
560     return false;
561   });
562 
563   PB.registerPipelineStartEPCallback([this, DebugPassManager](
564                                          ModulePassManager &PM,
565                                          PassBuilder::OptimizationLevel Level) {
566     FunctionPassManager FPM(DebugPassManager);
567     FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
568     FPM.addPass(AMDGPUUseNativeCallsPass());
569     if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
570       FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
571     PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
572   });
573 
574   PB.registerPipelineEarlySimplificationEPCallback(
575       [this](ModulePassManager &PM, PassBuilder::OptimizationLevel Level) {
576         if (Level == PassBuilder::OptimizationLevel::O0)
577           return;
578 
579         PM.addPass(AMDGPUUnifyMetadataPass());
580         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
581 
582         if (InternalizeSymbols) {
583           PM.addPass(InternalizePass(mustPreserveGV));
584         }
585         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
586         if (InternalizeSymbols) {
587           PM.addPass(GlobalDCEPass());
588         }
589         if (EarlyInlineAll && !EnableFunctionCalls)
590           PM.addPass(AMDGPUAlwaysInlinePass());
591       });
592 
593   PB.registerCGSCCOptimizerLateEPCallback(
594       [this, DebugPassManager](CGSCCPassManager &PM,
595                                PassBuilder::OptimizationLevel Level) {
596         if (Level == PassBuilder::OptimizationLevel::O0)
597           return;
598 
599         FunctionPassManager FPM(DebugPassManager);
600 
601         // Add infer address spaces pass to the opt pipeline after inlining
602         // but before SROA to increase SROA opportunities.
603         FPM.addPass(InferAddressSpacesPass());
604 
605         // This should run after inlining to have any chance of doing
606         // anything, and before other cleanup optimizations.
607         FPM.addPass(AMDGPULowerKernelAttributesPass());
608 
609         if (Level != PassBuilder::OptimizationLevel::O0) {
610           // Promote alloca to vector before SROA and loop unroll. If we
611           // manage to eliminate allocas before unroll we may choose to unroll
612           // less.
613           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
614         }
615 
616         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
617       });
618 }
619 
620 //===----------------------------------------------------------------------===//
621 // R600 Target Machine (R600 -> Cayman)
622 //===----------------------------------------------------------------------===//
623 
624 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
625                                      StringRef CPU, StringRef FS,
626                                      TargetOptions Options,
627                                      Optional<Reloc::Model> RM,
628                                      Optional<CodeModel::Model> CM,
629                                      CodeGenOpt::Level OL, bool JIT)
630     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
631   setRequiresStructuredCFG(true);
632 
633   // Override the default since calls aren't supported for r600.
634   if (EnableFunctionCalls &&
635       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
636     EnableFunctionCalls = false;
637 }
638 
639 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
640   const Function &F) const {
641   StringRef GPU = getGPUName(F);
642   StringRef FS = getFeatureString(F);
643 
644   SmallString<128> SubtargetKey(GPU);
645   SubtargetKey.append(FS);
646 
647   auto &I = SubtargetMap[SubtargetKey];
648   if (!I) {
649     // This needs to be done before we create a new subtarget since any
650     // creation will depend on the TM and the code generation flags on the
651     // function that reside in TargetOptions.
652     resetTargetOptions(F);
653     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
654   }
655 
656   return I.get();
657 }
658 
659 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
660   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
661           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
662           AddrSpace == AMDGPUAS::REGION_ADDRESS)
663              ? -1
664              : 0;
665 }
666 
667 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
668                                               unsigned DestAS) const {
669   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
670          AMDGPU::isFlatGlobalAddrSpace(DestAS);
671 }
672 
673 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
674   const auto *LD = dyn_cast<LoadInst>(V);
675   if (!LD)
676     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
677 
678   // It must be a generic pointer loaded.
679   assert(V->getType()->isPointerTy() &&
680          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
681 
682   const auto *Ptr = LD->getPointerOperand();
683   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
684     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
685   // For a generic pointer loaded from the constant memory, it could be assumed
686   // as a global pointer since the constant memory is only populated on the
687   // host side. As implied by the offload programming model, only global
688   // pointers could be referenced on the host side.
689   return AMDGPUAS::GLOBAL_ADDRESS;
690 }
691 
692 TargetTransformInfo
693 R600TargetMachine::getTargetTransformInfo(const Function &F) {
694   return TargetTransformInfo(R600TTIImpl(this, F));
695 }
696 
697 //===----------------------------------------------------------------------===//
698 // GCN Target Machine (SI+)
699 //===----------------------------------------------------------------------===//
700 
701 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
702                                    StringRef CPU, StringRef FS,
703                                    TargetOptions Options,
704                                    Optional<Reloc::Model> RM,
705                                    Optional<CodeModel::Model> CM,
706                                    CodeGenOpt::Level OL, bool JIT)
707     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
708 
709 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
710   StringRef GPU = getGPUName(F);
711   StringRef FS = getFeatureString(F);
712 
713   SmallString<128> SubtargetKey(GPU);
714   SubtargetKey.append(FS);
715 
716   auto &I = SubtargetMap[SubtargetKey];
717   if (!I) {
718     // This needs to be done before we create a new subtarget since any
719     // creation will depend on the TM and the code generation flags on the
720     // function that reside in TargetOptions.
721     resetTargetOptions(F);
722     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
723   }
724 
725   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
726 
727   return I.get();
728 }
729 
730 TargetTransformInfo
731 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
732   return TargetTransformInfo(GCNTTIImpl(this, F));
733 }
734 
735 //===----------------------------------------------------------------------===//
736 // AMDGPU Pass Setup
737 //===----------------------------------------------------------------------===//
738 
739 namespace {
740 
741 class AMDGPUPassConfig : public TargetPassConfig {
742 public:
743   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
744     : TargetPassConfig(TM, PM) {
745     // Exceptions and StackMaps are not supported, so these passes will never do
746     // anything.
747     disablePass(&StackMapLivenessID);
748     disablePass(&FuncletLayoutID);
749   }
750 
751   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
752     return getTM<AMDGPUTargetMachine>();
753   }
754 
755   ScheduleDAGInstrs *
756   createMachineScheduler(MachineSchedContext *C) const override {
757     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
758     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
759     return DAG;
760   }
761 
762   void addEarlyCSEOrGVNPass();
763   void addStraightLineScalarOptimizationPasses();
764   void addIRPasses() override;
765   void addCodeGenPrepare() override;
766   bool addPreISel() override;
767   bool addInstSelector() override;
768   bool addGCPasses() override;
769 
770   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
771 };
772 
773 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
774   return getStandardCSEConfigForOpt(TM->getOptLevel());
775 }
776 
777 class R600PassConfig final : public AMDGPUPassConfig {
778 public:
779   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
780     : AMDGPUPassConfig(TM, PM) {}
781 
782   ScheduleDAGInstrs *createMachineScheduler(
783     MachineSchedContext *C) const override {
784     return createR600MachineScheduler(C);
785   }
786 
787   bool addPreISel() override;
788   bool addInstSelector() override;
789   void addPreRegAlloc() override;
790   void addPreSched2() override;
791   void addPreEmitPass() override;
792 };
793 
794 class GCNPassConfig final : public AMDGPUPassConfig {
795 public:
796   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
797     : AMDGPUPassConfig(TM, PM) {
798     // It is necessary to know the register usage of the entire call graph.  We
799     // allow calls without EnableAMDGPUFunctionCalls if they are marked
800     // noinline, so this is always required.
801     setRequiresCodeGenSCCOrder(true);
802   }
803 
804   GCNTargetMachine &getGCNTargetMachine() const {
805     return getTM<GCNTargetMachine>();
806   }
807 
808   ScheduleDAGInstrs *
809   createMachineScheduler(MachineSchedContext *C) const override;
810 
811   bool addPreISel() override;
812   void addMachineSSAOptimization() override;
813   bool addILPOpts() override;
814   bool addInstSelector() override;
815   bool addIRTranslator() override;
816   void addPreLegalizeMachineIR() override;
817   bool addLegalizeMachineIR() override;
818   void addPreRegBankSelect() override;
819   bool addRegBankSelect() override;
820   void addPreGlobalInstructionSelect() override;
821   bool addGlobalInstructionSelect() override;
822   void addFastRegAlloc() override;
823   void addOptimizedRegAlloc() override;
824   void addPreRegAlloc() override;
825   bool addPreRewrite() override;
826   void addPostRegAlloc() override;
827   void addPreSched2() override;
828   void addPreEmitPass() override;
829 };
830 
831 } // end anonymous namespace
832 
833 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
834   if (getOptLevel() == CodeGenOpt::Aggressive)
835     addPass(createGVNPass());
836   else
837     addPass(createEarlyCSEPass());
838 }
839 
840 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
841   addPass(createLICMPass());
842   addPass(createSeparateConstOffsetFromGEPPass());
843   addPass(createSpeculativeExecutionPass());
844   // ReassociateGEPs exposes more opportunites for SLSR. See
845   // the example in reassociate-geps-and-slsr.ll.
846   addPass(createStraightLineStrengthReducePass());
847   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
848   // EarlyCSE can reuse.
849   addEarlyCSEOrGVNPass();
850   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
851   addPass(createNaryReassociatePass());
852   // NaryReassociate on GEPs creates redundant common expressions, so run
853   // EarlyCSE after it.
854   addPass(createEarlyCSEPass());
855 }
856 
857 void AMDGPUPassConfig::addIRPasses() {
858   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
859 
860   // There is no reason to run these.
861   disablePass(&StackMapLivenessID);
862   disablePass(&FuncletLayoutID);
863   disablePass(&PatchableFunctionID);
864 
865   addPass(createAMDGPUPrintfRuntimeBinding());
866 
867   // This must occur before inlining, as the inliner will not look through
868   // bitcast calls.
869   addPass(createAMDGPUFixFunctionBitcastsPass());
870 
871   // A call to propagate attributes pass in the backend in case opt was not run.
872   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
873 
874   addPass(createAtomicExpandPass());
875 
876 
877   addPass(createAMDGPULowerIntrinsicsPass());
878 
879   // Function calls are not supported, so make sure we inline everything.
880   addPass(createAMDGPUAlwaysInlinePass());
881   addPass(createAlwaysInlinerLegacyPass());
882   // We need to add the barrier noop pass, otherwise adding the function
883   // inlining pass will cause all of the PassConfigs passes to be run
884   // one function at a time, which means if we have a nodule with two
885   // functions, then we will generate code for the first function
886   // without ever running any passes on the second.
887   addPass(createBarrierNoopPass());
888 
889   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
890   if (TM.getTargetTriple().getArch() == Triple::r600)
891     addPass(createR600OpenCLImageTypeLoweringPass());
892 
893   // Replace OpenCL enqueued block function pointers with global variables.
894   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
895 
896   // Can increase LDS used by kernel so runs before PromoteAlloca
897   if (!DisableLowerModuleLDS)
898     addPass(createAMDGPULowerModuleLDSPass());
899 
900   if (TM.getOptLevel() > CodeGenOpt::None) {
901     addPass(createInferAddressSpacesPass());
902     addPass(createAMDGPUPromoteAlloca());
903 
904     if (EnableSROA)
905       addPass(createSROAPass());
906 
907     if (EnableScalarIRPasses)
908       addStraightLineScalarOptimizationPasses();
909 
910     if (EnableAMDGPUAliasAnalysis) {
911       addPass(createAMDGPUAAWrapperPass());
912       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
913                                              AAResults &AAR) {
914         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
915           AAR.addAAResult(WrapperPass->getResult());
916         }));
917     }
918   }
919 
920   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
921     // TODO: May want to move later or split into an early and late one.
922     addPass(createAMDGPUCodeGenPreparePass());
923   }
924 
925   TargetPassConfig::addIRPasses();
926 
927   // EarlyCSE is not always strong enough to clean up what LSR produces. For
928   // example, GVN can combine
929   //
930   //   %0 = add %a, %b
931   //   %1 = add %b, %a
932   //
933   // and
934   //
935   //   %0 = shl nsw %a, 2
936   //   %1 = shl %a, 2
937   //
938   // but EarlyCSE can do neither of them.
939   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
940     addEarlyCSEOrGVNPass();
941 }
942 
943 void AMDGPUPassConfig::addCodeGenPrepare() {
944   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
945     addPass(createAMDGPUAnnotateKernelFeaturesPass());
946 
947   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
948       EnableLowerKernelArguments)
949     addPass(createAMDGPULowerKernelArgumentsPass());
950 
951   addPass(&AMDGPUPerfHintAnalysisID);
952 
953   TargetPassConfig::addCodeGenPrepare();
954 
955   if (EnableLoadStoreVectorizer)
956     addPass(createLoadStoreVectorizerPass());
957 
958   // LowerSwitch pass may introduce unreachable blocks that can
959   // cause unexpected behavior for subsequent passes. Placing it
960   // here seems better that these blocks would get cleaned up by
961   // UnreachableBlockElim inserted next in the pass flow.
962   addPass(createLowerSwitchPass());
963 }
964 
965 bool AMDGPUPassConfig::addPreISel() {
966   addPass(createFlattenCFGPass());
967   return false;
968 }
969 
970 bool AMDGPUPassConfig::addInstSelector() {
971   // Defer the verifier until FinalizeISel.
972   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
973   return false;
974 }
975 
976 bool AMDGPUPassConfig::addGCPasses() {
977   // Do nothing. GC is not supported.
978   return false;
979 }
980 
981 //===----------------------------------------------------------------------===//
982 // R600 Pass Setup
983 //===----------------------------------------------------------------------===//
984 
985 bool R600PassConfig::addPreISel() {
986   AMDGPUPassConfig::addPreISel();
987 
988   if (EnableR600StructurizeCFG)
989     addPass(createStructurizeCFGPass());
990   return false;
991 }
992 
993 bool R600PassConfig::addInstSelector() {
994   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
995   return false;
996 }
997 
998 void R600PassConfig::addPreRegAlloc() {
999   addPass(createR600VectorRegMerger());
1000 }
1001 
1002 void R600PassConfig::addPreSched2() {
1003   addPass(createR600EmitClauseMarkers(), false);
1004   if (EnableR600IfConvert)
1005     addPass(&IfConverterID, false);
1006   addPass(createR600ClauseMergePass(), false);
1007 }
1008 
1009 void R600PassConfig::addPreEmitPass() {
1010   addPass(createAMDGPUCFGStructurizerPass(), false);
1011   addPass(createR600ExpandSpecialInstrsPass(), false);
1012   addPass(&FinalizeMachineBundlesID, false);
1013   addPass(createR600Packetizer(), false);
1014   addPass(createR600ControlFlowFinalizer(), false);
1015 }
1016 
1017 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
1018   return new R600PassConfig(*this, PM);
1019 }
1020 
1021 //===----------------------------------------------------------------------===//
1022 // GCN Pass Setup
1023 //===----------------------------------------------------------------------===//
1024 
1025 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1026   MachineSchedContext *C) const {
1027   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1028   if (ST.enableSIScheduler())
1029     return createSIMachineScheduler(C);
1030   return createGCNMaxOccupancyMachineScheduler(C);
1031 }
1032 
1033 bool GCNPassConfig::addPreISel() {
1034   AMDGPUPassConfig::addPreISel();
1035 
1036   addPass(createAMDGPULateCodeGenPreparePass());
1037   if (EnableAtomicOptimizations) {
1038     addPass(createAMDGPUAtomicOptimizerPass());
1039   }
1040 
1041   // FIXME: We need to run a pass to propagate the attributes when calls are
1042   // supported.
1043 
1044   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1045   // regions formed by them.
1046   addPass(&AMDGPUUnifyDivergentExitNodesID);
1047   if (!LateCFGStructurize) {
1048     if (EnableStructurizerWorkarounds) {
1049       addPass(createFixIrreduciblePass());
1050       addPass(createUnifyLoopExitsPass());
1051     }
1052     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1053   }
1054   addPass(createSinkingPass());
1055   addPass(createAMDGPUAnnotateUniformValues());
1056   if (!LateCFGStructurize) {
1057     addPass(createSIAnnotateControlFlowPass());
1058   }
1059   addPass(createLCSSAPass());
1060 
1061   return false;
1062 }
1063 
1064 void GCNPassConfig::addMachineSSAOptimization() {
1065   TargetPassConfig::addMachineSSAOptimization();
1066 
1067   // We want to fold operands after PeepholeOptimizer has run (or as part of
1068   // it), because it will eliminate extra copies making it easier to fold the
1069   // real source operand. We want to eliminate dead instructions after, so that
1070   // we see fewer uses of the copies. We then need to clean up the dead
1071   // instructions leftover after the operands are folded as well.
1072   //
1073   // XXX - Can we get away without running DeadMachineInstructionElim again?
1074   addPass(&SIFoldOperandsID);
1075   if (EnableDPPCombine)
1076     addPass(&GCNDPPCombineID);
1077   addPass(&DeadMachineInstructionElimID);
1078   addPass(&SILoadStoreOptimizerID);
1079   if (EnableSDWAPeephole) {
1080     addPass(&SIPeepholeSDWAID);
1081     addPass(&EarlyMachineLICMID);
1082     addPass(&MachineCSEID);
1083     addPass(&SIFoldOperandsID);
1084     addPass(&DeadMachineInstructionElimID);
1085   }
1086   addPass(createSIShrinkInstructionsPass());
1087 }
1088 
1089 bool GCNPassConfig::addILPOpts() {
1090   if (EnableEarlyIfConversion)
1091     addPass(&EarlyIfConverterID);
1092 
1093   TargetPassConfig::addILPOpts();
1094   return false;
1095 }
1096 
1097 bool GCNPassConfig::addInstSelector() {
1098   AMDGPUPassConfig::addInstSelector();
1099   addPass(&SIFixSGPRCopiesID);
1100   addPass(createSILowerI1CopiesPass());
1101   addPass(createSIAddIMGInitPass());
1102   return false;
1103 }
1104 
1105 bool GCNPassConfig::addIRTranslator() {
1106   addPass(new IRTranslator(getOptLevel()));
1107   return false;
1108 }
1109 
1110 void GCNPassConfig::addPreLegalizeMachineIR() {
1111   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1112   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1113   addPass(new Localizer());
1114 }
1115 
1116 bool GCNPassConfig::addLegalizeMachineIR() {
1117   addPass(new Legalizer());
1118   return false;
1119 }
1120 
1121 void GCNPassConfig::addPreRegBankSelect() {
1122   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1123   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1124 }
1125 
1126 bool GCNPassConfig::addRegBankSelect() {
1127   addPass(new RegBankSelect());
1128   return false;
1129 }
1130 
1131 void GCNPassConfig::addPreGlobalInstructionSelect() {
1132   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1133   addPass(createAMDGPURegBankCombiner(IsOptNone));
1134 }
1135 
1136 bool GCNPassConfig::addGlobalInstructionSelect() {
1137   addPass(new InstructionSelect(getOptLevel()));
1138   // TODO: Fix instruction selection to do the right thing for image
1139   // instructions with tfe or lwe in the first place, instead of running a
1140   // separate pass to fix them up?
1141   addPass(createSIAddIMGInitPass());
1142   return false;
1143 }
1144 
1145 void GCNPassConfig::addPreRegAlloc() {
1146   if (LateCFGStructurize) {
1147     addPass(createAMDGPUMachineCFGStructurizerPass());
1148   }
1149 }
1150 
1151 void GCNPassConfig::addFastRegAlloc() {
1152   // FIXME: We have to disable the verifier here because of PHIElimination +
1153   // TwoAddressInstructions disabling it.
1154 
1155   // This must be run immediately after phi elimination and before
1156   // TwoAddressInstructions, otherwise the processing of the tied operand of
1157   // SI_ELSE will introduce a copy of the tied operand source after the else.
1158   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1159 
1160   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1161   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1162 
1163   TargetPassConfig::addFastRegAlloc();
1164 }
1165 
1166 void GCNPassConfig::addOptimizedRegAlloc() {
1167   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1168   // instructions that cause scheduling barriers.
1169   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1170   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1171 
1172   if (OptExecMaskPreRA)
1173     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1174   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1175 
1176   // This must be run immediately after phi elimination and before
1177   // TwoAddressInstructions, otherwise the processing of the tied operand of
1178   // SI_ELSE will introduce a copy of the tied operand source after the else.
1179   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1180 
1181   if (EnableDCEInRA)
1182     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1183 
1184   TargetPassConfig::addOptimizedRegAlloc();
1185 }
1186 
1187 bool GCNPassConfig::addPreRewrite() {
1188   if (EnableRegReassign) {
1189     addPass(&GCNNSAReassignID);
1190     addPass(&GCNRegBankReassignID);
1191   }
1192   return true;
1193 }
1194 
1195 void GCNPassConfig::addPostRegAlloc() {
1196   addPass(&SIFixVGPRCopiesID);
1197   if (getOptLevel() > CodeGenOpt::None)
1198     addPass(&SIOptimizeExecMaskingID);
1199   TargetPassConfig::addPostRegAlloc();
1200 
1201   // Equivalent of PEI for SGPRs.
1202   addPass(&SILowerSGPRSpillsID);
1203 }
1204 
1205 void GCNPassConfig::addPreSched2() {
1206   addPass(&SIPostRABundlerID);
1207 }
1208 
1209 void GCNPassConfig::addPreEmitPass() {
1210   addPass(createSIMemoryLegalizerPass());
1211   addPass(createSIInsertWaitcntsPass());
1212   addPass(createSIShrinkInstructionsPass());
1213   addPass(createSIModeRegisterPass());
1214 
1215   if (getOptLevel() > CodeGenOpt::None)
1216     addPass(&SIInsertHardClausesID);
1217 
1218   addPass(&SIRemoveShortExecBranchesID);
1219   addPass(&SIInsertSkipsPassID);
1220   addPass(&SIPreEmitPeepholeID);
1221   // The hazard recognizer that runs as part of the post-ra scheduler does not
1222   // guarantee to be able handle all hazards correctly. This is because if there
1223   // are multiple scheduling regions in a basic block, the regions are scheduled
1224   // bottom up, so when we begin to schedule a region we don't know what
1225   // instructions were emitted directly before it.
1226   //
1227   // Here we add a stand-alone hazard recognizer pass which can handle all
1228   // cases.
1229   addPass(&PostRAHazardRecognizerID);
1230   addPass(&BranchRelaxationPassID);
1231 }
1232 
1233 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1234   return new GCNPassConfig(*this, PM);
1235 }
1236 
1237 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1238   return new yaml::SIMachineFunctionInfo();
1239 }
1240 
1241 yaml::MachineFunctionInfo *
1242 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1243   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1244   return new yaml::SIMachineFunctionInfo(*MFI,
1245                                          *MF.getSubtarget().getRegisterInfo());
1246 }
1247 
1248 bool GCNTargetMachine::parseMachineFunctionInfo(
1249     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1250     SMDiagnostic &Error, SMRange &SourceRange) const {
1251   const yaml::SIMachineFunctionInfo &YamlMFI =
1252       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1253   MachineFunction &MF = PFS.MF;
1254   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1255 
1256   MFI->initializeBaseYamlFields(YamlMFI);
1257 
1258   if (MFI->Occupancy == 0) {
1259     // Fixup the subtarget dependent default value.
1260     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1261     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1262   }
1263 
1264   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1265     Register TempReg;
1266     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1267       SourceRange = RegName.SourceRange;
1268       return true;
1269     }
1270     RegVal = TempReg;
1271 
1272     return false;
1273   };
1274 
1275   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1276     // Create a diagnostic for a the register string literal.
1277     const MemoryBuffer &Buffer =
1278         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1279     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1280                          RegName.Value.size(), SourceMgr::DK_Error,
1281                          "incorrect register class for field", RegName.Value,
1282                          None, None);
1283     SourceRange = RegName.SourceRange;
1284     return true;
1285   };
1286 
1287   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1288       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1289       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1290     return true;
1291 
1292   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1293       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1294     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1295   }
1296 
1297   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1298       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1299     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1300   }
1301 
1302   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1303       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1304     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1305   }
1306 
1307   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1308                                    const TargetRegisterClass &RC,
1309                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1310                                    unsigned SystemSGPRs) {
1311     // Skip parsing if it's not present.
1312     if (!A)
1313       return false;
1314 
1315     if (A->IsRegister) {
1316       Register Reg;
1317       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1318         SourceRange = A->RegisterName.SourceRange;
1319         return true;
1320       }
1321       if (!RC.contains(Reg))
1322         return diagnoseRegisterClass(A->RegisterName);
1323       Arg = ArgDescriptor::createRegister(Reg);
1324     } else
1325       Arg = ArgDescriptor::createStack(A->StackOffset);
1326     // Check and apply the optional mask.
1327     if (A->Mask)
1328       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1329 
1330     MFI->NumUserSGPRs += UserSGPRs;
1331     MFI->NumSystemSGPRs += SystemSGPRs;
1332     return false;
1333   };
1334 
1335   if (YamlMFI.ArgInfo &&
1336       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1337                              AMDGPU::SGPR_128RegClass,
1338                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1339        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1340                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1341                              2, 0) ||
1342        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1343                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1344        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1345                              AMDGPU::SReg_64RegClass,
1346                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1347        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1348                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1349                              2, 0) ||
1350        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1351                              AMDGPU::SReg_64RegClass,
1352                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1353        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1354                              AMDGPU::SGPR_32RegClass,
1355                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1356        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1357                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1358                              0, 1) ||
1359        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1360                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1361                              0, 1) ||
1362        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1363                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1364                              0, 1) ||
1365        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1366                              AMDGPU::SGPR_32RegClass,
1367                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1368        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1369                              AMDGPU::SGPR_32RegClass,
1370                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1371        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1372                              AMDGPU::SReg_64RegClass,
1373                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1374        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1375                              AMDGPU::SReg_64RegClass,
1376                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1377        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1378                              AMDGPU::VGPR_32RegClass,
1379                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1380        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1381                              AMDGPU::VGPR_32RegClass,
1382                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1383        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1384                              AMDGPU::VGPR_32RegClass,
1385                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1386     return true;
1387 
1388   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1389   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1390   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1391   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1392   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1393   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1394 
1395   return false;
1396 }
1397