1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600MachineScheduler.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIMachineScheduler.h"
27 #include "TargetInfo/AMDGPUTargetInfo.h"
28 #include "llvm/Analysis/CGSCCPassManager.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/Localizer.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MIRParser/MIParser.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/LegacyPassManager.h"
37 #include "llvm/IR/PassManager.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/Passes/PassBuilder.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Transforms/IPO.h"
42 #include "llvm/Transforms/IPO/AlwaysInliner.h"
43 #include "llvm/Transforms/IPO/GlobalDCE.h"
44 #include "llvm/Transforms/IPO/Internalize.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
49 #include "llvm/Transforms/Utils.h"
50 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
51 #include "llvm/Transforms/Vectorize.h"
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73             cl::desc("Run pre-RA exec mask optimizations"),
74             cl::init(true));
75 
76 static cl::opt<bool> EnableR600IfConvert(
77   "r600-if-convert",
78   cl::desc("Use if conversion pass"),
79   cl::ReallyHidden,
80   cl::init(true));
81 
82 // Option to disable vectorizer for tests.
83 static cl::opt<bool> EnableLoadStoreVectorizer(
84   "amdgpu-load-store-vectorizer",
85   cl::desc("Enable load store vectorizer"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to control global loads scalarization
90 static cl::opt<bool> ScalarizeGlobal(
91   "amdgpu-scalarize-global-loads",
92   cl::desc("Enable global load scalarization"),
93   cl::init(true),
94   cl::Hidden);
95 
96 // Option to run internalize pass.
97 static cl::opt<bool> InternalizeSymbols(
98   "amdgpu-internalize-symbols",
99   cl::desc("Enable elimination of non-kernel functions and unused globals"),
100   cl::init(false),
101   cl::Hidden);
102 
103 // Option to inline all early.
104 static cl::opt<bool> EarlyInlineAll(
105   "amdgpu-early-inline-all",
106   cl::desc("Inline all functions early"),
107   cl::init(false),
108   cl::Hidden);
109 
110 static cl::opt<bool> EnableSDWAPeephole(
111   "amdgpu-sdwa-peephole",
112   cl::desc("Enable SDWA peepholer"),
113   cl::init(true));
114 
115 static cl::opt<bool> EnableDPPCombine(
116   "amdgpu-dpp-combine",
117   cl::desc("Enable DPP combiner"),
118   cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122   cl::desc("Enable AMDGPU Alias Analysis"),
123   cl::init(true));
124 
125 // Option to run late CFG structurizer
126 static cl::opt<bool, true> LateCFGStructurize(
127   "amdgpu-late-structurize",
128   cl::desc("Enable late CFG structurization"),
129   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
130   cl::Hidden);
131 
132 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
133   "amdgpu-function-calls",
134   cl::desc("Enable AMDGPU function call support"),
135   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
136   cl::init(true),
137   cl::Hidden);
138 
139 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
140   "amdgpu-fixed-function-abi",
141   cl::desc("Enable all implicit function arguments"),
142   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
143   cl::init(false),
144   cl::Hidden);
145 
146 // Enable lib calls simplifications
147 static cl::opt<bool> EnableLibCallSimplify(
148   "amdgpu-simplify-libcall",
149   cl::desc("Enable amdgpu library simplifications"),
150   cl::init(true),
151   cl::Hidden);
152 
153 static cl::opt<bool> EnableLowerKernelArguments(
154   "amdgpu-ir-lower-kernel-arguments",
155   cl::desc("Lower kernel argument loads in IR pass"),
156   cl::init(true),
157   cl::Hidden);
158 
159 static cl::opt<bool> EnableRegReassign(
160   "amdgpu-reassign-regs",
161   cl::desc("Enable register reassign optimizations on gfx10+"),
162   cl::init(true),
163   cl::Hidden);
164 
165 // Enable atomic optimization
166 static cl::opt<bool> EnableAtomicOptimizations(
167   "amdgpu-atomic-optimizations",
168   cl::desc("Enable atomic optimizations"),
169   cl::init(false),
170   cl::Hidden);
171 
172 // Enable Mode register optimization
173 static cl::opt<bool> EnableSIModeRegisterPass(
174   "amdgpu-mode-register",
175   cl::desc("Enable mode register pass"),
176   cl::init(true),
177   cl::Hidden);
178 
179 // Option is used in lit tests to prevent deadcoding of patterns inspected.
180 static cl::opt<bool>
181 EnableDCEInRA("amdgpu-dce-in-ra",
182     cl::init(true), cl::Hidden,
183     cl::desc("Enable machine DCE inside regalloc"));
184 
185 static cl::opt<bool> EnableScalarIRPasses(
186   "amdgpu-scalar-ir-passes",
187   cl::desc("Enable scalar IR passes"),
188   cl::init(true),
189   cl::Hidden);
190 
191 static cl::opt<bool> EnableStructurizerWorkarounds(
192     "amdgpu-enable-structurizer-workarounds",
193     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
194     cl::Hidden);
195 
196 static cl::opt<bool, true> EnableLowerModuleLDS(
197     "amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"),
198     cl::location(AMDGPUTargetMachine::EnableLowerModuleLDS), cl::init(true),
199     cl::Hidden);
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFoldOperandsPass(*PR);
220   initializeSIPeepholeSDWAPass(*PR);
221   initializeSIShrinkInstructionsPass(*PR);
222   initializeSIOptimizeExecMaskingPreRAPass(*PR);
223   initializeSILoadStoreOptimizerPass(*PR);
224   initializeAMDGPUFixFunctionBitcastsPass(*PR);
225   initializeAMDGPUAlwaysInlinePass(*PR);
226   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
227   initializeAMDGPUAnnotateUniformValuesPass(*PR);
228   initializeAMDGPUArgumentUsageInfoPass(*PR);
229   initializeAMDGPUAtomicOptimizerPass(*PR);
230   initializeAMDGPULowerKernelArgumentsPass(*PR);
231   initializeAMDGPULowerKernelAttributesPass(*PR);
232   initializeAMDGPULowerIntrinsicsPass(*PR);
233   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
234   initializeAMDGPUPostLegalizerCombinerPass(*PR);
235   initializeAMDGPUPreLegalizerCombinerPass(*PR);
236   initializeAMDGPURegBankCombinerPass(*PR);
237   initializeAMDGPUPromoteAllocaPass(*PR);
238   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
239   initializeAMDGPUCodeGenPreparePass(*PR);
240   initializeAMDGPULateCodeGenPreparePass(*PR);
241   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
242   initializeAMDGPUPropagateAttributesLatePass(*PR);
243   initializeAMDGPULowerModuleLDSPass(*PR);
244   initializeAMDGPURewriteOutArgumentsPass(*PR);
245   initializeAMDGPUUnifyMetadataPass(*PR);
246   initializeSIAnnotateControlFlowPass(*PR);
247   initializeSIInsertHardClausesPass(*PR);
248   initializeSIInsertWaitcntsPass(*PR);
249   initializeSIModeRegisterPass(*PR);
250   initializeSIWholeQuadModePass(*PR);
251   initializeSILowerControlFlowPass(*PR);
252   initializeSIPreEmitPeepholePass(*PR);
253   initializeSILateBranchLoweringPass(*PR);
254   initializeSIMemoryLegalizerPass(*PR);
255   initializeSIOptimizeExecMaskingPass(*PR);
256   initializeSIPreAllocateWWMRegsPass(*PR);
257   initializeSIFormMemoryClausesPass(*PR);
258   initializeSIPostRABundlerPass(*PR);
259   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
260   initializeAMDGPUAAWrapperPassPass(*PR);
261   initializeAMDGPUExternalAAWrapperPass(*PR);
262   initializeAMDGPUUseNativeCallsPass(*PR);
263   initializeAMDGPUSimplifyLibCallsPass(*PR);
264   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
265   initializeGCNRegBankReassignPass(*PR);
266   initializeGCNNSAReassignPass(*PR);
267 }
268 
269 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
270   return std::make_unique<AMDGPUTargetObjectFile>();
271 }
272 
273 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
274   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
275 }
276 
277 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
278   return new SIScheduleDAGMI(C);
279 }
280 
281 static ScheduleDAGInstrs *
282 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
283   ScheduleDAGMILive *DAG =
284     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
285   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
286   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
287   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
288   return DAG;
289 }
290 
291 static ScheduleDAGInstrs *
292 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
293   auto DAG = new GCNIterativeScheduler(C,
294     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
295   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
296   return DAG;
297 }
298 
299 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
300   return new GCNIterativeScheduler(C,
301     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
302 }
303 
304 static ScheduleDAGInstrs *
305 createIterativeILPMachineScheduler(MachineSchedContext *C) {
306   auto DAG = new GCNIterativeScheduler(C,
307     GCNIterativeScheduler::SCHEDULE_ILP);
308   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
309   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
310   return DAG;
311 }
312 
313 static MachineSchedRegistry
314 R600SchedRegistry("r600", "Run R600's custom scheduler",
315                    createR600MachineScheduler);
316 
317 static MachineSchedRegistry
318 SISchedRegistry("si", "Run SI's custom scheduler",
319                 createSIMachineScheduler);
320 
321 static MachineSchedRegistry
322 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
323                              "Run GCN scheduler to maximize occupancy",
324                              createGCNMaxOccupancyMachineScheduler);
325 
326 static MachineSchedRegistry
327 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
328   "Run GCN scheduler to maximize occupancy (experimental)",
329   createIterativeGCNMaxOccupancyMachineScheduler);
330 
331 static MachineSchedRegistry
332 GCNMinRegSchedRegistry("gcn-minreg",
333   "Run GCN iterative scheduler for minimal register usage (experimental)",
334   createMinRegScheduler);
335 
336 static MachineSchedRegistry
337 GCNILPSchedRegistry("gcn-ilp",
338   "Run GCN iterative scheduler for ILP scheduling (experimental)",
339   createIterativeILPMachineScheduler);
340 
341 static StringRef computeDataLayout(const Triple &TT) {
342   if (TT.getArch() == Triple::r600) {
343     // 32-bit pointers.
344     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
345            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
346   }
347 
348   // 32-bit private, local, and region pointers. 64-bit global, constant and
349   // flat, non-integral buffer fat pointers.
350   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
351          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
352          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
353          "-ni:7";
354 }
355 
356 LLVM_READNONE
357 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
358   if (!GPU.empty())
359     return GPU;
360 
361   // Need to default to a target with flat support for HSA.
362   if (TT.getArch() == Triple::amdgcn)
363     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
364 
365   return "r600";
366 }
367 
368 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
369   // The AMDGPU toolchain only supports generating shared objects, so we
370   // must always use PIC.
371   return Reloc::PIC_;
372 }
373 
374 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
375                                          StringRef CPU, StringRef FS,
376                                          TargetOptions Options,
377                                          Optional<Reloc::Model> RM,
378                                          Optional<CodeModel::Model> CM,
379                                          CodeGenOpt::Level OptLevel)
380     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
381                         FS, Options, getEffectiveRelocModel(RM),
382                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
383       TLOF(createTLOF(getTargetTriple())) {
384   initAsmInfo();
385   if (TT.getArch() == Triple::amdgcn) {
386     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
387       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
388     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
389       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
390   }
391 }
392 
393 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
394 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
395 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
396 bool AMDGPUTargetMachine::EnableLowerModuleLDS = true;
397 
398 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
399 
400 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
401   Attribute GPUAttr = F.getFnAttribute("target-cpu");
402   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
403 }
404 
405 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
406   Attribute FSAttr = F.getFnAttribute("target-features");
407 
408   return FSAttr.isValid() ? FSAttr.getValueAsString()
409                           : getTargetFeatureString();
410 }
411 
412 /// Predicate for Internalize pass.
413 static bool mustPreserveGV(const GlobalValue &GV) {
414   if (const Function *F = dyn_cast<Function>(&GV))
415     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
416 
417   return !GV.use_empty();
418 }
419 
420 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
421   Builder.DivergentTarget = true;
422 
423   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
424   bool Internalize = InternalizeSymbols;
425   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
426   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
427   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
428 
429   if (EnableFunctionCalls) {
430     delete Builder.Inliner;
431     Builder.Inliner = createFunctionInliningPass();
432   }
433 
434   Builder.addExtension(
435     PassManagerBuilder::EP_ModuleOptimizerEarly,
436     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
437                                                legacy::PassManagerBase &PM) {
438       if (AMDGPUAA) {
439         PM.add(createAMDGPUAAWrapperPass());
440         PM.add(createAMDGPUExternalAAWrapperPass());
441       }
442       PM.add(createAMDGPUUnifyMetadataPass());
443       PM.add(createAMDGPUPrintfRuntimeBinding());
444       if (Internalize)
445         PM.add(createInternalizePass(mustPreserveGV));
446       PM.add(createAMDGPUPropagateAttributesLatePass(this));
447       if (Internalize)
448         PM.add(createGlobalDCEPass());
449       if (EarlyInline)
450         PM.add(createAMDGPUAlwaysInlinePass(false));
451   });
452 
453   Builder.addExtension(
454     PassManagerBuilder::EP_EarlyAsPossible,
455     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
456                                       legacy::PassManagerBase &PM) {
457       if (AMDGPUAA) {
458         PM.add(createAMDGPUAAWrapperPass());
459         PM.add(createAMDGPUExternalAAWrapperPass());
460       }
461       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
462       PM.add(llvm::createAMDGPUUseNativeCallsPass());
463       if (LibCallSimplify)
464         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
465   });
466 
467   Builder.addExtension(
468     PassManagerBuilder::EP_CGSCCOptimizerLate,
469     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
470       // Add infer address spaces pass to the opt pipeline after inlining
471       // but before SROA to increase SROA opportunities.
472       PM.add(createInferAddressSpacesPass());
473 
474       // This should run after inlining to have any chance of doing anything,
475       // and before other cleanup optimizations.
476       PM.add(createAMDGPULowerKernelAttributesPass());
477 
478       // Promote alloca to vector before SROA and loop unroll. If we manage
479       // to eliminate allocas before unroll we may choose to unroll less.
480       if (EnableOpt)
481         PM.add(createAMDGPUPromoteAllocaToVector());
482   });
483 }
484 
485 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
486   AAM.registerFunctionAnalysis<AMDGPUAA>();
487 }
488 
489 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
490                                                        bool DebugPassManager) {
491   PB.registerPipelineParsingCallback(
492       [this](StringRef PassName, ModulePassManager &PM,
493              ArrayRef<PassBuilder::PipelineElement>) {
494         if (PassName == "amdgpu-propagate-attributes-late") {
495           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
496           return true;
497         }
498         if (PassName == "amdgpu-unify-metadata") {
499           PM.addPass(AMDGPUUnifyMetadataPass());
500           return true;
501         }
502         if (PassName == "amdgpu-printf-runtime-binding") {
503           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
504           return true;
505         }
506         if (PassName == "amdgpu-always-inline") {
507           PM.addPass(AMDGPUAlwaysInlinePass());
508           return true;
509         }
510         if (PassName == "amdgpu-lower-module-lds") {
511           PM.addPass(AMDGPULowerModuleLDSPass());
512           return true;
513         }
514         return false;
515       });
516   PB.registerPipelineParsingCallback(
517       [this](StringRef PassName, FunctionPassManager &PM,
518              ArrayRef<PassBuilder::PipelineElement>) {
519         if (PassName == "amdgpu-simplifylib") {
520           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
521           return true;
522         }
523         if (PassName == "amdgpu-usenative") {
524           PM.addPass(AMDGPUUseNativeCallsPass());
525           return true;
526         }
527         if (PassName == "amdgpu-promote-alloca") {
528           PM.addPass(AMDGPUPromoteAllocaPass(*this));
529           return true;
530         }
531         if (PassName == "amdgpu-promote-alloca-to-vector") {
532           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
533           return true;
534         }
535         if (PassName == "amdgpu-lower-kernel-attributes") {
536           PM.addPass(AMDGPULowerKernelAttributesPass());
537           return true;
538         }
539         if (PassName == "amdgpu-propagate-attributes-early") {
540           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
541           return true;
542         }
543         return false;
544       });
545 
546   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
547     FAM.registerPass([&] { return AMDGPUAA(); });
548   });
549 
550   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
551     if (AAName == "amdgpu-aa") {
552       AAM.registerFunctionAnalysis<AMDGPUAA>();
553       return true;
554     }
555     return false;
556   });
557 
558   PB.registerPipelineStartEPCallback([this, DebugPassManager](
559                                          ModulePassManager &PM,
560                                          PassBuilder::OptimizationLevel Level) {
561     FunctionPassManager FPM(DebugPassManager);
562     FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
563     FPM.addPass(AMDGPUUseNativeCallsPass());
564     if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
565       FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
566     PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
567   });
568 
569   PB.registerPipelineEarlySimplificationEPCallback(
570       [this](ModulePassManager &PM, PassBuilder::OptimizationLevel Level) {
571         if (Level == PassBuilder::OptimizationLevel::O0)
572           return;
573 
574         PM.addPass(AMDGPUUnifyMetadataPass());
575         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
576 
577         if (InternalizeSymbols) {
578           PM.addPass(InternalizePass(mustPreserveGV));
579         }
580         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
581         if (InternalizeSymbols) {
582           PM.addPass(GlobalDCEPass());
583         }
584         if (EarlyInlineAll && !EnableFunctionCalls)
585           PM.addPass(AMDGPUAlwaysInlinePass());
586       });
587 
588   PB.registerCGSCCOptimizerLateEPCallback(
589       [this, DebugPassManager](CGSCCPassManager &PM,
590                                PassBuilder::OptimizationLevel Level) {
591         if (Level == PassBuilder::OptimizationLevel::O0)
592           return;
593 
594         FunctionPassManager FPM(DebugPassManager);
595 
596         // Add infer address spaces pass to the opt pipeline after inlining
597         // but before SROA to increase SROA opportunities.
598         FPM.addPass(InferAddressSpacesPass());
599 
600         // This should run after inlining to have any chance of doing
601         // anything, and before other cleanup optimizations.
602         FPM.addPass(AMDGPULowerKernelAttributesPass());
603 
604         if (Level != PassBuilder::OptimizationLevel::O0) {
605           // Promote alloca to vector before SROA and loop unroll. If we
606           // manage to eliminate allocas before unroll we may choose to unroll
607           // less.
608           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
609         }
610 
611         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
612       });
613 }
614 
615 //===----------------------------------------------------------------------===//
616 // R600 Target Machine (R600 -> Cayman)
617 //===----------------------------------------------------------------------===//
618 
619 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
620                                      StringRef CPU, StringRef FS,
621                                      TargetOptions Options,
622                                      Optional<Reloc::Model> RM,
623                                      Optional<CodeModel::Model> CM,
624                                      CodeGenOpt::Level OL, bool JIT)
625     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
626   setRequiresStructuredCFG(true);
627 
628   // Override the default since calls aren't supported for r600.
629   if (EnableFunctionCalls &&
630       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
631     EnableFunctionCalls = false;
632 }
633 
634 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
635   const Function &F) const {
636   StringRef GPU = getGPUName(F);
637   StringRef FS = getFeatureString(F);
638 
639   SmallString<128> SubtargetKey(GPU);
640   SubtargetKey.append(FS);
641 
642   auto &I = SubtargetMap[SubtargetKey];
643   if (!I) {
644     // This needs to be done before we create a new subtarget since any
645     // creation will depend on the TM and the code generation flags on the
646     // function that reside in TargetOptions.
647     resetTargetOptions(F);
648     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
649   }
650 
651   return I.get();
652 }
653 
654 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
655   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
656           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
657           AddrSpace == AMDGPUAS::REGION_ADDRESS)
658              ? -1
659              : 0;
660 }
661 
662 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
663                                               unsigned DestAS) const {
664   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
665          AMDGPU::isFlatGlobalAddrSpace(DestAS);
666 }
667 
668 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
669   const auto *LD = dyn_cast<LoadInst>(V);
670   if (!LD)
671     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
672 
673   // It must be a generic pointer loaded.
674   assert(V->getType()->isPointerTy() &&
675          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
676 
677   const auto *Ptr = LD->getPointerOperand();
678   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
679     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
680   // For a generic pointer loaded from the constant memory, it could be assumed
681   // as a global pointer since the constant memory is only populated on the
682   // host side. As implied by the offload programming model, only global
683   // pointers could be referenced on the host side.
684   return AMDGPUAS::GLOBAL_ADDRESS;
685 }
686 
687 TargetTransformInfo
688 R600TargetMachine::getTargetTransformInfo(const Function &F) {
689   return TargetTransformInfo(R600TTIImpl(this, F));
690 }
691 
692 //===----------------------------------------------------------------------===//
693 // GCN Target Machine (SI+)
694 //===----------------------------------------------------------------------===//
695 
696 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
697                                    StringRef CPU, StringRef FS,
698                                    TargetOptions Options,
699                                    Optional<Reloc::Model> RM,
700                                    Optional<CodeModel::Model> CM,
701                                    CodeGenOpt::Level OL, bool JIT)
702     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
703 
704 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
705   StringRef GPU = getGPUName(F);
706   StringRef FS = getFeatureString(F);
707 
708   SmallString<128> SubtargetKey(GPU);
709   SubtargetKey.append(FS);
710 
711   auto &I = SubtargetMap[SubtargetKey];
712   if (!I) {
713     // This needs to be done before we create a new subtarget since any
714     // creation will depend on the TM and the code generation flags on the
715     // function that reside in TargetOptions.
716     resetTargetOptions(F);
717     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
718   }
719 
720   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
721 
722   return I.get();
723 }
724 
725 TargetTransformInfo
726 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
727   return TargetTransformInfo(GCNTTIImpl(this, F));
728 }
729 
730 //===----------------------------------------------------------------------===//
731 // AMDGPU Pass Setup
732 //===----------------------------------------------------------------------===//
733 
734 namespace {
735 
736 class AMDGPUPassConfig : public TargetPassConfig {
737 public:
738   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
739     : TargetPassConfig(TM, PM) {
740     // Exceptions and StackMaps are not supported, so these passes will never do
741     // anything.
742     disablePass(&StackMapLivenessID);
743     disablePass(&FuncletLayoutID);
744   }
745 
746   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
747     return getTM<AMDGPUTargetMachine>();
748   }
749 
750   ScheduleDAGInstrs *
751   createMachineScheduler(MachineSchedContext *C) const override {
752     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
753     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
754     return DAG;
755   }
756 
757   void addEarlyCSEOrGVNPass();
758   void addStraightLineScalarOptimizationPasses();
759   void addIRPasses() override;
760   void addCodeGenPrepare() override;
761   bool addPreISel() override;
762   bool addInstSelector() override;
763   bool addGCPasses() override;
764 
765   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
766 };
767 
768 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
769   return getStandardCSEConfigForOpt(TM->getOptLevel());
770 }
771 
772 class R600PassConfig final : public AMDGPUPassConfig {
773 public:
774   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
775     : AMDGPUPassConfig(TM, PM) {}
776 
777   ScheduleDAGInstrs *createMachineScheduler(
778     MachineSchedContext *C) const override {
779     return createR600MachineScheduler(C);
780   }
781 
782   bool addPreISel() override;
783   bool addInstSelector() override;
784   void addPreRegAlloc() override;
785   void addPreSched2() override;
786   void addPreEmitPass() override;
787 };
788 
789 class GCNPassConfig final : public AMDGPUPassConfig {
790 public:
791   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
792     : AMDGPUPassConfig(TM, PM) {
793     // It is necessary to know the register usage of the entire call graph.  We
794     // allow calls without EnableAMDGPUFunctionCalls if they are marked
795     // noinline, so this is always required.
796     setRequiresCodeGenSCCOrder(true);
797   }
798 
799   GCNTargetMachine &getGCNTargetMachine() const {
800     return getTM<GCNTargetMachine>();
801   }
802 
803   ScheduleDAGInstrs *
804   createMachineScheduler(MachineSchedContext *C) const override;
805 
806   bool addPreISel() override;
807   void addMachineSSAOptimization() override;
808   bool addILPOpts() override;
809   bool addInstSelector() override;
810   bool addIRTranslator() override;
811   void addPreLegalizeMachineIR() override;
812   bool addLegalizeMachineIR() override;
813   void addPreRegBankSelect() override;
814   bool addRegBankSelect() override;
815   void addPreGlobalInstructionSelect() override;
816   bool addGlobalInstructionSelect() override;
817   void addFastRegAlloc() override;
818   void addOptimizedRegAlloc() override;
819   void addPreRegAlloc() override;
820   bool addPreRewrite() override;
821   void addPostRegAlloc() override;
822   void addPreSched2() override;
823   void addPreEmitPass() override;
824 };
825 
826 } // end anonymous namespace
827 
828 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
829   if (getOptLevel() == CodeGenOpt::Aggressive)
830     addPass(createGVNPass());
831   else
832     addPass(createEarlyCSEPass());
833 }
834 
835 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
836   addPass(createLICMPass());
837   addPass(createSeparateConstOffsetFromGEPPass());
838   addPass(createSpeculativeExecutionPass());
839   // ReassociateGEPs exposes more opportunites for SLSR. See
840   // the example in reassociate-geps-and-slsr.ll.
841   addPass(createStraightLineStrengthReducePass());
842   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
843   // EarlyCSE can reuse.
844   addEarlyCSEOrGVNPass();
845   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
846   addPass(createNaryReassociatePass());
847   // NaryReassociate on GEPs creates redundant common expressions, so run
848   // EarlyCSE after it.
849   addPass(createEarlyCSEPass());
850 }
851 
852 void AMDGPUPassConfig::addIRPasses() {
853   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
854 
855   // There is no reason to run these.
856   disablePass(&StackMapLivenessID);
857   disablePass(&FuncletLayoutID);
858   disablePass(&PatchableFunctionID);
859 
860   addPass(createAMDGPUPrintfRuntimeBinding());
861 
862   // This must occur before inlining, as the inliner will not look through
863   // bitcast calls.
864   addPass(createAMDGPUFixFunctionBitcastsPass());
865 
866   // A call to propagate attributes pass in the backend in case opt was not run.
867   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
868 
869   addPass(createAtomicExpandPass());
870 
871 
872   addPass(createAMDGPULowerIntrinsicsPass());
873 
874   // Function calls are not supported, so make sure we inline everything.
875   addPass(createAMDGPUAlwaysInlinePass());
876   addPass(createAlwaysInlinerLegacyPass());
877   // We need to add the barrier noop pass, otherwise adding the function
878   // inlining pass will cause all of the PassConfigs passes to be run
879   // one function at a time, which means if we have a nodule with two
880   // functions, then we will generate code for the first function
881   // without ever running any passes on the second.
882   addPass(createBarrierNoopPass());
883 
884   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
885   if (TM.getTargetTriple().getArch() == Triple::r600)
886     addPass(createR600OpenCLImageTypeLoweringPass());
887 
888   // Replace OpenCL enqueued block function pointers with global variables.
889   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
890 
891   // Can increase LDS used by kernel so runs before PromoteAlloca
892   if (EnableLowerModuleLDS)
893     addPass(createAMDGPULowerModuleLDSPass());
894 
895   if (TM.getOptLevel() > CodeGenOpt::None) {
896     addPass(createInferAddressSpacesPass());
897     addPass(createAMDGPUPromoteAlloca());
898 
899     if (EnableSROA)
900       addPass(createSROAPass());
901 
902     if (EnableScalarIRPasses)
903       addStraightLineScalarOptimizationPasses();
904 
905     if (EnableAMDGPUAliasAnalysis) {
906       addPass(createAMDGPUAAWrapperPass());
907       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
908                                              AAResults &AAR) {
909         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
910           AAR.addAAResult(WrapperPass->getResult());
911         }));
912     }
913   }
914 
915   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
916     // TODO: May want to move later or split into an early and late one.
917     addPass(createAMDGPUCodeGenPreparePass());
918   }
919 
920   TargetPassConfig::addIRPasses();
921 
922   // EarlyCSE is not always strong enough to clean up what LSR produces. For
923   // example, GVN can combine
924   //
925   //   %0 = add %a, %b
926   //   %1 = add %b, %a
927   //
928   // and
929   //
930   //   %0 = shl nsw %a, 2
931   //   %1 = shl %a, 2
932   //
933   // but EarlyCSE can do neither of them.
934   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
935     addEarlyCSEOrGVNPass();
936 }
937 
938 void AMDGPUPassConfig::addCodeGenPrepare() {
939   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
940     addPass(createAMDGPUAnnotateKernelFeaturesPass());
941 
942   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
943       EnableLowerKernelArguments)
944     addPass(createAMDGPULowerKernelArgumentsPass());
945 
946   addPass(&AMDGPUPerfHintAnalysisID);
947 
948   TargetPassConfig::addCodeGenPrepare();
949 
950   if (EnableLoadStoreVectorizer)
951     addPass(createLoadStoreVectorizerPass());
952 
953   // LowerSwitch pass may introduce unreachable blocks that can
954   // cause unexpected behavior for subsequent passes. Placing it
955   // here seems better that these blocks would get cleaned up by
956   // UnreachableBlockElim inserted next in the pass flow.
957   addPass(createLowerSwitchPass());
958 }
959 
960 bool AMDGPUPassConfig::addPreISel() {
961   addPass(createFlattenCFGPass());
962   return false;
963 }
964 
965 bool AMDGPUPassConfig::addInstSelector() {
966   // Defer the verifier until FinalizeISel.
967   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
968   return false;
969 }
970 
971 bool AMDGPUPassConfig::addGCPasses() {
972   // Do nothing. GC is not supported.
973   return false;
974 }
975 
976 //===----------------------------------------------------------------------===//
977 // R600 Pass Setup
978 //===----------------------------------------------------------------------===//
979 
980 bool R600PassConfig::addPreISel() {
981   AMDGPUPassConfig::addPreISel();
982 
983   if (EnableR600StructurizeCFG)
984     addPass(createStructurizeCFGPass());
985   return false;
986 }
987 
988 bool R600PassConfig::addInstSelector() {
989   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
990   return false;
991 }
992 
993 void R600PassConfig::addPreRegAlloc() {
994   addPass(createR600VectorRegMerger());
995 }
996 
997 void R600PassConfig::addPreSched2() {
998   addPass(createR600EmitClauseMarkers(), false);
999   if (EnableR600IfConvert)
1000     addPass(&IfConverterID, false);
1001   addPass(createR600ClauseMergePass(), false);
1002 }
1003 
1004 void R600PassConfig::addPreEmitPass() {
1005   addPass(createAMDGPUCFGStructurizerPass(), false);
1006   addPass(createR600ExpandSpecialInstrsPass(), false);
1007   addPass(&FinalizeMachineBundlesID, false);
1008   addPass(createR600Packetizer(), false);
1009   addPass(createR600ControlFlowFinalizer(), false);
1010 }
1011 
1012 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
1013   return new R600PassConfig(*this, PM);
1014 }
1015 
1016 //===----------------------------------------------------------------------===//
1017 // GCN Pass Setup
1018 //===----------------------------------------------------------------------===//
1019 
1020 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1021   MachineSchedContext *C) const {
1022   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1023   if (ST.enableSIScheduler())
1024     return createSIMachineScheduler(C);
1025   return createGCNMaxOccupancyMachineScheduler(C);
1026 }
1027 
1028 bool GCNPassConfig::addPreISel() {
1029   AMDGPUPassConfig::addPreISel();
1030 
1031   addPass(createAMDGPULateCodeGenPreparePass());
1032   if (EnableAtomicOptimizations) {
1033     addPass(createAMDGPUAtomicOptimizerPass());
1034   }
1035 
1036   // FIXME: We need to run a pass to propagate the attributes when calls are
1037   // supported.
1038 
1039   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1040   // regions formed by them.
1041   addPass(&AMDGPUUnifyDivergentExitNodesID);
1042   if (!LateCFGStructurize) {
1043     if (EnableStructurizerWorkarounds) {
1044       addPass(createFixIrreduciblePass());
1045       addPass(createUnifyLoopExitsPass());
1046     }
1047     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1048   }
1049   addPass(createSinkingPass());
1050   addPass(createAMDGPUAnnotateUniformValues());
1051   if (!LateCFGStructurize) {
1052     addPass(createSIAnnotateControlFlowPass());
1053   }
1054   addPass(createLCSSAPass());
1055 
1056   return false;
1057 }
1058 
1059 void GCNPassConfig::addMachineSSAOptimization() {
1060   TargetPassConfig::addMachineSSAOptimization();
1061 
1062   // We want to fold operands after PeepholeOptimizer has run (or as part of
1063   // it), because it will eliminate extra copies making it easier to fold the
1064   // real source operand. We want to eliminate dead instructions after, so that
1065   // we see fewer uses of the copies. We then need to clean up the dead
1066   // instructions leftover after the operands are folded as well.
1067   //
1068   // XXX - Can we get away without running DeadMachineInstructionElim again?
1069   addPass(&SIFoldOperandsID);
1070   if (EnableDPPCombine)
1071     addPass(&GCNDPPCombineID);
1072   addPass(&DeadMachineInstructionElimID);
1073   addPass(&SILoadStoreOptimizerID);
1074   if (EnableSDWAPeephole) {
1075     addPass(&SIPeepholeSDWAID);
1076     addPass(&EarlyMachineLICMID);
1077     addPass(&MachineCSEID);
1078     addPass(&SIFoldOperandsID);
1079     addPass(&DeadMachineInstructionElimID);
1080   }
1081   addPass(createSIShrinkInstructionsPass());
1082 }
1083 
1084 bool GCNPassConfig::addILPOpts() {
1085   if (EnableEarlyIfConversion)
1086     addPass(&EarlyIfConverterID);
1087 
1088   TargetPassConfig::addILPOpts();
1089   return false;
1090 }
1091 
1092 bool GCNPassConfig::addInstSelector() {
1093   AMDGPUPassConfig::addInstSelector();
1094   addPass(&SIFixSGPRCopiesID);
1095   addPass(createSILowerI1CopiesPass());
1096   return false;
1097 }
1098 
1099 bool GCNPassConfig::addIRTranslator() {
1100   addPass(new IRTranslator(getOptLevel()));
1101   return false;
1102 }
1103 
1104 void GCNPassConfig::addPreLegalizeMachineIR() {
1105   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1106   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1107   addPass(new Localizer());
1108 }
1109 
1110 bool GCNPassConfig::addLegalizeMachineIR() {
1111   addPass(new Legalizer());
1112   return false;
1113 }
1114 
1115 void GCNPassConfig::addPreRegBankSelect() {
1116   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1117   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1118 }
1119 
1120 bool GCNPassConfig::addRegBankSelect() {
1121   addPass(new RegBankSelect());
1122   return false;
1123 }
1124 
1125 void GCNPassConfig::addPreGlobalInstructionSelect() {
1126   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1127   addPass(createAMDGPURegBankCombiner(IsOptNone));
1128 }
1129 
1130 bool GCNPassConfig::addGlobalInstructionSelect() {
1131   addPass(new InstructionSelect(getOptLevel()));
1132   return false;
1133 }
1134 
1135 void GCNPassConfig::addPreRegAlloc() {
1136   if (LateCFGStructurize) {
1137     addPass(createAMDGPUMachineCFGStructurizerPass());
1138   }
1139 }
1140 
1141 void GCNPassConfig::addFastRegAlloc() {
1142   // FIXME: We have to disable the verifier here because of PHIElimination +
1143   // TwoAddressInstructions disabling it.
1144 
1145   // This must be run immediately after phi elimination and before
1146   // TwoAddressInstructions, otherwise the processing of the tied operand of
1147   // SI_ELSE will introduce a copy of the tied operand source after the else.
1148   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1149 
1150   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1151   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1152 
1153   TargetPassConfig::addFastRegAlloc();
1154 }
1155 
1156 void GCNPassConfig::addOptimizedRegAlloc() {
1157   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1158   // instructions that cause scheduling barriers.
1159   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1160   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1161 
1162   if (OptExecMaskPreRA)
1163     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1164   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1165 
1166   // This must be run immediately after phi elimination and before
1167   // TwoAddressInstructions, otherwise the processing of the tied operand of
1168   // SI_ELSE will introduce a copy of the tied operand source after the else.
1169   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1170 
1171   if (EnableDCEInRA)
1172     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1173 
1174   TargetPassConfig::addOptimizedRegAlloc();
1175 }
1176 
1177 bool GCNPassConfig::addPreRewrite() {
1178   if (EnableRegReassign) {
1179     addPass(&GCNNSAReassignID);
1180     addPass(createGCNRegBankReassignPass(AMDGPU::RM_BOTH));
1181   }
1182   return true;
1183 }
1184 
1185 void GCNPassConfig::addPostRegAlloc() {
1186   addPass(&SIFixVGPRCopiesID);
1187   if (getOptLevel() > CodeGenOpt::None)
1188     addPass(&SIOptimizeExecMaskingID);
1189   TargetPassConfig::addPostRegAlloc();
1190 
1191   // Equivalent of PEI for SGPRs.
1192   addPass(&SILowerSGPRSpillsID);
1193 }
1194 
1195 void GCNPassConfig::addPreSched2() {
1196   addPass(&SIPostRABundlerID);
1197 }
1198 
1199 void GCNPassConfig::addPreEmitPass() {
1200   addPass(createSIMemoryLegalizerPass());
1201   addPass(createSIInsertWaitcntsPass());
1202   addPass(createSIShrinkInstructionsPass());
1203   addPass(createSIModeRegisterPass());
1204 
1205   if (getOptLevel() > CodeGenOpt::None)
1206     addPass(&SIInsertHardClausesID);
1207 
1208   addPass(&SILateBranchLoweringPassID);
1209   if (getOptLevel() > CodeGenOpt::None)
1210     addPass(&SIPreEmitPeepholeID);
1211   // The hazard recognizer that runs as part of the post-ra scheduler does not
1212   // guarantee to be able handle all hazards correctly. This is because if there
1213   // are multiple scheduling regions in a basic block, the regions are scheduled
1214   // bottom up, so when we begin to schedule a region we don't know what
1215   // instructions were emitted directly before it.
1216   //
1217   // Here we add a stand-alone hazard recognizer pass which can handle all
1218   // cases.
1219   addPass(&PostRAHazardRecognizerID);
1220   addPass(&BranchRelaxationPassID);
1221 }
1222 
1223 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1224   return new GCNPassConfig(*this, PM);
1225 }
1226 
1227 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1228   return new yaml::SIMachineFunctionInfo();
1229 }
1230 
1231 yaml::MachineFunctionInfo *
1232 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1233   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1234   return new yaml::SIMachineFunctionInfo(*MFI,
1235                                          *MF.getSubtarget().getRegisterInfo());
1236 }
1237 
1238 bool GCNTargetMachine::parseMachineFunctionInfo(
1239     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1240     SMDiagnostic &Error, SMRange &SourceRange) const {
1241   const yaml::SIMachineFunctionInfo &YamlMFI =
1242       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1243   MachineFunction &MF = PFS.MF;
1244   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1245 
1246   MFI->initializeBaseYamlFields(YamlMFI);
1247 
1248   if (MFI->Occupancy == 0) {
1249     // Fixup the subtarget dependent default value.
1250     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1251     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1252   }
1253 
1254   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1255     Register TempReg;
1256     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1257       SourceRange = RegName.SourceRange;
1258       return true;
1259     }
1260     RegVal = TempReg;
1261 
1262     return false;
1263   };
1264 
1265   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1266     // Create a diagnostic for a the register string literal.
1267     const MemoryBuffer &Buffer =
1268         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1269     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1270                          RegName.Value.size(), SourceMgr::DK_Error,
1271                          "incorrect register class for field", RegName.Value,
1272                          None, None);
1273     SourceRange = RegName.SourceRange;
1274     return true;
1275   };
1276 
1277   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1278       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1279       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1280     return true;
1281 
1282   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1283       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1284     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1285   }
1286 
1287   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1288       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1289     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1290   }
1291 
1292   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1293       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1294     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1295   }
1296 
1297   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1298                                    const TargetRegisterClass &RC,
1299                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1300                                    unsigned SystemSGPRs) {
1301     // Skip parsing if it's not present.
1302     if (!A)
1303       return false;
1304 
1305     if (A->IsRegister) {
1306       Register Reg;
1307       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1308         SourceRange = A->RegisterName.SourceRange;
1309         return true;
1310       }
1311       if (!RC.contains(Reg))
1312         return diagnoseRegisterClass(A->RegisterName);
1313       Arg = ArgDescriptor::createRegister(Reg);
1314     } else
1315       Arg = ArgDescriptor::createStack(A->StackOffset);
1316     // Check and apply the optional mask.
1317     if (A->Mask)
1318       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1319 
1320     MFI->NumUserSGPRs += UserSGPRs;
1321     MFI->NumSystemSGPRs += SystemSGPRs;
1322     return false;
1323   };
1324 
1325   if (YamlMFI.ArgInfo &&
1326       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1327                              AMDGPU::SGPR_128RegClass,
1328                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1329        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1330                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1331                              2, 0) ||
1332        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1333                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1334        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1335                              AMDGPU::SReg_64RegClass,
1336                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1337        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1338                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1339                              2, 0) ||
1340        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1341                              AMDGPU::SReg_64RegClass,
1342                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1343        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1344                              AMDGPU::SGPR_32RegClass,
1345                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1346        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1347                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1348                              0, 1) ||
1349        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1350                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1351                              0, 1) ||
1352        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1353                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1354                              0, 1) ||
1355        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1356                              AMDGPU::SGPR_32RegClass,
1357                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1358        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1359                              AMDGPU::SGPR_32RegClass,
1360                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1361        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1362                              AMDGPU::SReg_64RegClass,
1363                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1364        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1365                              AMDGPU::SReg_64RegClass,
1366                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1367        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1368                              AMDGPU::VGPR_32RegClass,
1369                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1370        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1371                              AMDGPU::VGPR_32RegClass,
1372                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1373        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1374                              AMDGPU::VGPR_32RegClass,
1375                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1376     return true;
1377 
1378   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1379   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1380   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1381   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1382   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1383   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1384 
1385   return false;
1386 }
1387