1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUExportClustering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
28 #include "R600MachineScheduler.h"
29 #include "SIMachineFunctionInfo.h"
30 #include "SIMachineScheduler.h"
31 #include "TargetInfo/AMDGPUTargetInfo.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
35 #include "llvm/CodeGen/GlobalISel/Localizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MIRParser/MIParser.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/LegacyPassManager.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/Pass.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Transforms/IPO.h"
50 #include "llvm/Transforms/IPO/AlwaysInliner.h"
51 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
52 #include "llvm/Transforms/Scalar.h"
53 #include "llvm/Transforms/Scalar/GVN.h"
54 #include "llvm/Transforms/Utils.h"
55 #include "llvm/Transforms/Vectorize.h"
56 #include <memory>
57 
58 using namespace llvm;
59 
60 static cl::opt<bool> EnableR600StructurizeCFG(
61   "r600-ir-structurize",
62   cl::desc("Use StructurizeCFG IR pass"),
63   cl::init(true));
64 
65 static cl::opt<bool> EnableSROA(
66   "amdgpu-sroa",
67   cl::desc("Run SROA after promote alloca pass"),
68   cl::ReallyHidden,
69   cl::init(true));
70 
71 static cl::opt<bool>
72 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
73                         cl::desc("Run early if-conversion"),
74                         cl::init(false));
75 
76 static cl::opt<bool>
77 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
78             cl::desc("Run pre-RA exec mask optimizations"),
79             cl::init(true));
80 
81 static cl::opt<bool> EnableR600IfConvert(
82   "r600-if-convert",
83   cl::desc("Use if conversion pass"),
84   cl::ReallyHidden,
85   cl::init(true));
86 
87 // Option to disable vectorizer for tests.
88 static cl::opt<bool> EnableLoadStoreVectorizer(
89   "amdgpu-load-store-vectorizer",
90   cl::desc("Enable load store vectorizer"),
91   cl::init(true),
92   cl::Hidden);
93 
94 // Option to control global loads scalarization
95 static cl::opt<bool> ScalarizeGlobal(
96   "amdgpu-scalarize-global-loads",
97   cl::desc("Enable global load scalarization"),
98   cl::init(true),
99   cl::Hidden);
100 
101 // Option to run internalize pass.
102 static cl::opt<bool> InternalizeSymbols(
103   "amdgpu-internalize-symbols",
104   cl::desc("Enable elimination of non-kernel functions and unused globals"),
105   cl::init(false),
106   cl::Hidden);
107 
108 // Option to inline all early.
109 static cl::opt<bool> EarlyInlineAll(
110   "amdgpu-early-inline-all",
111   cl::desc("Inline all functions early"),
112   cl::init(false),
113   cl::Hidden);
114 
115 static cl::opt<bool> EnableSDWAPeephole(
116   "amdgpu-sdwa-peephole",
117   cl::desc("Enable SDWA peepholer"),
118   cl::init(true));
119 
120 static cl::opt<bool> EnableDPPCombine(
121   "amdgpu-dpp-combine",
122   cl::desc("Enable DPP combiner"),
123   cl::init(true));
124 
125 // Enable address space based alias analysis
126 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
127   cl::desc("Enable AMDGPU Alias Analysis"),
128   cl::init(true));
129 
130 // Option to run late CFG structurizer
131 static cl::opt<bool, true> LateCFGStructurize(
132   "amdgpu-late-structurize",
133   cl::desc("Enable late CFG structurization"),
134   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
135   cl::Hidden);
136 
137 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
138   "amdgpu-function-calls",
139   cl::desc("Enable AMDGPU function call support"),
140   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
141   cl::init(true),
142   cl::Hidden);
143 
144 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
145   "amdgpu-fixed-function-abi",
146   cl::desc("Enable all implicit function arguments"),
147   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
148   cl::init(false),
149   cl::Hidden);
150 
151 // Enable lib calls simplifications
152 static cl::opt<bool> EnableLibCallSimplify(
153   "amdgpu-simplify-libcall",
154   cl::desc("Enable amdgpu library simplifications"),
155   cl::init(true),
156   cl::Hidden);
157 
158 static cl::opt<bool> EnableLowerKernelArguments(
159   "amdgpu-ir-lower-kernel-arguments",
160   cl::desc("Lower kernel argument loads in IR pass"),
161   cl::init(true),
162   cl::Hidden);
163 
164 static cl::opt<bool> EnableRegReassign(
165   "amdgpu-reassign-regs",
166   cl::desc("Enable register reassign optimizations on gfx10+"),
167   cl::init(true),
168   cl::Hidden);
169 
170 // Enable atomic optimization
171 static cl::opt<bool> EnableAtomicOptimizations(
172   "amdgpu-atomic-optimizations",
173   cl::desc("Enable atomic optimizations"),
174   cl::init(false),
175   cl::Hidden);
176 
177 // Enable Mode register optimization
178 static cl::opt<bool> EnableSIModeRegisterPass(
179   "amdgpu-mode-register",
180   cl::desc("Enable mode register pass"),
181   cl::init(true),
182   cl::Hidden);
183 
184 // Option is used in lit tests to prevent deadcoding of patterns inspected.
185 static cl::opt<bool>
186 EnableDCEInRA("amdgpu-dce-in-ra",
187     cl::init(true), cl::Hidden,
188     cl::desc("Enable machine DCE inside regalloc"));
189 
190 static cl::opt<bool> EnableScalarIRPasses(
191   "amdgpu-scalar-ir-passes",
192   cl::desc("Enable scalar IR passes"),
193   cl::init(true),
194   cl::Hidden);
195 
196 static cl::opt<bool> EnableStructurizerWorkarounds(
197     "amdgpu-enable-structurizer-workarounds",
198     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
199     cl::Hidden);
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFixupVectorISelPass(*PR);
220   initializeSIFoldOperandsPass(*PR);
221   initializeSIPeepholeSDWAPass(*PR);
222   initializeSIShrinkInstructionsPass(*PR);
223   initializeSIOptimizeExecMaskingPreRAPass(*PR);
224   initializeSILoadStoreOptimizerPass(*PR);
225   initializeAMDGPUFixFunctionBitcastsPass(*PR);
226   initializeAMDGPUAlwaysInlinePass(*PR);
227   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
228   initializeAMDGPUAnnotateUniformValuesPass(*PR);
229   initializeAMDGPUArgumentUsageInfoPass(*PR);
230   initializeAMDGPUAtomicOptimizerPass(*PR);
231   initializeAMDGPULowerKernelArgumentsPass(*PR);
232   initializeAMDGPULowerKernelAttributesPass(*PR);
233   initializeAMDGPULowerIntrinsicsPass(*PR);
234   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
235   initializeAMDGPUPostLegalizerCombinerPass(*PR);
236   initializeAMDGPUPreLegalizerCombinerPass(*PR);
237   initializeAMDGPUPromoteAllocaPass(*PR);
238   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
239   initializeAMDGPUCodeGenPreparePass(*PR);
240   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
241   initializeAMDGPUPropagateAttributesLatePass(*PR);
242   initializeAMDGPURewriteOutArgumentsPass(*PR);
243   initializeAMDGPUUnifyMetadataPass(*PR);
244   initializeSIAnnotateControlFlowPass(*PR);
245   initializeSIInsertHardClausesPass(*PR);
246   initializeSIInsertWaitcntsPass(*PR);
247   initializeSIModeRegisterPass(*PR);
248   initializeSIWholeQuadModePass(*PR);
249   initializeSILowerControlFlowPass(*PR);
250   initializeSIRemoveShortExecBranchesPass(*PR);
251   initializeSIPreEmitPeepholePass(*PR);
252   initializeSIInsertSkipsPass(*PR);
253   initializeSIMemoryLegalizerPass(*PR);
254   initializeSIOptimizeExecMaskingPass(*PR);
255   initializeSIPreAllocateWWMRegsPass(*PR);
256   initializeSIFormMemoryClausesPass(*PR);
257   initializeSIPostRABundlerPass(*PR);
258   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
259   initializeAMDGPUAAWrapperPassPass(*PR);
260   initializeAMDGPUExternalAAWrapperPass(*PR);
261   initializeAMDGPUUseNativeCallsPass(*PR);
262   initializeAMDGPUSimplifyLibCallsPass(*PR);
263   initializeAMDGPUInlinerPass(*PR);
264   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
265   initializeGCNRegBankReassignPass(*PR);
266   initializeGCNNSAReassignPass(*PR);
267   initializeSIAddIMGInitPass(*PR);
268 }
269 
270 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
271   return std::make_unique<AMDGPUTargetObjectFile>();
272 }
273 
274 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
275   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
276 }
277 
278 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
279   return new SIScheduleDAGMI(C);
280 }
281 
282 static ScheduleDAGInstrs *
283 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
284   ScheduleDAGMILive *DAG =
285     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
286   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
287   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
288   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
289   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
290   return DAG;
291 }
292 
293 static ScheduleDAGInstrs *
294 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
295   auto DAG = new GCNIterativeScheduler(C,
296     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
297   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
298   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
299   return DAG;
300 }
301 
302 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
303   return new GCNIterativeScheduler(C,
304     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
305 }
306 
307 static ScheduleDAGInstrs *
308 createIterativeILPMachineScheduler(MachineSchedContext *C) {
309   auto DAG = new GCNIterativeScheduler(C,
310     GCNIterativeScheduler::SCHEDULE_ILP);
311   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
312   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
313   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
314   return DAG;
315 }
316 
317 static MachineSchedRegistry
318 R600SchedRegistry("r600", "Run R600's custom scheduler",
319                    createR600MachineScheduler);
320 
321 static MachineSchedRegistry
322 SISchedRegistry("si", "Run SI's custom scheduler",
323                 createSIMachineScheduler);
324 
325 static MachineSchedRegistry
326 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
327                              "Run GCN scheduler to maximize occupancy",
328                              createGCNMaxOccupancyMachineScheduler);
329 
330 static MachineSchedRegistry
331 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
332   "Run GCN scheduler to maximize occupancy (experimental)",
333   createIterativeGCNMaxOccupancyMachineScheduler);
334 
335 static MachineSchedRegistry
336 GCNMinRegSchedRegistry("gcn-minreg",
337   "Run GCN iterative scheduler for minimal register usage (experimental)",
338   createMinRegScheduler);
339 
340 static MachineSchedRegistry
341 GCNILPSchedRegistry("gcn-ilp",
342   "Run GCN iterative scheduler for ILP scheduling (experimental)",
343   createIterativeILPMachineScheduler);
344 
345 static StringRef computeDataLayout(const Triple &TT) {
346   if (TT.getArch() == Triple::r600) {
347     // 32-bit pointers.
348       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
349              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
350   }
351 
352   // 32-bit private, local, and region pointers. 64-bit global, constant and
353   // flat, non-integral buffer fat pointers.
354     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
355          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
356          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
357          "-ni:7";
358 }
359 
360 LLVM_READNONE
361 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
362   if (!GPU.empty())
363     return GPU;
364 
365   // Need to default to a target with flat support for HSA.
366   if (TT.getArch() == Triple::amdgcn)
367     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
368 
369   return "r600";
370 }
371 
372 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
373   // The AMDGPU toolchain only supports generating shared objects, so we
374   // must always use PIC.
375   return Reloc::PIC_;
376 }
377 
378 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
379                                          StringRef CPU, StringRef FS,
380                                          TargetOptions Options,
381                                          Optional<Reloc::Model> RM,
382                                          Optional<CodeModel::Model> CM,
383                                          CodeGenOpt::Level OptLevel)
384     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
385                         FS, Options, getEffectiveRelocModel(RM),
386                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
387       TLOF(createTLOF(getTargetTriple())) {
388   initAsmInfo();
389   if (TT.getArch() == Triple::amdgcn) {
390     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
391       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
392     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
393       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
394   }
395 }
396 
397 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
398 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
399 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
400 
401 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
402 
403 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
404   Attribute GPUAttr = F.getFnAttribute("target-cpu");
405   return GPUAttr.hasAttribute(Attribute::None) ?
406     getTargetCPU() : GPUAttr.getValueAsString();
407 }
408 
409 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
410   Attribute FSAttr = F.getFnAttribute("target-features");
411 
412   return FSAttr.hasAttribute(Attribute::None) ?
413     getTargetFeatureString() :
414     FSAttr.getValueAsString();
415 }
416 
417 /// Predicate for Internalize pass.
418 static bool mustPreserveGV(const GlobalValue &GV) {
419   if (const Function *F = dyn_cast<Function>(&GV))
420     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
421 
422   return !GV.use_empty();
423 }
424 
425 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
426   Builder.DivergentTarget = true;
427 
428   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
429   bool Internalize = InternalizeSymbols;
430   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
431   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
432   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
433 
434   if (EnableFunctionCalls) {
435     delete Builder.Inliner;
436     Builder.Inliner = createAMDGPUFunctionInliningPass();
437   }
438 
439   Builder.addExtension(
440     PassManagerBuilder::EP_ModuleOptimizerEarly,
441     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
442                                                legacy::PassManagerBase &PM) {
443       if (AMDGPUAA) {
444         PM.add(createAMDGPUAAWrapperPass());
445         PM.add(createAMDGPUExternalAAWrapperPass());
446       }
447       PM.add(createAMDGPUUnifyMetadataPass());
448       PM.add(createAMDGPUPrintfRuntimeBinding());
449       if (Internalize)
450         PM.add(createInternalizePass(mustPreserveGV));
451       PM.add(createAMDGPUPropagateAttributesLatePass(this));
452       if (Internalize)
453         PM.add(createGlobalDCEPass());
454       if (EarlyInline)
455         PM.add(createAMDGPUAlwaysInlinePass(false));
456   });
457 
458   Builder.addExtension(
459     PassManagerBuilder::EP_EarlyAsPossible,
460     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
461                                       legacy::PassManagerBase &PM) {
462       if (AMDGPUAA) {
463         PM.add(createAMDGPUAAWrapperPass());
464         PM.add(createAMDGPUExternalAAWrapperPass());
465       }
466       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
467       PM.add(llvm::createAMDGPUUseNativeCallsPass());
468       if (LibCallSimplify)
469         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
470   });
471 
472   Builder.addExtension(
473     PassManagerBuilder::EP_CGSCCOptimizerLate,
474     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
475       // Add infer address spaces pass to the opt pipeline after inlining
476       // but before SROA to increase SROA opportunities.
477       PM.add(createInferAddressSpacesPass());
478 
479       // This should run after inlining to have any chance of doing anything,
480       // and before other cleanup optimizations.
481       PM.add(createAMDGPULowerKernelAttributesPass());
482 
483       // Promote alloca to vector before SROA and loop unroll. If we manage
484       // to eliminate allocas before unroll we may choose to unroll less.
485       if (EnableOpt)
486         PM.add(createAMDGPUPromoteAllocaToVector());
487   });
488 }
489 
490 //===----------------------------------------------------------------------===//
491 // R600 Target Machine (R600 -> Cayman)
492 //===----------------------------------------------------------------------===//
493 
494 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
495                                      StringRef CPU, StringRef FS,
496                                      TargetOptions Options,
497                                      Optional<Reloc::Model> RM,
498                                      Optional<CodeModel::Model> CM,
499                                      CodeGenOpt::Level OL, bool JIT)
500     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
501   setRequiresStructuredCFG(true);
502 
503   // Override the default since calls aren't supported for r600.
504   if (EnableFunctionCalls &&
505       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
506     EnableFunctionCalls = false;
507 }
508 
509 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
510   const Function &F) const {
511   StringRef GPU = getGPUName(F);
512   StringRef FS = getFeatureString(F);
513 
514   SmallString<128> SubtargetKey(GPU);
515   SubtargetKey.append(FS);
516 
517   auto &I = SubtargetMap[SubtargetKey];
518   if (!I) {
519     // This needs to be done before we create a new subtarget since any
520     // creation will depend on the TM and the code generation flags on the
521     // function that reside in TargetOptions.
522     resetTargetOptions(F);
523     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
524   }
525 
526   return I.get();
527 }
528 
529 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
530                                               unsigned DestAS) const {
531   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
532          AMDGPU::isFlatGlobalAddrSpace(DestAS);
533 }
534 
535 TargetTransformInfo
536 R600TargetMachine::getTargetTransformInfo(const Function &F) {
537   return TargetTransformInfo(R600TTIImpl(this, F));
538 }
539 
540 //===----------------------------------------------------------------------===//
541 // GCN Target Machine (SI+)
542 //===----------------------------------------------------------------------===//
543 
544 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
545                                    StringRef CPU, StringRef FS,
546                                    TargetOptions Options,
547                                    Optional<Reloc::Model> RM,
548                                    Optional<CodeModel::Model> CM,
549                                    CodeGenOpt::Level OL, bool JIT)
550     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
551 
552 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
553   StringRef GPU = getGPUName(F);
554   StringRef FS = getFeatureString(F);
555 
556   SmallString<128> SubtargetKey(GPU);
557   SubtargetKey.append(FS);
558 
559   auto &I = SubtargetMap[SubtargetKey];
560   if (!I) {
561     // This needs to be done before we create a new subtarget since any
562     // creation will depend on the TM and the code generation flags on the
563     // function that reside in TargetOptions.
564     resetTargetOptions(F);
565     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
566   }
567 
568   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
569 
570   return I.get();
571 }
572 
573 TargetTransformInfo
574 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
575   return TargetTransformInfo(GCNTTIImpl(this, F));
576 }
577 
578 //===----------------------------------------------------------------------===//
579 // AMDGPU Pass Setup
580 //===----------------------------------------------------------------------===//
581 
582 namespace {
583 
584 class AMDGPUPassConfig : public TargetPassConfig {
585 public:
586   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
587     : TargetPassConfig(TM, PM) {
588     // Exceptions and StackMaps are not supported, so these passes will never do
589     // anything.
590     disablePass(&StackMapLivenessID);
591     disablePass(&FuncletLayoutID);
592   }
593 
594   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
595     return getTM<AMDGPUTargetMachine>();
596   }
597 
598   ScheduleDAGInstrs *
599   createMachineScheduler(MachineSchedContext *C) const override {
600     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
601     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
602     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
603     return DAG;
604   }
605 
606   void addEarlyCSEOrGVNPass();
607   void addStraightLineScalarOptimizationPasses();
608   void addIRPasses() override;
609   void addCodeGenPrepare() override;
610   bool addPreISel() override;
611   bool addInstSelector() override;
612   bool addGCPasses() override;
613 
614   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
615 };
616 
617 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
618   return getStandardCSEConfigForOpt(TM->getOptLevel());
619 }
620 
621 class R600PassConfig final : public AMDGPUPassConfig {
622 public:
623   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
624     : AMDGPUPassConfig(TM, PM) {}
625 
626   ScheduleDAGInstrs *createMachineScheduler(
627     MachineSchedContext *C) const override {
628     return createR600MachineScheduler(C);
629   }
630 
631   bool addPreISel() override;
632   bool addInstSelector() override;
633   void addPreRegAlloc() override;
634   void addPreSched2() override;
635   void addPreEmitPass() override;
636 };
637 
638 class GCNPassConfig final : public AMDGPUPassConfig {
639 public:
640   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
641     : AMDGPUPassConfig(TM, PM) {
642     // It is necessary to know the register usage of the entire call graph.  We
643     // allow calls without EnableAMDGPUFunctionCalls if they are marked
644     // noinline, so this is always required.
645     setRequiresCodeGenSCCOrder(true);
646   }
647 
648   GCNTargetMachine &getGCNTargetMachine() const {
649     return getTM<GCNTargetMachine>();
650   }
651 
652   ScheduleDAGInstrs *
653   createMachineScheduler(MachineSchedContext *C) const override;
654 
655   bool addPreISel() override;
656   void addMachineSSAOptimization() override;
657   bool addILPOpts() override;
658   bool addInstSelector() override;
659   bool addIRTranslator() override;
660   void addPreLegalizeMachineIR() override;
661   bool addLegalizeMachineIR() override;
662   void addPreRegBankSelect() override;
663   bool addRegBankSelect() override;
664   bool addGlobalInstructionSelect() override;
665   void addFastRegAlloc() override;
666   void addOptimizedRegAlloc() override;
667   void addPreRegAlloc() override;
668   bool addPreRewrite() override;
669   void addPostRegAlloc() override;
670   void addPreSched2() override;
671   void addPreEmitPass() override;
672 };
673 
674 } // end anonymous namespace
675 
676 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
677   if (getOptLevel() == CodeGenOpt::Aggressive)
678     addPass(createGVNPass());
679   else
680     addPass(createEarlyCSEPass());
681 }
682 
683 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
684   addPass(createLICMPass());
685   addPass(createSeparateConstOffsetFromGEPPass());
686   addPass(createSpeculativeExecutionPass());
687   // ReassociateGEPs exposes more opportunites for SLSR. See
688   // the example in reassociate-geps-and-slsr.ll.
689   addPass(createStraightLineStrengthReducePass());
690   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
691   // EarlyCSE can reuse.
692   addEarlyCSEOrGVNPass();
693   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
694   addPass(createNaryReassociatePass());
695   // NaryReassociate on GEPs creates redundant common expressions, so run
696   // EarlyCSE after it.
697   addPass(createEarlyCSEPass());
698 }
699 
700 void AMDGPUPassConfig::addIRPasses() {
701   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
702 
703   // There is no reason to run these.
704   disablePass(&StackMapLivenessID);
705   disablePass(&FuncletLayoutID);
706   disablePass(&PatchableFunctionID);
707 
708   addPass(createAMDGPUPrintfRuntimeBinding());
709 
710   // This must occur before inlining, as the inliner will not look through
711   // bitcast calls.
712   addPass(createAMDGPUFixFunctionBitcastsPass());
713 
714   // A call to propagate attributes pass in the backend in case opt was not run.
715   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
716 
717   addPass(createAtomicExpandPass());
718 
719 
720   addPass(createAMDGPULowerIntrinsicsPass());
721 
722   // Function calls are not supported, so make sure we inline everything.
723   addPass(createAMDGPUAlwaysInlinePass());
724   addPass(createAlwaysInlinerLegacyPass());
725   // We need to add the barrier noop pass, otherwise adding the function
726   // inlining pass will cause all of the PassConfigs passes to be run
727   // one function at a time, which means if we have a nodule with two
728   // functions, then we will generate code for the first function
729   // without ever running any passes on the second.
730   addPass(createBarrierNoopPass());
731 
732   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
733   if (TM.getTargetTriple().getArch() == Triple::r600)
734     addPass(createR600OpenCLImageTypeLoweringPass());
735 
736   // Replace OpenCL enqueued block function pointers with global variables.
737   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
738 
739   if (TM.getOptLevel() > CodeGenOpt::None) {
740     addPass(createInferAddressSpacesPass());
741     addPass(createAMDGPUPromoteAlloca());
742 
743     if (EnableSROA)
744       addPass(createSROAPass());
745 
746     if (EnableScalarIRPasses)
747       addStraightLineScalarOptimizationPasses();
748 
749     if (EnableAMDGPUAliasAnalysis) {
750       addPass(createAMDGPUAAWrapperPass());
751       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
752                                              AAResults &AAR) {
753         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
754           AAR.addAAResult(WrapperPass->getResult());
755         }));
756     }
757   }
758 
759   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
760     // TODO: May want to move later or split into an early and late one.
761     addPass(createAMDGPUCodeGenPreparePass());
762   }
763 
764   TargetPassConfig::addIRPasses();
765 
766   // EarlyCSE is not always strong enough to clean up what LSR produces. For
767   // example, GVN can combine
768   //
769   //   %0 = add %a, %b
770   //   %1 = add %b, %a
771   //
772   // and
773   //
774   //   %0 = shl nsw %a, 2
775   //   %1 = shl %a, 2
776   //
777   // but EarlyCSE can do neither of them.
778   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
779     addEarlyCSEOrGVNPass();
780 }
781 
782 void AMDGPUPassConfig::addCodeGenPrepare() {
783   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
784     addPass(createAMDGPUAnnotateKernelFeaturesPass());
785 
786   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
787       EnableLowerKernelArguments)
788     addPass(createAMDGPULowerKernelArgumentsPass());
789 
790   addPass(&AMDGPUPerfHintAnalysisID);
791 
792   TargetPassConfig::addCodeGenPrepare();
793 
794   if (EnableLoadStoreVectorizer)
795     addPass(createLoadStoreVectorizerPass());
796 
797   // LowerSwitch pass may introduce unreachable blocks that can
798   // cause unexpected behavior for subsequent passes. Placing it
799   // here seems better that these blocks would get cleaned up by
800   // UnreachableBlockElim inserted next in the pass flow.
801   addPass(createLowerSwitchPass());
802 }
803 
804 bool AMDGPUPassConfig::addPreISel() {
805   addPass(createFlattenCFGPass());
806   return false;
807 }
808 
809 bool AMDGPUPassConfig::addInstSelector() {
810   // Defer the verifier until FinalizeISel.
811   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
812   return false;
813 }
814 
815 bool AMDGPUPassConfig::addGCPasses() {
816   // Do nothing. GC is not supported.
817   return false;
818 }
819 
820 //===----------------------------------------------------------------------===//
821 // R600 Pass Setup
822 //===----------------------------------------------------------------------===//
823 
824 bool R600PassConfig::addPreISel() {
825   AMDGPUPassConfig::addPreISel();
826 
827   if (EnableR600StructurizeCFG)
828     addPass(createStructurizeCFGPass());
829   return false;
830 }
831 
832 bool R600PassConfig::addInstSelector() {
833   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
834   return false;
835 }
836 
837 void R600PassConfig::addPreRegAlloc() {
838   addPass(createR600VectorRegMerger());
839 }
840 
841 void R600PassConfig::addPreSched2() {
842   addPass(createR600EmitClauseMarkers(), false);
843   if (EnableR600IfConvert)
844     addPass(&IfConverterID, false);
845   addPass(createR600ClauseMergePass(), false);
846 }
847 
848 void R600PassConfig::addPreEmitPass() {
849   addPass(createAMDGPUCFGStructurizerPass(), false);
850   addPass(createR600ExpandSpecialInstrsPass(), false);
851   addPass(&FinalizeMachineBundlesID, false);
852   addPass(createR600Packetizer(), false);
853   addPass(createR600ControlFlowFinalizer(), false);
854 }
855 
856 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
857   return new R600PassConfig(*this, PM);
858 }
859 
860 //===----------------------------------------------------------------------===//
861 // GCN Pass Setup
862 //===----------------------------------------------------------------------===//
863 
864 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
865   MachineSchedContext *C) const {
866   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
867   if (ST.enableSIScheduler())
868     return createSIMachineScheduler(C);
869   return createGCNMaxOccupancyMachineScheduler(C);
870 }
871 
872 bool GCNPassConfig::addPreISel() {
873   AMDGPUPassConfig::addPreISel();
874 
875   if (EnableAtomicOptimizations) {
876     addPass(createAMDGPUAtomicOptimizerPass());
877   }
878 
879   // FIXME: We need to run a pass to propagate the attributes when calls are
880   // supported.
881 
882   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
883   // regions formed by them.
884   addPass(&AMDGPUUnifyDivergentExitNodesID);
885   if (!LateCFGStructurize) {
886     if (EnableStructurizerWorkarounds) {
887       addPass(createFixIrreduciblePass());
888       addPass(createUnifyLoopExitsPass());
889     }
890     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
891   }
892   addPass(createSinkingPass());
893   addPass(createAMDGPUAnnotateUniformValues());
894   if (!LateCFGStructurize) {
895     addPass(createSIAnnotateControlFlowPass());
896   }
897   addPass(createLCSSAPass());
898 
899   return false;
900 }
901 
902 void GCNPassConfig::addMachineSSAOptimization() {
903   TargetPassConfig::addMachineSSAOptimization();
904 
905   // We want to fold operands after PeepholeOptimizer has run (or as part of
906   // it), because it will eliminate extra copies making it easier to fold the
907   // real source operand. We want to eliminate dead instructions after, so that
908   // we see fewer uses of the copies. We then need to clean up the dead
909   // instructions leftover after the operands are folded as well.
910   //
911   // XXX - Can we get away without running DeadMachineInstructionElim again?
912   addPass(&SIFoldOperandsID);
913   if (EnableDPPCombine)
914     addPass(&GCNDPPCombineID);
915   addPass(&DeadMachineInstructionElimID);
916   addPass(&SILoadStoreOptimizerID);
917   if (EnableSDWAPeephole) {
918     addPass(&SIPeepholeSDWAID);
919     addPass(&EarlyMachineLICMID);
920     addPass(&MachineCSEID);
921     addPass(&SIFoldOperandsID);
922     addPass(&DeadMachineInstructionElimID);
923   }
924   addPass(createSIShrinkInstructionsPass());
925 }
926 
927 bool GCNPassConfig::addILPOpts() {
928   if (EnableEarlyIfConversion)
929     addPass(&EarlyIfConverterID);
930 
931   TargetPassConfig::addILPOpts();
932   return false;
933 }
934 
935 bool GCNPassConfig::addInstSelector() {
936   AMDGPUPassConfig::addInstSelector();
937   addPass(&SIFixSGPRCopiesID);
938   addPass(createSILowerI1CopiesPass());
939   // TODO: We have to add FinalizeISel
940   // to expand V_ADD/SUB_U64_PSEUDO before SIFixupVectorISel
941   // that expects V_ADD/SUB -> A_ADDC/SUBB pairs expanded.
942   // Will be removed as soon as SIFixupVectorISel is changed
943   // to work with V_ADD/SUB_U64_PSEUDO instead.
944   addPass(&FinalizeISelID);
945   addPass(createSIFixupVectorISelPass());
946   addPass(createSIAddIMGInitPass());
947   return false;
948 }
949 
950 bool GCNPassConfig::addIRTranslator() {
951   addPass(new IRTranslator());
952   return false;
953 }
954 
955 void GCNPassConfig::addPreLegalizeMachineIR() {
956   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
957   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
958   addPass(new Localizer());
959 }
960 
961 bool GCNPassConfig::addLegalizeMachineIR() {
962   addPass(new Legalizer());
963   return false;
964 }
965 
966 void GCNPassConfig::addPreRegBankSelect() {
967   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
968   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
969 }
970 
971 bool GCNPassConfig::addRegBankSelect() {
972   addPass(new RegBankSelect());
973   return false;
974 }
975 
976 bool GCNPassConfig::addGlobalInstructionSelect() {
977   addPass(new InstructionSelect());
978   return false;
979 }
980 
981 void GCNPassConfig::addPreRegAlloc() {
982   if (LateCFGStructurize) {
983     addPass(createAMDGPUMachineCFGStructurizerPass());
984   }
985   addPass(createSIWholeQuadModePass());
986 }
987 
988 void GCNPassConfig::addFastRegAlloc() {
989   // FIXME: We have to disable the verifier here because of PHIElimination +
990   // TwoAddressInstructions disabling it.
991 
992   // This must be run immediately after phi elimination and before
993   // TwoAddressInstructions, otherwise the processing of the tied operand of
994   // SI_ELSE will introduce a copy of the tied operand source after the else.
995   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
996 
997   // This must be run just after RegisterCoalescing.
998   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
999 
1000   TargetPassConfig::addFastRegAlloc();
1001 }
1002 
1003 void GCNPassConfig::addOptimizedRegAlloc() {
1004   if (OptExecMaskPreRA)
1005     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1006   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1007 
1008   // This must be run immediately after phi elimination and before
1009   // TwoAddressInstructions, otherwise the processing of the tied operand of
1010   // SI_ELSE will introduce a copy of the tied operand source after the else.
1011   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1012 
1013   // This must be run just after RegisterCoalescing.
1014   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
1015 
1016   if (EnableDCEInRA)
1017     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1018 
1019   TargetPassConfig::addOptimizedRegAlloc();
1020 }
1021 
1022 bool GCNPassConfig::addPreRewrite() {
1023   if (EnableRegReassign) {
1024     addPass(&GCNNSAReassignID);
1025     addPass(&GCNRegBankReassignID);
1026   }
1027   return true;
1028 }
1029 
1030 void GCNPassConfig::addPostRegAlloc() {
1031   addPass(&SIFixVGPRCopiesID);
1032   if (getOptLevel() > CodeGenOpt::None)
1033     addPass(&SIOptimizeExecMaskingID);
1034   TargetPassConfig::addPostRegAlloc();
1035 
1036   // Equivalent of PEI for SGPRs.
1037   addPass(&SILowerSGPRSpillsID);
1038 }
1039 
1040 void GCNPassConfig::addPreSched2() {
1041   addPass(&SIPostRABundlerID);
1042 }
1043 
1044 void GCNPassConfig::addPreEmitPass() {
1045   addPass(createSIMemoryLegalizerPass());
1046   addPass(createSIInsertWaitcntsPass());
1047   addPass(createSIShrinkInstructionsPass());
1048   addPass(createSIModeRegisterPass());
1049 
1050   // The hazard recognizer that runs as part of the post-ra scheduler does not
1051   // guarantee to be able handle all hazards correctly. This is because if there
1052   // are multiple scheduling regions in a basic block, the regions are scheduled
1053   // bottom up, so when we begin to schedule a region we don't know what
1054   // instructions were emitted directly before it.
1055   //
1056   // Here we add a stand-alone hazard recognizer pass which can handle all
1057   // cases.
1058   //
1059   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
1060   // be better for it to emit S_NOP <N> when possible.
1061   addPass(&PostRAHazardRecognizerID);
1062   if (getOptLevel() > CodeGenOpt::None)
1063     addPass(&SIInsertHardClausesID);
1064 
1065   addPass(&SIRemoveShortExecBranchesID);
1066   addPass(&SIInsertSkipsPassID);
1067   addPass(&SIPreEmitPeepholeID);
1068   addPass(&BranchRelaxationPassID);
1069 }
1070 
1071 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1072   return new GCNPassConfig(*this, PM);
1073 }
1074 
1075 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1076   return new yaml::SIMachineFunctionInfo();
1077 }
1078 
1079 yaml::MachineFunctionInfo *
1080 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1081   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1082   return new yaml::SIMachineFunctionInfo(*MFI,
1083                                          *MF.getSubtarget().getRegisterInfo());
1084 }
1085 
1086 bool GCNTargetMachine::parseMachineFunctionInfo(
1087     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1088     SMDiagnostic &Error, SMRange &SourceRange) const {
1089   const yaml::SIMachineFunctionInfo &YamlMFI =
1090       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1091   MachineFunction &MF = PFS.MF;
1092   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1093 
1094   MFI->initializeBaseYamlFields(YamlMFI);
1095 
1096   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1097     Register TempReg;
1098     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1099       SourceRange = RegName.SourceRange;
1100       return true;
1101     }
1102     RegVal = TempReg;
1103 
1104     return false;
1105   };
1106 
1107   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1108     // Create a diagnostic for a the register string literal.
1109     const MemoryBuffer &Buffer =
1110         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1111     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1112                          RegName.Value.size(), SourceMgr::DK_Error,
1113                          "incorrect register class for field", RegName.Value,
1114                          None, None);
1115     SourceRange = RegName.SourceRange;
1116     return true;
1117   };
1118 
1119   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1120       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1121       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1122     return true;
1123 
1124   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1125       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1126     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1127   }
1128 
1129   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1130       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1131     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1132   }
1133 
1134   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1135       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1136     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1137   }
1138 
1139   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1140                                    const TargetRegisterClass &RC,
1141                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1142                                    unsigned SystemSGPRs) {
1143     // Skip parsing if it's not present.
1144     if (!A)
1145       return false;
1146 
1147     if (A->IsRegister) {
1148       Register Reg;
1149       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1150         SourceRange = A->RegisterName.SourceRange;
1151         return true;
1152       }
1153       if (!RC.contains(Reg))
1154         return diagnoseRegisterClass(A->RegisterName);
1155       Arg = ArgDescriptor::createRegister(Reg);
1156     } else
1157       Arg = ArgDescriptor::createStack(A->StackOffset);
1158     // Check and apply the optional mask.
1159     if (A->Mask)
1160       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1161 
1162     MFI->NumUserSGPRs += UserSGPRs;
1163     MFI->NumSystemSGPRs += SystemSGPRs;
1164     return false;
1165   };
1166 
1167   if (YamlMFI.ArgInfo &&
1168       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1169                              AMDGPU::SGPR_128RegClass,
1170                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1171        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1172                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1173                              2, 0) ||
1174        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1175                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1176        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1177                              AMDGPU::SReg_64RegClass,
1178                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1179        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1180                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1181                              2, 0) ||
1182        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1183                              AMDGPU::SReg_64RegClass,
1184                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1185        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1186                              AMDGPU::SGPR_32RegClass,
1187                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1188        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1189                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1190                              0, 1) ||
1191        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1192                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1193                              0, 1) ||
1194        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1195                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1196                              0, 1) ||
1197        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1198                              AMDGPU::SGPR_32RegClass,
1199                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1200        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1201                              AMDGPU::SGPR_32RegClass,
1202                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1203        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1204                              AMDGPU::SReg_64RegClass,
1205                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1206        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1207                              AMDGPU::SReg_64RegClass,
1208                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1209        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1210                              AMDGPU::VGPR_32RegClass,
1211                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1212        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1213                              AMDGPU::VGPR_32RegClass,
1214                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1215        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1216                              AMDGPU::VGPR_32RegClass,
1217                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1218     return true;
1219 
1220   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1221   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1222   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1223   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1224   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1225   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1226 
1227   return false;
1228 }
1229