1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600MachineScheduler.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIMachineScheduler.h"
27 #include "TargetInfo/AMDGPUTargetInfo.h"
28 #include "llvm/Analysis/CGSCCPassManager.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/Localizer.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MIRParser/MIParser.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/LegacyPassManager.h"
37 #include "llvm/IR/PassManager.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/Passes/PassBuilder.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Transforms/IPO.h"
42 #include "llvm/Transforms/IPO/AlwaysInliner.h"
43 #include "llvm/Transforms/IPO/GlobalDCE.h"
44 #include "llvm/Transforms/IPO/Internalize.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
49 #include "llvm/Transforms/Utils.h"
50 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
51 #include "llvm/Transforms/Vectorize.h"
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73             cl::desc("Run pre-RA exec mask optimizations"),
74             cl::init(true));
75 
76 static cl::opt<bool> EnableR600IfConvert(
77   "r600-if-convert",
78   cl::desc("Use if conversion pass"),
79   cl::ReallyHidden,
80   cl::init(true));
81 
82 // Option to disable vectorizer for tests.
83 static cl::opt<bool> EnableLoadStoreVectorizer(
84   "amdgpu-load-store-vectorizer",
85   cl::desc("Enable load store vectorizer"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to control global loads scalarization
90 static cl::opt<bool> ScalarizeGlobal(
91   "amdgpu-scalarize-global-loads",
92   cl::desc("Enable global load scalarization"),
93   cl::init(true),
94   cl::Hidden);
95 
96 // Option to run internalize pass.
97 static cl::opt<bool> InternalizeSymbols(
98   "amdgpu-internalize-symbols",
99   cl::desc("Enable elimination of non-kernel functions and unused globals"),
100   cl::init(false),
101   cl::Hidden);
102 
103 // Option to inline all early.
104 static cl::opt<bool> EarlyInlineAll(
105   "amdgpu-early-inline-all",
106   cl::desc("Inline all functions early"),
107   cl::init(false),
108   cl::Hidden);
109 
110 static cl::opt<bool> EnableSDWAPeephole(
111   "amdgpu-sdwa-peephole",
112   cl::desc("Enable SDWA peepholer"),
113   cl::init(true));
114 
115 static cl::opt<bool> EnableDPPCombine(
116   "amdgpu-dpp-combine",
117   cl::desc("Enable DPP combiner"),
118   cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122   cl::desc("Enable AMDGPU Alias Analysis"),
123   cl::init(true));
124 
125 // Option to run late CFG structurizer
126 static cl::opt<bool, true> LateCFGStructurize(
127   "amdgpu-late-structurize",
128   cl::desc("Enable late CFG structurization"),
129   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
130   cl::Hidden);
131 
132 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
133   "amdgpu-function-calls",
134   cl::desc("Enable AMDGPU function call support"),
135   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
136   cl::init(true),
137   cl::Hidden);
138 
139 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
140   "amdgpu-fixed-function-abi",
141   cl::desc("Enable all implicit function arguments"),
142   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
143   cl::init(false),
144   cl::Hidden);
145 
146 // Enable lib calls simplifications
147 static cl::opt<bool> EnableLibCallSimplify(
148   "amdgpu-simplify-libcall",
149   cl::desc("Enable amdgpu library simplifications"),
150   cl::init(true),
151   cl::Hidden);
152 
153 static cl::opt<bool> EnableLowerKernelArguments(
154   "amdgpu-ir-lower-kernel-arguments",
155   cl::desc("Lower kernel argument loads in IR pass"),
156   cl::init(true),
157   cl::Hidden);
158 
159 static cl::opt<bool> EnableRegReassign(
160   "amdgpu-reassign-regs",
161   cl::desc("Enable register reassign optimizations on gfx10+"),
162   cl::init(true),
163   cl::Hidden);
164 
165 // Enable atomic optimization
166 static cl::opt<bool> EnableAtomicOptimizations(
167   "amdgpu-atomic-optimizations",
168   cl::desc("Enable atomic optimizations"),
169   cl::init(false),
170   cl::Hidden);
171 
172 // Enable Mode register optimization
173 static cl::opt<bool> EnableSIModeRegisterPass(
174   "amdgpu-mode-register",
175   cl::desc("Enable mode register pass"),
176   cl::init(true),
177   cl::Hidden);
178 
179 // Option is used in lit tests to prevent deadcoding of patterns inspected.
180 static cl::opt<bool>
181 EnableDCEInRA("amdgpu-dce-in-ra",
182     cl::init(true), cl::Hidden,
183     cl::desc("Enable machine DCE inside regalloc"));
184 
185 static cl::opt<bool> EnableScalarIRPasses(
186   "amdgpu-scalar-ir-passes",
187   cl::desc("Enable scalar IR passes"),
188   cl::init(true),
189   cl::Hidden);
190 
191 static cl::opt<bool> EnableStructurizerWorkarounds(
192     "amdgpu-enable-structurizer-workarounds",
193     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
194     cl::Hidden);
195 
196 static cl::opt<bool, true> EnableLowerModuleLDS(
197     "amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"),
198     cl::location(AMDGPUTargetMachine::EnableLowerModuleLDS), cl::init(true),
199     cl::Hidden);
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFoldOperandsPass(*PR);
220   initializeSIPeepholeSDWAPass(*PR);
221   initializeSIShrinkInstructionsPass(*PR);
222   initializeSIOptimizeExecMaskingPreRAPass(*PR);
223   initializeSILoadStoreOptimizerPass(*PR);
224   initializeAMDGPUFixFunctionBitcastsPass(*PR);
225   initializeAMDGPUAlwaysInlinePass(*PR);
226   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
227   initializeAMDGPUAnnotateUniformValuesPass(*PR);
228   initializeAMDGPUArgumentUsageInfoPass(*PR);
229   initializeAMDGPUAtomicOptimizerPass(*PR);
230   initializeAMDGPULowerKernelArgumentsPass(*PR);
231   initializeAMDGPULowerKernelAttributesPass(*PR);
232   initializeAMDGPULowerIntrinsicsPass(*PR);
233   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
234   initializeAMDGPUPostLegalizerCombinerPass(*PR);
235   initializeAMDGPUPreLegalizerCombinerPass(*PR);
236   initializeAMDGPURegBankCombinerPass(*PR);
237   initializeAMDGPUPromoteAllocaPass(*PR);
238   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
239   initializeAMDGPUCodeGenPreparePass(*PR);
240   initializeAMDGPULateCodeGenPreparePass(*PR);
241   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
242   initializeAMDGPUPropagateAttributesLatePass(*PR);
243   initializeAMDGPULowerModuleLDSPass(*PR);
244   initializeAMDGPURewriteOutArgumentsPass(*PR);
245   initializeAMDGPUUnifyMetadataPass(*PR);
246   initializeSIAnnotateControlFlowPass(*PR);
247   initializeSIInsertHardClausesPass(*PR);
248   initializeSIInsertWaitcntsPass(*PR);
249   initializeSIModeRegisterPass(*PR);
250   initializeSIWholeQuadModePass(*PR);
251   initializeSILowerControlFlowPass(*PR);
252   initializeSIPreEmitPeepholePass(*PR);
253   initializeSILateBranchLoweringPass(*PR);
254   initializeSIMemoryLegalizerPass(*PR);
255   initializeSIOptimizeExecMaskingPass(*PR);
256   initializeSIPreAllocateWWMRegsPass(*PR);
257   initializeSIFormMemoryClausesPass(*PR);
258   initializeSIPostRABundlerPass(*PR);
259   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
260   initializeAMDGPUAAWrapperPassPass(*PR);
261   initializeAMDGPUExternalAAWrapperPass(*PR);
262   initializeAMDGPUUseNativeCallsPass(*PR);
263   initializeAMDGPUSimplifyLibCallsPass(*PR);
264   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
265   initializeGCNNSAReassignPass(*PR);
266 }
267 
268 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
269   return std::make_unique<AMDGPUTargetObjectFile>();
270 }
271 
272 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
273   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
274 }
275 
276 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
277   return new SIScheduleDAGMI(C);
278 }
279 
280 static ScheduleDAGInstrs *
281 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
282   ScheduleDAGMILive *DAG =
283     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
284   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
285   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
286   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
287   return DAG;
288 }
289 
290 static ScheduleDAGInstrs *
291 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
292   auto DAG = new GCNIterativeScheduler(C,
293     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
294   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
295   return DAG;
296 }
297 
298 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
299   return new GCNIterativeScheduler(C,
300     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
301 }
302 
303 static ScheduleDAGInstrs *
304 createIterativeILPMachineScheduler(MachineSchedContext *C) {
305   auto DAG = new GCNIterativeScheduler(C,
306     GCNIterativeScheduler::SCHEDULE_ILP);
307   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
308   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
309   return DAG;
310 }
311 
312 static MachineSchedRegistry
313 R600SchedRegistry("r600", "Run R600's custom scheduler",
314                    createR600MachineScheduler);
315 
316 static MachineSchedRegistry
317 SISchedRegistry("si", "Run SI's custom scheduler",
318                 createSIMachineScheduler);
319 
320 static MachineSchedRegistry
321 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
322                              "Run GCN scheduler to maximize occupancy",
323                              createGCNMaxOccupancyMachineScheduler);
324 
325 static MachineSchedRegistry
326 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
327   "Run GCN scheduler to maximize occupancy (experimental)",
328   createIterativeGCNMaxOccupancyMachineScheduler);
329 
330 static MachineSchedRegistry
331 GCNMinRegSchedRegistry("gcn-minreg",
332   "Run GCN iterative scheduler for minimal register usage (experimental)",
333   createMinRegScheduler);
334 
335 static MachineSchedRegistry
336 GCNILPSchedRegistry("gcn-ilp",
337   "Run GCN iterative scheduler for ILP scheduling (experimental)",
338   createIterativeILPMachineScheduler);
339 
340 static StringRef computeDataLayout(const Triple &TT) {
341   if (TT.getArch() == Triple::r600) {
342     // 32-bit pointers.
343     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
344            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
345   }
346 
347   // 32-bit private, local, and region pointers. 64-bit global, constant and
348   // flat, non-integral buffer fat pointers.
349   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
350          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
351          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
352          "-ni:7";
353 }
354 
355 LLVM_READNONE
356 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
357   if (!GPU.empty())
358     return GPU;
359 
360   // Need to default to a target with flat support for HSA.
361   if (TT.getArch() == Triple::amdgcn)
362     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
363 
364   return "r600";
365 }
366 
367 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
368   // The AMDGPU toolchain only supports generating shared objects, so we
369   // must always use PIC.
370   return Reloc::PIC_;
371 }
372 
373 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
374                                          StringRef CPU, StringRef FS,
375                                          TargetOptions Options,
376                                          Optional<Reloc::Model> RM,
377                                          Optional<CodeModel::Model> CM,
378                                          CodeGenOpt::Level OptLevel)
379     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
380                         FS, Options, getEffectiveRelocModel(RM),
381                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
382       TLOF(createTLOF(getTargetTriple())) {
383   initAsmInfo();
384   if (TT.getArch() == Triple::amdgcn) {
385     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
386       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
387     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
388       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
389   }
390 }
391 
392 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
393 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
394 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
395 bool AMDGPUTargetMachine::EnableLowerModuleLDS = true;
396 
397 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
398 
399 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
400   Attribute GPUAttr = F.getFnAttribute("target-cpu");
401   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
402 }
403 
404 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
405   Attribute FSAttr = F.getFnAttribute("target-features");
406 
407   return FSAttr.isValid() ? FSAttr.getValueAsString()
408                           : getTargetFeatureString();
409 }
410 
411 /// Predicate for Internalize pass.
412 static bool mustPreserveGV(const GlobalValue &GV) {
413   if (const Function *F = dyn_cast<Function>(&GV))
414     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
415 
416   return !GV.use_empty();
417 }
418 
419 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
420   Builder.DivergentTarget = true;
421 
422   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
423   bool Internalize = InternalizeSymbols;
424   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
425   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
426   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
427 
428   if (EnableFunctionCalls) {
429     delete Builder.Inliner;
430     Builder.Inliner = createFunctionInliningPass();
431   }
432 
433   Builder.addExtension(
434     PassManagerBuilder::EP_ModuleOptimizerEarly,
435     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
436                                                legacy::PassManagerBase &PM) {
437       if (AMDGPUAA) {
438         PM.add(createAMDGPUAAWrapperPass());
439         PM.add(createAMDGPUExternalAAWrapperPass());
440       }
441       PM.add(createAMDGPUUnifyMetadataPass());
442       PM.add(createAMDGPUPrintfRuntimeBinding());
443       if (Internalize)
444         PM.add(createInternalizePass(mustPreserveGV));
445       PM.add(createAMDGPUPropagateAttributesLatePass(this));
446       if (Internalize)
447         PM.add(createGlobalDCEPass());
448       if (EarlyInline)
449         PM.add(createAMDGPUAlwaysInlinePass(false));
450   });
451 
452   Builder.addExtension(
453     PassManagerBuilder::EP_EarlyAsPossible,
454     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
455                                       legacy::PassManagerBase &PM) {
456       if (AMDGPUAA) {
457         PM.add(createAMDGPUAAWrapperPass());
458         PM.add(createAMDGPUExternalAAWrapperPass());
459       }
460       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
461       PM.add(llvm::createAMDGPUUseNativeCallsPass());
462       if (LibCallSimplify)
463         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
464   });
465 
466   Builder.addExtension(
467     PassManagerBuilder::EP_CGSCCOptimizerLate,
468     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
469       // Add infer address spaces pass to the opt pipeline after inlining
470       // but before SROA to increase SROA opportunities.
471       PM.add(createInferAddressSpacesPass());
472 
473       // This should run after inlining to have any chance of doing anything,
474       // and before other cleanup optimizations.
475       PM.add(createAMDGPULowerKernelAttributesPass());
476 
477       // Promote alloca to vector before SROA and loop unroll. If we manage
478       // to eliminate allocas before unroll we may choose to unroll less.
479       if (EnableOpt)
480         PM.add(createAMDGPUPromoteAllocaToVector());
481   });
482 }
483 
484 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
485   AAM.registerFunctionAnalysis<AMDGPUAA>();
486 }
487 
488 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
489                                                        bool DebugPassManager) {
490   PB.registerPipelineParsingCallback(
491       [this](StringRef PassName, ModulePassManager &PM,
492              ArrayRef<PassBuilder::PipelineElement>) {
493         if (PassName == "amdgpu-propagate-attributes-late") {
494           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
495           return true;
496         }
497         if (PassName == "amdgpu-unify-metadata") {
498           PM.addPass(AMDGPUUnifyMetadataPass());
499           return true;
500         }
501         if (PassName == "amdgpu-printf-runtime-binding") {
502           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
503           return true;
504         }
505         if (PassName == "amdgpu-always-inline") {
506           PM.addPass(AMDGPUAlwaysInlinePass());
507           return true;
508         }
509         if (PassName == "amdgpu-lower-module-lds") {
510           PM.addPass(AMDGPULowerModuleLDSPass());
511           return true;
512         }
513         return false;
514       });
515   PB.registerPipelineParsingCallback(
516       [this](StringRef PassName, FunctionPassManager &PM,
517              ArrayRef<PassBuilder::PipelineElement>) {
518         if (PassName == "amdgpu-simplifylib") {
519           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
520           return true;
521         }
522         if (PassName == "amdgpu-usenative") {
523           PM.addPass(AMDGPUUseNativeCallsPass());
524           return true;
525         }
526         if (PassName == "amdgpu-promote-alloca") {
527           PM.addPass(AMDGPUPromoteAllocaPass(*this));
528           return true;
529         }
530         if (PassName == "amdgpu-promote-alloca-to-vector") {
531           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
532           return true;
533         }
534         if (PassName == "amdgpu-lower-kernel-attributes") {
535           PM.addPass(AMDGPULowerKernelAttributesPass());
536           return true;
537         }
538         if (PassName == "amdgpu-propagate-attributes-early") {
539           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
540           return true;
541         }
542         return false;
543       });
544 
545   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
546     FAM.registerPass([&] { return AMDGPUAA(); });
547   });
548 
549   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
550     if (AAName == "amdgpu-aa") {
551       AAM.registerFunctionAnalysis<AMDGPUAA>();
552       return true;
553     }
554     return false;
555   });
556 
557   PB.registerPipelineStartEPCallback([this, DebugPassManager](
558                                          ModulePassManager &PM,
559                                          PassBuilder::OptimizationLevel Level) {
560     FunctionPassManager FPM(DebugPassManager);
561     FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
562     FPM.addPass(AMDGPUUseNativeCallsPass());
563     if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
564       FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
565     PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
566   });
567 
568   PB.registerPipelineEarlySimplificationEPCallback(
569       [this](ModulePassManager &PM, PassBuilder::OptimizationLevel Level) {
570         if (Level == PassBuilder::OptimizationLevel::O0)
571           return;
572 
573         PM.addPass(AMDGPUUnifyMetadataPass());
574         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
575 
576         if (InternalizeSymbols) {
577           // Global variables may have dead uses which need to be removed.
578           // Otherwise these useless global variables will not get internalized.
579           PM.addPass(GlobalDCEPass());
580           PM.addPass(InternalizePass(mustPreserveGV));
581         }
582         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
583         if (InternalizeSymbols) {
584           PM.addPass(GlobalDCEPass());
585         }
586         if (EarlyInlineAll && !EnableFunctionCalls)
587           PM.addPass(AMDGPUAlwaysInlinePass());
588       });
589 
590   PB.registerCGSCCOptimizerLateEPCallback(
591       [this, DebugPassManager](CGSCCPassManager &PM,
592                                PassBuilder::OptimizationLevel Level) {
593         if (Level == PassBuilder::OptimizationLevel::O0)
594           return;
595 
596         FunctionPassManager FPM(DebugPassManager);
597 
598         // Add infer address spaces pass to the opt pipeline after inlining
599         // but before SROA to increase SROA opportunities.
600         FPM.addPass(InferAddressSpacesPass());
601 
602         // This should run after inlining to have any chance of doing
603         // anything, and before other cleanup optimizations.
604         FPM.addPass(AMDGPULowerKernelAttributesPass());
605 
606         if (Level != PassBuilder::OptimizationLevel::O0) {
607           // Promote alloca to vector before SROA and loop unroll. If we
608           // manage to eliminate allocas before unroll we may choose to unroll
609           // less.
610           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
611         }
612 
613         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
614       });
615 }
616 
617 //===----------------------------------------------------------------------===//
618 // R600 Target Machine (R600 -> Cayman)
619 //===----------------------------------------------------------------------===//
620 
621 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
622                                      StringRef CPU, StringRef FS,
623                                      TargetOptions Options,
624                                      Optional<Reloc::Model> RM,
625                                      Optional<CodeModel::Model> CM,
626                                      CodeGenOpt::Level OL, bool JIT)
627     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
628   setRequiresStructuredCFG(true);
629 
630   // Override the default since calls aren't supported for r600.
631   if (EnableFunctionCalls &&
632       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
633     EnableFunctionCalls = false;
634 }
635 
636 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
637   const Function &F) const {
638   StringRef GPU = getGPUName(F);
639   StringRef FS = getFeatureString(F);
640 
641   SmallString<128> SubtargetKey(GPU);
642   SubtargetKey.append(FS);
643 
644   auto &I = SubtargetMap[SubtargetKey];
645   if (!I) {
646     // This needs to be done before we create a new subtarget since any
647     // creation will depend on the TM and the code generation flags on the
648     // function that reside in TargetOptions.
649     resetTargetOptions(F);
650     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
651   }
652 
653   return I.get();
654 }
655 
656 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
657   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
658           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
659           AddrSpace == AMDGPUAS::REGION_ADDRESS)
660              ? -1
661              : 0;
662 }
663 
664 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
665                                               unsigned DestAS) const {
666   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
667          AMDGPU::isFlatGlobalAddrSpace(DestAS);
668 }
669 
670 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
671   const auto *LD = dyn_cast<LoadInst>(V);
672   if (!LD)
673     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
674 
675   // It must be a generic pointer loaded.
676   assert(V->getType()->isPointerTy() &&
677          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
678 
679   const auto *Ptr = LD->getPointerOperand();
680   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
681     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
682   // For a generic pointer loaded from the constant memory, it could be assumed
683   // as a global pointer since the constant memory is only populated on the
684   // host side. As implied by the offload programming model, only global
685   // pointers could be referenced on the host side.
686   return AMDGPUAS::GLOBAL_ADDRESS;
687 }
688 
689 TargetTransformInfo
690 R600TargetMachine::getTargetTransformInfo(const Function &F) {
691   return TargetTransformInfo(R600TTIImpl(this, F));
692 }
693 
694 //===----------------------------------------------------------------------===//
695 // GCN Target Machine (SI+)
696 //===----------------------------------------------------------------------===//
697 
698 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
699                                    StringRef CPU, StringRef FS,
700                                    TargetOptions Options,
701                                    Optional<Reloc::Model> RM,
702                                    Optional<CodeModel::Model> CM,
703                                    CodeGenOpt::Level OL, bool JIT)
704     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
705 
706 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
707   StringRef GPU = getGPUName(F);
708   StringRef FS = getFeatureString(F);
709 
710   SmallString<128> SubtargetKey(GPU);
711   SubtargetKey.append(FS);
712 
713   auto &I = SubtargetMap[SubtargetKey];
714   if (!I) {
715     // This needs to be done before we create a new subtarget since any
716     // creation will depend on the TM and the code generation flags on the
717     // function that reside in TargetOptions.
718     resetTargetOptions(F);
719     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
720   }
721 
722   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
723 
724   return I.get();
725 }
726 
727 TargetTransformInfo
728 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
729   return TargetTransformInfo(GCNTTIImpl(this, F));
730 }
731 
732 //===----------------------------------------------------------------------===//
733 // AMDGPU Pass Setup
734 //===----------------------------------------------------------------------===//
735 
736 namespace {
737 
738 class AMDGPUPassConfig : public TargetPassConfig {
739 public:
740   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
741     : TargetPassConfig(TM, PM) {
742     // Exceptions and StackMaps are not supported, so these passes will never do
743     // anything.
744     disablePass(&StackMapLivenessID);
745     disablePass(&FuncletLayoutID);
746   }
747 
748   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
749     return getTM<AMDGPUTargetMachine>();
750   }
751 
752   ScheduleDAGInstrs *
753   createMachineScheduler(MachineSchedContext *C) const override {
754     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
755     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
756     return DAG;
757   }
758 
759   void addEarlyCSEOrGVNPass();
760   void addStraightLineScalarOptimizationPasses();
761   void addIRPasses() override;
762   void addCodeGenPrepare() override;
763   bool addPreISel() override;
764   bool addInstSelector() override;
765   bool addGCPasses() override;
766 
767   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
768 };
769 
770 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
771   return getStandardCSEConfigForOpt(TM->getOptLevel());
772 }
773 
774 class R600PassConfig final : public AMDGPUPassConfig {
775 public:
776   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
777     : AMDGPUPassConfig(TM, PM) {}
778 
779   ScheduleDAGInstrs *createMachineScheduler(
780     MachineSchedContext *C) const override {
781     return createR600MachineScheduler(C);
782   }
783 
784   bool addPreISel() override;
785   bool addInstSelector() override;
786   void addPreRegAlloc() override;
787   void addPreSched2() override;
788   void addPreEmitPass() override;
789 };
790 
791 class GCNPassConfig final : public AMDGPUPassConfig {
792 public:
793   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
794     : AMDGPUPassConfig(TM, PM) {
795     // It is necessary to know the register usage of the entire call graph.  We
796     // allow calls without EnableAMDGPUFunctionCalls if they are marked
797     // noinline, so this is always required.
798     setRequiresCodeGenSCCOrder(true);
799   }
800 
801   GCNTargetMachine &getGCNTargetMachine() const {
802     return getTM<GCNTargetMachine>();
803   }
804 
805   ScheduleDAGInstrs *
806   createMachineScheduler(MachineSchedContext *C) const override;
807 
808   bool addPreISel() override;
809   void addMachineSSAOptimization() override;
810   bool addILPOpts() override;
811   bool addInstSelector() override;
812   bool addIRTranslator() override;
813   void addPreLegalizeMachineIR() override;
814   bool addLegalizeMachineIR() override;
815   void addPreRegBankSelect() override;
816   bool addRegBankSelect() override;
817   void addPreGlobalInstructionSelect() override;
818   bool addGlobalInstructionSelect() override;
819   void addFastRegAlloc() override;
820   void addOptimizedRegAlloc() override;
821   void addPreRegAlloc() override;
822   bool addPreRewrite() override;
823   void addPostRegAlloc() override;
824   void addPreSched2() override;
825   void addPreEmitPass() override;
826 };
827 
828 } // end anonymous namespace
829 
830 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
831   if (getOptLevel() == CodeGenOpt::Aggressive)
832     addPass(createGVNPass());
833   else
834     addPass(createEarlyCSEPass());
835 }
836 
837 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
838   addPass(createLICMPass());
839   addPass(createSeparateConstOffsetFromGEPPass());
840   addPass(createSpeculativeExecutionPass());
841   // ReassociateGEPs exposes more opportunites for SLSR. See
842   // the example in reassociate-geps-and-slsr.ll.
843   addPass(createStraightLineStrengthReducePass());
844   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
845   // EarlyCSE can reuse.
846   addEarlyCSEOrGVNPass();
847   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
848   addPass(createNaryReassociatePass());
849   // NaryReassociate on GEPs creates redundant common expressions, so run
850   // EarlyCSE after it.
851   addPass(createEarlyCSEPass());
852 }
853 
854 void AMDGPUPassConfig::addIRPasses() {
855   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
856 
857   // There is no reason to run these.
858   disablePass(&StackMapLivenessID);
859   disablePass(&FuncletLayoutID);
860   disablePass(&PatchableFunctionID);
861 
862   addPass(createAMDGPUPrintfRuntimeBinding());
863 
864   // This must occur before inlining, as the inliner will not look through
865   // bitcast calls.
866   addPass(createAMDGPUFixFunctionBitcastsPass());
867 
868   // A call to propagate attributes pass in the backend in case opt was not run.
869   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
870 
871   addPass(createAtomicExpandPass());
872 
873 
874   addPass(createAMDGPULowerIntrinsicsPass());
875 
876   // Function calls are not supported, so make sure we inline everything.
877   addPass(createAMDGPUAlwaysInlinePass());
878   addPass(createAlwaysInlinerLegacyPass());
879   // We need to add the barrier noop pass, otherwise adding the function
880   // inlining pass will cause all of the PassConfigs passes to be run
881   // one function at a time, which means if we have a nodule with two
882   // functions, then we will generate code for the first function
883   // without ever running any passes on the second.
884   addPass(createBarrierNoopPass());
885 
886   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
887   if (TM.getTargetTriple().getArch() == Triple::r600)
888     addPass(createR600OpenCLImageTypeLoweringPass());
889 
890   // Replace OpenCL enqueued block function pointers with global variables.
891   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
892 
893   // Can increase LDS used by kernel so runs before PromoteAlloca
894   if (EnableLowerModuleLDS)
895     addPass(createAMDGPULowerModuleLDSPass());
896 
897   if (TM.getOptLevel() > CodeGenOpt::None) {
898     addPass(createInferAddressSpacesPass());
899     addPass(createAMDGPUPromoteAlloca());
900 
901     if (EnableSROA)
902       addPass(createSROAPass());
903 
904     if (EnableScalarIRPasses)
905       addStraightLineScalarOptimizationPasses();
906 
907     if (EnableAMDGPUAliasAnalysis) {
908       addPass(createAMDGPUAAWrapperPass());
909       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
910                                              AAResults &AAR) {
911         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
912           AAR.addAAResult(WrapperPass->getResult());
913         }));
914     }
915   }
916 
917   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
918     // TODO: May want to move later or split into an early and late one.
919     addPass(createAMDGPUCodeGenPreparePass());
920   }
921 
922   TargetPassConfig::addIRPasses();
923 
924   // EarlyCSE is not always strong enough to clean up what LSR produces. For
925   // example, GVN can combine
926   //
927   //   %0 = add %a, %b
928   //   %1 = add %b, %a
929   //
930   // and
931   //
932   //   %0 = shl nsw %a, 2
933   //   %1 = shl %a, 2
934   //
935   // but EarlyCSE can do neither of them.
936   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
937     addEarlyCSEOrGVNPass();
938 }
939 
940 void AMDGPUPassConfig::addCodeGenPrepare() {
941   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
942     addPass(createAMDGPUAnnotateKernelFeaturesPass());
943 
944   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
945       EnableLowerKernelArguments)
946     addPass(createAMDGPULowerKernelArgumentsPass());
947 
948   addPass(&AMDGPUPerfHintAnalysisID);
949 
950   TargetPassConfig::addCodeGenPrepare();
951 
952   if (EnableLoadStoreVectorizer)
953     addPass(createLoadStoreVectorizerPass());
954 
955   // LowerSwitch pass may introduce unreachable blocks that can
956   // cause unexpected behavior for subsequent passes. Placing it
957   // here seems better that these blocks would get cleaned up by
958   // UnreachableBlockElim inserted next in the pass flow.
959   addPass(createLowerSwitchPass());
960 }
961 
962 bool AMDGPUPassConfig::addPreISel() {
963   addPass(createFlattenCFGPass());
964   return false;
965 }
966 
967 bool AMDGPUPassConfig::addInstSelector() {
968   // Defer the verifier until FinalizeISel.
969   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
970   return false;
971 }
972 
973 bool AMDGPUPassConfig::addGCPasses() {
974   // Do nothing. GC is not supported.
975   return false;
976 }
977 
978 //===----------------------------------------------------------------------===//
979 // R600 Pass Setup
980 //===----------------------------------------------------------------------===//
981 
982 bool R600PassConfig::addPreISel() {
983   AMDGPUPassConfig::addPreISel();
984 
985   if (EnableR600StructurizeCFG)
986     addPass(createStructurizeCFGPass());
987   return false;
988 }
989 
990 bool R600PassConfig::addInstSelector() {
991   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
992   return false;
993 }
994 
995 void R600PassConfig::addPreRegAlloc() {
996   addPass(createR600VectorRegMerger());
997 }
998 
999 void R600PassConfig::addPreSched2() {
1000   addPass(createR600EmitClauseMarkers(), false);
1001   if (EnableR600IfConvert)
1002     addPass(&IfConverterID, false);
1003   addPass(createR600ClauseMergePass(), false);
1004 }
1005 
1006 void R600PassConfig::addPreEmitPass() {
1007   addPass(createAMDGPUCFGStructurizerPass(), false);
1008   addPass(createR600ExpandSpecialInstrsPass(), false);
1009   addPass(&FinalizeMachineBundlesID, false);
1010   addPass(createR600Packetizer(), false);
1011   addPass(createR600ControlFlowFinalizer(), false);
1012 }
1013 
1014 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
1015   return new R600PassConfig(*this, PM);
1016 }
1017 
1018 //===----------------------------------------------------------------------===//
1019 // GCN Pass Setup
1020 //===----------------------------------------------------------------------===//
1021 
1022 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1023   MachineSchedContext *C) const {
1024   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1025   if (ST.enableSIScheduler())
1026     return createSIMachineScheduler(C);
1027   return createGCNMaxOccupancyMachineScheduler(C);
1028 }
1029 
1030 bool GCNPassConfig::addPreISel() {
1031   AMDGPUPassConfig::addPreISel();
1032 
1033   addPass(createAMDGPULateCodeGenPreparePass());
1034   if (EnableAtomicOptimizations) {
1035     addPass(createAMDGPUAtomicOptimizerPass());
1036   }
1037 
1038   // FIXME: We need to run a pass to propagate the attributes when calls are
1039   // supported.
1040 
1041   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1042   // regions formed by them.
1043   addPass(&AMDGPUUnifyDivergentExitNodesID);
1044   if (!LateCFGStructurize) {
1045     if (EnableStructurizerWorkarounds) {
1046       addPass(createFixIrreduciblePass());
1047       addPass(createUnifyLoopExitsPass());
1048     }
1049     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1050   }
1051   addPass(createSinkingPass());
1052   addPass(createAMDGPUAnnotateUniformValues());
1053   if (!LateCFGStructurize) {
1054     addPass(createSIAnnotateControlFlowPass());
1055   }
1056   addPass(createLCSSAPass());
1057 
1058   return false;
1059 }
1060 
1061 void GCNPassConfig::addMachineSSAOptimization() {
1062   TargetPassConfig::addMachineSSAOptimization();
1063 
1064   // We want to fold operands after PeepholeOptimizer has run (or as part of
1065   // it), because it will eliminate extra copies making it easier to fold the
1066   // real source operand. We want to eliminate dead instructions after, so that
1067   // we see fewer uses of the copies. We then need to clean up the dead
1068   // instructions leftover after the operands are folded as well.
1069   //
1070   // XXX - Can we get away without running DeadMachineInstructionElim again?
1071   addPass(&SIFoldOperandsID);
1072   if (EnableDPPCombine)
1073     addPass(&GCNDPPCombineID);
1074   addPass(&SILoadStoreOptimizerID);
1075   if (EnableSDWAPeephole) {
1076     addPass(&SIPeepholeSDWAID);
1077     addPass(&EarlyMachineLICMID);
1078     addPass(&MachineCSEID);
1079     addPass(&SIFoldOperandsID);
1080   }
1081   addPass(&DeadMachineInstructionElimID);
1082   addPass(createSIShrinkInstructionsPass());
1083 }
1084 
1085 bool GCNPassConfig::addILPOpts() {
1086   if (EnableEarlyIfConversion)
1087     addPass(&EarlyIfConverterID);
1088 
1089   TargetPassConfig::addILPOpts();
1090   return false;
1091 }
1092 
1093 bool GCNPassConfig::addInstSelector() {
1094   AMDGPUPassConfig::addInstSelector();
1095   addPass(&SIFixSGPRCopiesID);
1096   addPass(createSILowerI1CopiesPass());
1097   return false;
1098 }
1099 
1100 bool GCNPassConfig::addIRTranslator() {
1101   addPass(new IRTranslator(getOptLevel()));
1102   return false;
1103 }
1104 
1105 void GCNPassConfig::addPreLegalizeMachineIR() {
1106   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1107   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1108   addPass(new Localizer());
1109 }
1110 
1111 bool GCNPassConfig::addLegalizeMachineIR() {
1112   addPass(new Legalizer());
1113   return false;
1114 }
1115 
1116 void GCNPassConfig::addPreRegBankSelect() {
1117   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1118   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1119 }
1120 
1121 bool GCNPassConfig::addRegBankSelect() {
1122   addPass(new RegBankSelect());
1123   return false;
1124 }
1125 
1126 void GCNPassConfig::addPreGlobalInstructionSelect() {
1127   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1128   addPass(createAMDGPURegBankCombiner(IsOptNone));
1129 }
1130 
1131 bool GCNPassConfig::addGlobalInstructionSelect() {
1132   addPass(new InstructionSelect(getOptLevel()));
1133   return false;
1134 }
1135 
1136 void GCNPassConfig::addPreRegAlloc() {
1137   if (LateCFGStructurize) {
1138     addPass(createAMDGPUMachineCFGStructurizerPass());
1139   }
1140 }
1141 
1142 void GCNPassConfig::addFastRegAlloc() {
1143   // FIXME: We have to disable the verifier here because of PHIElimination +
1144   // TwoAddressInstructions disabling it.
1145 
1146   // This must be run immediately after phi elimination and before
1147   // TwoAddressInstructions, otherwise the processing of the tied operand of
1148   // SI_ELSE will introduce a copy of the tied operand source after the else.
1149   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1150 
1151   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1152   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1153 
1154   TargetPassConfig::addFastRegAlloc();
1155 }
1156 
1157 void GCNPassConfig::addOptimizedRegAlloc() {
1158   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1159   // instructions that cause scheduling barriers.
1160   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1161   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1162 
1163   if (OptExecMaskPreRA)
1164     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1165   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1166 
1167   // This must be run immediately after phi elimination and before
1168   // TwoAddressInstructions, otherwise the processing of the tied operand of
1169   // SI_ELSE will introduce a copy of the tied operand source after the else.
1170   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1171 
1172   if (EnableDCEInRA)
1173     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1174 
1175   TargetPassConfig::addOptimizedRegAlloc();
1176 }
1177 
1178 bool GCNPassConfig::addPreRewrite() {
1179   if (EnableRegReassign)
1180     addPass(&GCNNSAReassignID);
1181   return true;
1182 }
1183 
1184 void GCNPassConfig::addPostRegAlloc() {
1185   addPass(&SIFixVGPRCopiesID);
1186   if (getOptLevel() > CodeGenOpt::None)
1187     addPass(&SIOptimizeExecMaskingID);
1188   TargetPassConfig::addPostRegAlloc();
1189 
1190   // Equivalent of PEI for SGPRs.
1191   addPass(&SILowerSGPRSpillsID);
1192 }
1193 
1194 void GCNPassConfig::addPreSched2() {
1195   addPass(&SIPostRABundlerID);
1196 }
1197 
1198 void GCNPassConfig::addPreEmitPass() {
1199   addPass(createSIMemoryLegalizerPass());
1200   addPass(createSIInsertWaitcntsPass());
1201   addPass(createSIShrinkInstructionsPass());
1202   addPass(createSIModeRegisterPass());
1203 
1204   if (getOptLevel() > CodeGenOpt::None)
1205     addPass(&SIInsertHardClausesID);
1206 
1207   addPass(&SILateBranchLoweringPassID);
1208   if (getOptLevel() > CodeGenOpt::None)
1209     addPass(&SIPreEmitPeepholeID);
1210   // The hazard recognizer that runs as part of the post-ra scheduler does not
1211   // guarantee to be able handle all hazards correctly. This is because if there
1212   // are multiple scheduling regions in a basic block, the regions are scheduled
1213   // bottom up, so when we begin to schedule a region we don't know what
1214   // instructions were emitted directly before it.
1215   //
1216   // Here we add a stand-alone hazard recognizer pass which can handle all
1217   // cases.
1218   addPass(&PostRAHazardRecognizerID);
1219   addPass(&BranchRelaxationPassID);
1220 }
1221 
1222 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1223   return new GCNPassConfig(*this, PM);
1224 }
1225 
1226 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1227   return new yaml::SIMachineFunctionInfo();
1228 }
1229 
1230 yaml::MachineFunctionInfo *
1231 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1232   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1233   return new yaml::SIMachineFunctionInfo(*MFI,
1234                                          *MF.getSubtarget().getRegisterInfo());
1235 }
1236 
1237 bool GCNTargetMachine::parseMachineFunctionInfo(
1238     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1239     SMDiagnostic &Error, SMRange &SourceRange) const {
1240   const yaml::SIMachineFunctionInfo &YamlMFI =
1241       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1242   MachineFunction &MF = PFS.MF;
1243   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1244 
1245   MFI->initializeBaseYamlFields(YamlMFI);
1246 
1247   if (MFI->Occupancy == 0) {
1248     // Fixup the subtarget dependent default value.
1249     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1250     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1251   }
1252 
1253   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1254     Register TempReg;
1255     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1256       SourceRange = RegName.SourceRange;
1257       return true;
1258     }
1259     RegVal = TempReg;
1260 
1261     return false;
1262   };
1263 
1264   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1265     // Create a diagnostic for a the register string literal.
1266     const MemoryBuffer &Buffer =
1267         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1268     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1269                          RegName.Value.size(), SourceMgr::DK_Error,
1270                          "incorrect register class for field", RegName.Value,
1271                          None, None);
1272     SourceRange = RegName.SourceRange;
1273     return true;
1274   };
1275 
1276   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1277       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1278       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1279     return true;
1280 
1281   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1282       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1283     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1284   }
1285 
1286   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1287       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1288     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1289   }
1290 
1291   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1292       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1293     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1294   }
1295 
1296   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1297                                    const TargetRegisterClass &RC,
1298                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1299                                    unsigned SystemSGPRs) {
1300     // Skip parsing if it's not present.
1301     if (!A)
1302       return false;
1303 
1304     if (A->IsRegister) {
1305       Register Reg;
1306       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1307         SourceRange = A->RegisterName.SourceRange;
1308         return true;
1309       }
1310       if (!RC.contains(Reg))
1311         return diagnoseRegisterClass(A->RegisterName);
1312       Arg = ArgDescriptor::createRegister(Reg);
1313     } else
1314       Arg = ArgDescriptor::createStack(A->StackOffset);
1315     // Check and apply the optional mask.
1316     if (A->Mask)
1317       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1318 
1319     MFI->NumUserSGPRs += UserSGPRs;
1320     MFI->NumSystemSGPRs += SystemSGPRs;
1321     return false;
1322   };
1323 
1324   if (YamlMFI.ArgInfo &&
1325       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1326                              AMDGPU::SGPR_128RegClass,
1327                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1328        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1329                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1330                              2, 0) ||
1331        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1332                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1333        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1334                              AMDGPU::SReg_64RegClass,
1335                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1336        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1337                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1338                              2, 0) ||
1339        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1340                              AMDGPU::SReg_64RegClass,
1341                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1342        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1343                              AMDGPU::SGPR_32RegClass,
1344                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1345        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1346                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1347                              0, 1) ||
1348        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1349                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1350                              0, 1) ||
1351        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1352                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1353                              0, 1) ||
1354        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1355                              AMDGPU::SGPR_32RegClass,
1356                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1357        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1358                              AMDGPU::SGPR_32RegClass,
1359                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1360        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1361                              AMDGPU::SReg_64RegClass,
1362                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1363        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1364                              AMDGPU::SReg_64RegClass,
1365                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1366        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1367                              AMDGPU::VGPR_32RegClass,
1368                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1369        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1370                              AMDGPU::VGPR_32RegClass,
1371                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1372        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1373                              AMDGPU::VGPR_32RegClass,
1374                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1375     return true;
1376 
1377   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1378   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1379   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1380   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1381   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1382   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1383 
1384   return false;
1385 }
1386