1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUExportClustering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
28 #include "R600MachineScheduler.h"
29 #include "SIMachineFunctionInfo.h"
30 #include "SIMachineScheduler.h"
31 #include "TargetInfo/AMDGPUTargetInfo.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
35 #include "llvm/CodeGen/GlobalISel/Localizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MIRParser/MIParser.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/LegacyPassManager.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/Pass.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Transforms/IPO.h"
50 #include "llvm/Transforms/IPO/AlwaysInliner.h"
51 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
52 #include "llvm/Transforms/Scalar.h"
53 #include "llvm/Transforms/Scalar/GVN.h"
54 #include "llvm/Transforms/Utils.h"
55 #include "llvm/Transforms/Vectorize.h"
56 #include <memory>
57 
58 using namespace llvm;
59 
60 static cl::opt<bool> EnableR600StructurizeCFG(
61   "r600-ir-structurize",
62   cl::desc("Use StructurizeCFG IR pass"),
63   cl::init(true));
64 
65 static cl::opt<bool> EnableSROA(
66   "amdgpu-sroa",
67   cl::desc("Run SROA after promote alloca pass"),
68   cl::ReallyHidden,
69   cl::init(true));
70 
71 static cl::opt<bool>
72 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
73                         cl::desc("Run early if-conversion"),
74                         cl::init(false));
75 
76 static cl::opt<bool>
77 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
78             cl::desc("Run pre-RA exec mask optimizations"),
79             cl::init(true));
80 
81 static cl::opt<bool> EnableR600IfConvert(
82   "r600-if-convert",
83   cl::desc("Use if conversion pass"),
84   cl::ReallyHidden,
85   cl::init(true));
86 
87 // Option to disable vectorizer for tests.
88 static cl::opt<bool> EnableLoadStoreVectorizer(
89   "amdgpu-load-store-vectorizer",
90   cl::desc("Enable load store vectorizer"),
91   cl::init(true),
92   cl::Hidden);
93 
94 // Option to control global loads scalarization
95 static cl::opt<bool> ScalarizeGlobal(
96   "amdgpu-scalarize-global-loads",
97   cl::desc("Enable global load scalarization"),
98   cl::init(true),
99   cl::Hidden);
100 
101 // Option to run internalize pass.
102 static cl::opt<bool> InternalizeSymbols(
103   "amdgpu-internalize-symbols",
104   cl::desc("Enable elimination of non-kernel functions and unused globals"),
105   cl::init(false),
106   cl::Hidden);
107 
108 // Option to inline all early.
109 static cl::opt<bool> EarlyInlineAll(
110   "amdgpu-early-inline-all",
111   cl::desc("Inline all functions early"),
112   cl::init(false),
113   cl::Hidden);
114 
115 static cl::opt<bool> EnableSDWAPeephole(
116   "amdgpu-sdwa-peephole",
117   cl::desc("Enable SDWA peepholer"),
118   cl::init(true));
119 
120 static cl::opt<bool> EnableDPPCombine(
121   "amdgpu-dpp-combine",
122   cl::desc("Enable DPP combiner"),
123   cl::init(true));
124 
125 // Enable address space based alias analysis
126 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
127   cl::desc("Enable AMDGPU Alias Analysis"),
128   cl::init(true));
129 
130 // Option to run late CFG structurizer
131 static cl::opt<bool, true> LateCFGStructurize(
132   "amdgpu-late-structurize",
133   cl::desc("Enable late CFG structurization"),
134   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
135   cl::Hidden);
136 
137 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
138   "amdgpu-function-calls",
139   cl::desc("Enable AMDGPU function call support"),
140   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
141   cl::init(true),
142   cl::Hidden);
143 
144 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
145   "amdgpu-fixed-function-abi",
146   cl::desc("Enable all implicit function arguments"),
147   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
148   cl::init(false),
149   cl::Hidden);
150 
151 // Enable lib calls simplifications
152 static cl::opt<bool> EnableLibCallSimplify(
153   "amdgpu-simplify-libcall",
154   cl::desc("Enable amdgpu library simplifications"),
155   cl::init(true),
156   cl::Hidden);
157 
158 static cl::opt<bool> EnableLowerKernelArguments(
159   "amdgpu-ir-lower-kernel-arguments",
160   cl::desc("Lower kernel argument loads in IR pass"),
161   cl::init(true),
162   cl::Hidden);
163 
164 static cl::opt<bool> EnableRegReassign(
165   "amdgpu-reassign-regs",
166   cl::desc("Enable register reassign optimizations on gfx10+"),
167   cl::init(true),
168   cl::Hidden);
169 
170 // Enable atomic optimization
171 static cl::opt<bool> EnableAtomicOptimizations(
172   "amdgpu-atomic-optimizations",
173   cl::desc("Enable atomic optimizations"),
174   cl::init(false),
175   cl::Hidden);
176 
177 // Enable Mode register optimization
178 static cl::opt<bool> EnableSIModeRegisterPass(
179   "amdgpu-mode-register",
180   cl::desc("Enable mode register pass"),
181   cl::init(true),
182   cl::Hidden);
183 
184 // Option is used in lit tests to prevent deadcoding of patterns inspected.
185 static cl::opt<bool>
186 EnableDCEInRA("amdgpu-dce-in-ra",
187     cl::init(true), cl::Hidden,
188     cl::desc("Enable machine DCE inside regalloc"));
189 
190 static cl::opt<bool> EnableScalarIRPasses(
191   "amdgpu-scalar-ir-passes",
192   cl::desc("Enable scalar IR passes"),
193   cl::init(true),
194   cl::Hidden);
195 
196 static cl::opt<bool> EnableStructurizerWorkarounds(
197     "amdgpu-enable-structurizer-workarounds",
198     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
199     cl::Hidden);
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFoldOperandsPass(*PR);
220   initializeSIPeepholeSDWAPass(*PR);
221   initializeSIShrinkInstructionsPass(*PR);
222   initializeSIOptimizeExecMaskingPreRAPass(*PR);
223   initializeSILoadStoreOptimizerPass(*PR);
224   initializeAMDGPUFixFunctionBitcastsPass(*PR);
225   initializeAMDGPUAlwaysInlinePass(*PR);
226   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
227   initializeAMDGPUAnnotateUniformValuesPass(*PR);
228   initializeAMDGPUArgumentUsageInfoPass(*PR);
229   initializeAMDGPUAtomicOptimizerPass(*PR);
230   initializeAMDGPULowerKernelArgumentsPass(*PR);
231   initializeAMDGPULowerKernelAttributesPass(*PR);
232   initializeAMDGPULowerIntrinsicsPass(*PR);
233   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
234   initializeAMDGPUPostLegalizerCombinerPass(*PR);
235   initializeAMDGPUPreLegalizerCombinerPass(*PR);
236   initializeAMDGPUPromoteAllocaPass(*PR);
237   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
238   initializeAMDGPUCodeGenPreparePass(*PR);
239   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
240   initializeAMDGPUPropagateAttributesLatePass(*PR);
241   initializeAMDGPURewriteOutArgumentsPass(*PR);
242   initializeAMDGPUUnifyMetadataPass(*PR);
243   initializeSIAnnotateControlFlowPass(*PR);
244   initializeSIInsertHardClausesPass(*PR);
245   initializeSIInsertWaitcntsPass(*PR);
246   initializeSIModeRegisterPass(*PR);
247   initializeSIWholeQuadModePass(*PR);
248   initializeSILowerControlFlowPass(*PR);
249   initializeSIRemoveShortExecBranchesPass(*PR);
250   initializeSIPreEmitPeepholePass(*PR);
251   initializeSIInsertSkipsPass(*PR);
252   initializeSIMemoryLegalizerPass(*PR);
253   initializeSIOptimizeExecMaskingPass(*PR);
254   initializeSIPreAllocateWWMRegsPass(*PR);
255   initializeSIFormMemoryClausesPass(*PR);
256   initializeSIPostRABundlerPass(*PR);
257   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
258   initializeAMDGPUAAWrapperPassPass(*PR);
259   initializeAMDGPUExternalAAWrapperPass(*PR);
260   initializeAMDGPUUseNativeCallsPass(*PR);
261   initializeAMDGPUSimplifyLibCallsPass(*PR);
262   initializeAMDGPUInlinerPass(*PR);
263   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
264   initializeGCNRegBankReassignPass(*PR);
265   initializeGCNNSAReassignPass(*PR);
266   initializeSIAddIMGInitPass(*PR);
267 }
268 
269 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
270   return std::make_unique<AMDGPUTargetObjectFile>();
271 }
272 
273 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
274   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
275 }
276 
277 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
278   return new SIScheduleDAGMI(C);
279 }
280 
281 static ScheduleDAGInstrs *
282 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
283   ScheduleDAGMILive *DAG =
284     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
285   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
286   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
287   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
288   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
289   return DAG;
290 }
291 
292 static ScheduleDAGInstrs *
293 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
294   auto DAG = new GCNIterativeScheduler(C,
295     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
296   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
297   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
298   return DAG;
299 }
300 
301 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
302   return new GCNIterativeScheduler(C,
303     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
304 }
305 
306 static ScheduleDAGInstrs *
307 createIterativeILPMachineScheduler(MachineSchedContext *C) {
308   auto DAG = new GCNIterativeScheduler(C,
309     GCNIterativeScheduler::SCHEDULE_ILP);
310   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
311   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
312   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
313   return DAG;
314 }
315 
316 static MachineSchedRegistry
317 R600SchedRegistry("r600", "Run R600's custom scheduler",
318                    createR600MachineScheduler);
319 
320 static MachineSchedRegistry
321 SISchedRegistry("si", "Run SI's custom scheduler",
322                 createSIMachineScheduler);
323 
324 static MachineSchedRegistry
325 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
326                              "Run GCN scheduler to maximize occupancy",
327                              createGCNMaxOccupancyMachineScheduler);
328 
329 static MachineSchedRegistry
330 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
331   "Run GCN scheduler to maximize occupancy (experimental)",
332   createIterativeGCNMaxOccupancyMachineScheduler);
333 
334 static MachineSchedRegistry
335 GCNMinRegSchedRegistry("gcn-minreg",
336   "Run GCN iterative scheduler for minimal register usage (experimental)",
337   createMinRegScheduler);
338 
339 static MachineSchedRegistry
340 GCNILPSchedRegistry("gcn-ilp",
341   "Run GCN iterative scheduler for ILP scheduling (experimental)",
342   createIterativeILPMachineScheduler);
343 
344 static StringRef computeDataLayout(const Triple &TT) {
345   if (TT.getArch() == Triple::r600) {
346     // 32-bit pointers.
347       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
348              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
349   }
350 
351   // 32-bit private, local, and region pointers. 64-bit global, constant and
352   // flat, non-integral buffer fat pointers.
353     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
354          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
355          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
356          "-ni:7";
357 }
358 
359 LLVM_READNONE
360 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
361   if (!GPU.empty())
362     return GPU;
363 
364   // Need to default to a target with flat support for HSA.
365   if (TT.getArch() == Triple::amdgcn)
366     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
367 
368   return "r600";
369 }
370 
371 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
372   // The AMDGPU toolchain only supports generating shared objects, so we
373   // must always use PIC.
374   return Reloc::PIC_;
375 }
376 
377 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
378                                          StringRef CPU, StringRef FS,
379                                          TargetOptions Options,
380                                          Optional<Reloc::Model> RM,
381                                          Optional<CodeModel::Model> CM,
382                                          CodeGenOpt::Level OptLevel)
383     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
384                         FS, Options, getEffectiveRelocModel(RM),
385                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
386       TLOF(createTLOF(getTargetTriple())) {
387   initAsmInfo();
388   if (TT.getArch() == Triple::amdgcn) {
389     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
390       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
391     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
392       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
393   }
394 }
395 
396 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
397 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
398 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
399 
400 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
401 
402 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
403   Attribute GPUAttr = F.getFnAttribute("target-cpu");
404   return GPUAttr.hasAttribute(Attribute::None) ?
405     getTargetCPU() : GPUAttr.getValueAsString();
406 }
407 
408 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
409   Attribute FSAttr = F.getFnAttribute("target-features");
410 
411   return FSAttr.hasAttribute(Attribute::None) ?
412     getTargetFeatureString() :
413     FSAttr.getValueAsString();
414 }
415 
416 /// Predicate for Internalize pass.
417 static bool mustPreserveGV(const GlobalValue &GV) {
418   if (const Function *F = dyn_cast<Function>(&GV))
419     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
420 
421   return !GV.use_empty();
422 }
423 
424 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
425   Builder.DivergentTarget = true;
426 
427   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
428   bool Internalize = InternalizeSymbols;
429   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
430   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
431   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
432 
433   if (EnableFunctionCalls) {
434     delete Builder.Inliner;
435     Builder.Inliner = createAMDGPUFunctionInliningPass();
436   }
437 
438   Builder.addExtension(
439     PassManagerBuilder::EP_ModuleOptimizerEarly,
440     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
441                                                legacy::PassManagerBase &PM) {
442       if (AMDGPUAA) {
443         PM.add(createAMDGPUAAWrapperPass());
444         PM.add(createAMDGPUExternalAAWrapperPass());
445       }
446       PM.add(createAMDGPUUnifyMetadataPass());
447       PM.add(createAMDGPUPrintfRuntimeBinding());
448       if (Internalize)
449         PM.add(createInternalizePass(mustPreserveGV));
450       PM.add(createAMDGPUPropagateAttributesLatePass(this));
451       if (Internalize)
452         PM.add(createGlobalDCEPass());
453       if (EarlyInline)
454         PM.add(createAMDGPUAlwaysInlinePass(false));
455   });
456 
457   Builder.addExtension(
458     PassManagerBuilder::EP_EarlyAsPossible,
459     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
460                                       legacy::PassManagerBase &PM) {
461       if (AMDGPUAA) {
462         PM.add(createAMDGPUAAWrapperPass());
463         PM.add(createAMDGPUExternalAAWrapperPass());
464       }
465       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
466       PM.add(llvm::createAMDGPUUseNativeCallsPass());
467       if (LibCallSimplify)
468         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
469   });
470 
471   Builder.addExtension(
472     PassManagerBuilder::EP_CGSCCOptimizerLate,
473     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
474       // Add infer address spaces pass to the opt pipeline after inlining
475       // but before SROA to increase SROA opportunities.
476       PM.add(createInferAddressSpacesPass());
477 
478       // This should run after inlining to have any chance of doing anything,
479       // and before other cleanup optimizations.
480       PM.add(createAMDGPULowerKernelAttributesPass());
481 
482       // Promote alloca to vector before SROA and loop unroll. If we manage
483       // to eliminate allocas before unroll we may choose to unroll less.
484       if (EnableOpt)
485         PM.add(createAMDGPUPromoteAllocaToVector());
486   });
487 }
488 
489 //===----------------------------------------------------------------------===//
490 // R600 Target Machine (R600 -> Cayman)
491 //===----------------------------------------------------------------------===//
492 
493 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
494                                      StringRef CPU, StringRef FS,
495                                      TargetOptions Options,
496                                      Optional<Reloc::Model> RM,
497                                      Optional<CodeModel::Model> CM,
498                                      CodeGenOpt::Level OL, bool JIT)
499     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
500   setRequiresStructuredCFG(true);
501 
502   // Override the default since calls aren't supported for r600.
503   if (EnableFunctionCalls &&
504       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
505     EnableFunctionCalls = false;
506 }
507 
508 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
509   const Function &F) const {
510   StringRef GPU = getGPUName(F);
511   StringRef FS = getFeatureString(F);
512 
513   SmallString<128> SubtargetKey(GPU);
514   SubtargetKey.append(FS);
515 
516   auto &I = SubtargetMap[SubtargetKey];
517   if (!I) {
518     // This needs to be done before we create a new subtarget since any
519     // creation will depend on the TM and the code generation flags on the
520     // function that reside in TargetOptions.
521     resetTargetOptions(F);
522     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
523   }
524 
525   return I.get();
526 }
527 
528 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
529                                               unsigned DestAS) const {
530   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
531          AMDGPU::isFlatGlobalAddrSpace(DestAS);
532 }
533 
534 TargetTransformInfo
535 R600TargetMachine::getTargetTransformInfo(const Function &F) {
536   return TargetTransformInfo(R600TTIImpl(this, F));
537 }
538 
539 //===----------------------------------------------------------------------===//
540 // GCN Target Machine (SI+)
541 //===----------------------------------------------------------------------===//
542 
543 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
544                                    StringRef CPU, StringRef FS,
545                                    TargetOptions Options,
546                                    Optional<Reloc::Model> RM,
547                                    Optional<CodeModel::Model> CM,
548                                    CodeGenOpt::Level OL, bool JIT)
549     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
550 
551 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
552   StringRef GPU = getGPUName(F);
553   StringRef FS = getFeatureString(F);
554 
555   SmallString<128> SubtargetKey(GPU);
556   SubtargetKey.append(FS);
557 
558   auto &I = SubtargetMap[SubtargetKey];
559   if (!I) {
560     // This needs to be done before we create a new subtarget since any
561     // creation will depend on the TM and the code generation flags on the
562     // function that reside in TargetOptions.
563     resetTargetOptions(F);
564     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
565   }
566 
567   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
568 
569   return I.get();
570 }
571 
572 TargetTransformInfo
573 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
574   return TargetTransformInfo(GCNTTIImpl(this, F));
575 }
576 
577 //===----------------------------------------------------------------------===//
578 // AMDGPU Pass Setup
579 //===----------------------------------------------------------------------===//
580 
581 namespace {
582 
583 class AMDGPUPassConfig : public TargetPassConfig {
584 public:
585   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
586     : TargetPassConfig(TM, PM) {
587     // Exceptions and StackMaps are not supported, so these passes will never do
588     // anything.
589     disablePass(&StackMapLivenessID);
590     disablePass(&FuncletLayoutID);
591   }
592 
593   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
594     return getTM<AMDGPUTargetMachine>();
595   }
596 
597   ScheduleDAGInstrs *
598   createMachineScheduler(MachineSchedContext *C) const override {
599     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
600     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
601     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
602     return DAG;
603   }
604 
605   void addEarlyCSEOrGVNPass();
606   void addStraightLineScalarOptimizationPasses();
607   void addIRPasses() override;
608   void addCodeGenPrepare() override;
609   bool addPreISel() override;
610   bool addInstSelector() override;
611   bool addGCPasses() override;
612 
613   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
614 };
615 
616 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
617   return getStandardCSEConfigForOpt(TM->getOptLevel());
618 }
619 
620 class R600PassConfig final : public AMDGPUPassConfig {
621 public:
622   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
623     : AMDGPUPassConfig(TM, PM) {}
624 
625   ScheduleDAGInstrs *createMachineScheduler(
626     MachineSchedContext *C) const override {
627     return createR600MachineScheduler(C);
628   }
629 
630   bool addPreISel() override;
631   bool addInstSelector() override;
632   void addPreRegAlloc() override;
633   void addPreSched2() override;
634   void addPreEmitPass() override;
635 };
636 
637 class GCNPassConfig final : public AMDGPUPassConfig {
638 public:
639   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
640     : AMDGPUPassConfig(TM, PM) {
641     // It is necessary to know the register usage of the entire call graph.  We
642     // allow calls without EnableAMDGPUFunctionCalls if they are marked
643     // noinline, so this is always required.
644     setRequiresCodeGenSCCOrder(true);
645   }
646 
647   GCNTargetMachine &getGCNTargetMachine() const {
648     return getTM<GCNTargetMachine>();
649   }
650 
651   ScheduleDAGInstrs *
652   createMachineScheduler(MachineSchedContext *C) const override;
653 
654   bool addPreISel() override;
655   void addMachineSSAOptimization() override;
656   bool addILPOpts() override;
657   bool addInstSelector() override;
658   bool addIRTranslator() override;
659   void addPreLegalizeMachineIR() override;
660   bool addLegalizeMachineIR() override;
661   void addPreRegBankSelect() override;
662   bool addRegBankSelect() override;
663   bool addGlobalInstructionSelect() override;
664   void addFastRegAlloc() override;
665   void addOptimizedRegAlloc() override;
666   void addPreRegAlloc() override;
667   bool addPreRewrite() override;
668   void addPostRegAlloc() override;
669   void addPreSched2() override;
670   void addPreEmitPass() override;
671 };
672 
673 } // end anonymous namespace
674 
675 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
676   if (getOptLevel() == CodeGenOpt::Aggressive)
677     addPass(createGVNPass());
678   else
679     addPass(createEarlyCSEPass());
680 }
681 
682 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
683   addPass(createLICMPass());
684   addPass(createSeparateConstOffsetFromGEPPass());
685   addPass(createSpeculativeExecutionPass());
686   // ReassociateGEPs exposes more opportunites for SLSR. See
687   // the example in reassociate-geps-and-slsr.ll.
688   addPass(createStraightLineStrengthReducePass());
689   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
690   // EarlyCSE can reuse.
691   addEarlyCSEOrGVNPass();
692   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
693   addPass(createNaryReassociatePass());
694   // NaryReassociate on GEPs creates redundant common expressions, so run
695   // EarlyCSE after it.
696   addPass(createEarlyCSEPass());
697 }
698 
699 void AMDGPUPassConfig::addIRPasses() {
700   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
701 
702   // There is no reason to run these.
703   disablePass(&StackMapLivenessID);
704   disablePass(&FuncletLayoutID);
705   disablePass(&PatchableFunctionID);
706 
707   addPass(createAMDGPUPrintfRuntimeBinding());
708 
709   // This must occur before inlining, as the inliner will not look through
710   // bitcast calls.
711   addPass(createAMDGPUFixFunctionBitcastsPass());
712 
713   // A call to propagate attributes pass in the backend in case opt was not run.
714   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
715 
716   addPass(createAtomicExpandPass());
717 
718 
719   addPass(createAMDGPULowerIntrinsicsPass());
720 
721   // Function calls are not supported, so make sure we inline everything.
722   addPass(createAMDGPUAlwaysInlinePass());
723   addPass(createAlwaysInlinerLegacyPass());
724   // We need to add the barrier noop pass, otherwise adding the function
725   // inlining pass will cause all of the PassConfigs passes to be run
726   // one function at a time, which means if we have a nodule with two
727   // functions, then we will generate code for the first function
728   // without ever running any passes on the second.
729   addPass(createBarrierNoopPass());
730 
731   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
732   if (TM.getTargetTriple().getArch() == Triple::r600)
733     addPass(createR600OpenCLImageTypeLoweringPass());
734 
735   // Replace OpenCL enqueued block function pointers with global variables.
736   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
737 
738   if (TM.getOptLevel() > CodeGenOpt::None) {
739     addPass(createInferAddressSpacesPass());
740     addPass(createAMDGPUPromoteAlloca());
741 
742     if (EnableSROA)
743       addPass(createSROAPass());
744 
745     if (EnableScalarIRPasses)
746       addStraightLineScalarOptimizationPasses();
747 
748     if (EnableAMDGPUAliasAnalysis) {
749       addPass(createAMDGPUAAWrapperPass());
750       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
751                                              AAResults &AAR) {
752         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
753           AAR.addAAResult(WrapperPass->getResult());
754         }));
755     }
756   }
757 
758   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
759     // TODO: May want to move later or split into an early and late one.
760     addPass(createAMDGPUCodeGenPreparePass());
761   }
762 
763   TargetPassConfig::addIRPasses();
764 
765   // EarlyCSE is not always strong enough to clean up what LSR produces. For
766   // example, GVN can combine
767   //
768   //   %0 = add %a, %b
769   //   %1 = add %b, %a
770   //
771   // and
772   //
773   //   %0 = shl nsw %a, 2
774   //   %1 = shl %a, 2
775   //
776   // but EarlyCSE can do neither of them.
777   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
778     addEarlyCSEOrGVNPass();
779 }
780 
781 void AMDGPUPassConfig::addCodeGenPrepare() {
782   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
783     addPass(createAMDGPUAnnotateKernelFeaturesPass());
784 
785   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
786       EnableLowerKernelArguments)
787     addPass(createAMDGPULowerKernelArgumentsPass());
788 
789   addPass(&AMDGPUPerfHintAnalysisID);
790 
791   TargetPassConfig::addCodeGenPrepare();
792 
793   if (EnableLoadStoreVectorizer)
794     addPass(createLoadStoreVectorizerPass());
795 
796   // LowerSwitch pass may introduce unreachable blocks that can
797   // cause unexpected behavior for subsequent passes. Placing it
798   // here seems better that these blocks would get cleaned up by
799   // UnreachableBlockElim inserted next in the pass flow.
800   addPass(createLowerSwitchPass());
801 }
802 
803 bool AMDGPUPassConfig::addPreISel() {
804   addPass(createFlattenCFGPass());
805   return false;
806 }
807 
808 bool AMDGPUPassConfig::addInstSelector() {
809   // Defer the verifier until FinalizeISel.
810   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
811   return false;
812 }
813 
814 bool AMDGPUPassConfig::addGCPasses() {
815   // Do nothing. GC is not supported.
816   return false;
817 }
818 
819 //===----------------------------------------------------------------------===//
820 // R600 Pass Setup
821 //===----------------------------------------------------------------------===//
822 
823 bool R600PassConfig::addPreISel() {
824   AMDGPUPassConfig::addPreISel();
825 
826   if (EnableR600StructurizeCFG)
827     addPass(createStructurizeCFGPass());
828   return false;
829 }
830 
831 bool R600PassConfig::addInstSelector() {
832   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
833   return false;
834 }
835 
836 void R600PassConfig::addPreRegAlloc() {
837   addPass(createR600VectorRegMerger());
838 }
839 
840 void R600PassConfig::addPreSched2() {
841   addPass(createR600EmitClauseMarkers(), false);
842   if (EnableR600IfConvert)
843     addPass(&IfConverterID, false);
844   addPass(createR600ClauseMergePass(), false);
845 }
846 
847 void R600PassConfig::addPreEmitPass() {
848   addPass(createAMDGPUCFGStructurizerPass(), false);
849   addPass(createR600ExpandSpecialInstrsPass(), false);
850   addPass(&FinalizeMachineBundlesID, false);
851   addPass(createR600Packetizer(), false);
852   addPass(createR600ControlFlowFinalizer(), false);
853 }
854 
855 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
856   return new R600PassConfig(*this, PM);
857 }
858 
859 //===----------------------------------------------------------------------===//
860 // GCN Pass Setup
861 //===----------------------------------------------------------------------===//
862 
863 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
864   MachineSchedContext *C) const {
865   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
866   if (ST.enableSIScheduler())
867     return createSIMachineScheduler(C);
868   return createGCNMaxOccupancyMachineScheduler(C);
869 }
870 
871 bool GCNPassConfig::addPreISel() {
872   AMDGPUPassConfig::addPreISel();
873 
874   if (EnableAtomicOptimizations) {
875     addPass(createAMDGPUAtomicOptimizerPass());
876   }
877 
878   // FIXME: We need to run a pass to propagate the attributes when calls are
879   // supported.
880 
881   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
882   // regions formed by them.
883   addPass(&AMDGPUUnifyDivergentExitNodesID);
884   if (!LateCFGStructurize) {
885     if (EnableStructurizerWorkarounds) {
886       addPass(createFixIrreduciblePass());
887       addPass(createUnifyLoopExitsPass());
888     }
889     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
890   }
891   addPass(createSinkingPass());
892   addPass(createAMDGPUAnnotateUniformValues());
893   if (!LateCFGStructurize) {
894     addPass(createSIAnnotateControlFlowPass());
895   }
896   addPass(createLCSSAPass());
897 
898   return false;
899 }
900 
901 void GCNPassConfig::addMachineSSAOptimization() {
902   TargetPassConfig::addMachineSSAOptimization();
903 
904   // We want to fold operands after PeepholeOptimizer has run (or as part of
905   // it), because it will eliminate extra copies making it easier to fold the
906   // real source operand. We want to eliminate dead instructions after, so that
907   // we see fewer uses of the copies. We then need to clean up the dead
908   // instructions leftover after the operands are folded as well.
909   //
910   // XXX - Can we get away without running DeadMachineInstructionElim again?
911   addPass(&SIFoldOperandsID);
912   if (EnableDPPCombine)
913     addPass(&GCNDPPCombineID);
914   addPass(&DeadMachineInstructionElimID);
915   addPass(&SILoadStoreOptimizerID);
916   if (EnableSDWAPeephole) {
917     addPass(&SIPeepholeSDWAID);
918     addPass(&EarlyMachineLICMID);
919     addPass(&MachineCSEID);
920     addPass(&SIFoldOperandsID);
921     addPass(&DeadMachineInstructionElimID);
922   }
923   addPass(createSIShrinkInstructionsPass());
924 }
925 
926 bool GCNPassConfig::addILPOpts() {
927   if (EnableEarlyIfConversion)
928     addPass(&EarlyIfConverterID);
929 
930   TargetPassConfig::addILPOpts();
931   return false;
932 }
933 
934 bool GCNPassConfig::addInstSelector() {
935   AMDGPUPassConfig::addInstSelector();
936   addPass(&SIFixSGPRCopiesID);
937   addPass(createSILowerI1CopiesPass());
938   addPass(createSIAddIMGInitPass());
939   return false;
940 }
941 
942 bool GCNPassConfig::addIRTranslator() {
943   addPass(new IRTranslator());
944   return false;
945 }
946 
947 void GCNPassConfig::addPreLegalizeMachineIR() {
948   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
949   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
950   addPass(new Localizer());
951 }
952 
953 bool GCNPassConfig::addLegalizeMachineIR() {
954   addPass(new Legalizer());
955   return false;
956 }
957 
958 void GCNPassConfig::addPreRegBankSelect() {
959   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
960   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
961 }
962 
963 bool GCNPassConfig::addRegBankSelect() {
964   addPass(new RegBankSelect());
965   return false;
966 }
967 
968 bool GCNPassConfig::addGlobalInstructionSelect() {
969   addPass(new InstructionSelect());
970   return false;
971 }
972 
973 void GCNPassConfig::addPreRegAlloc() {
974   if (LateCFGStructurize) {
975     addPass(createAMDGPUMachineCFGStructurizerPass());
976   }
977   addPass(createSIWholeQuadModePass());
978 }
979 
980 void GCNPassConfig::addFastRegAlloc() {
981   // FIXME: We have to disable the verifier here because of PHIElimination +
982   // TwoAddressInstructions disabling it.
983 
984   // This must be run immediately after phi elimination and before
985   // TwoAddressInstructions, otherwise the processing of the tied operand of
986   // SI_ELSE will introduce a copy of the tied operand source after the else.
987   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
988 
989   // This must be run just after RegisterCoalescing.
990   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
991 
992   TargetPassConfig::addFastRegAlloc();
993 }
994 
995 void GCNPassConfig::addOptimizedRegAlloc() {
996   if (OptExecMaskPreRA)
997     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
998   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
999 
1000   // This must be run immediately after phi elimination and before
1001   // TwoAddressInstructions, otherwise the processing of the tied operand of
1002   // SI_ELSE will introduce a copy of the tied operand source after the else.
1003   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1004 
1005   // This must be run just after RegisterCoalescing.
1006   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
1007 
1008   if (EnableDCEInRA)
1009     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1010 
1011   TargetPassConfig::addOptimizedRegAlloc();
1012 }
1013 
1014 bool GCNPassConfig::addPreRewrite() {
1015   if (EnableRegReassign) {
1016     addPass(&GCNNSAReassignID);
1017     addPass(&GCNRegBankReassignID);
1018   }
1019   return true;
1020 }
1021 
1022 void GCNPassConfig::addPostRegAlloc() {
1023   addPass(&SIFixVGPRCopiesID);
1024   if (getOptLevel() > CodeGenOpt::None)
1025     addPass(&SIOptimizeExecMaskingID);
1026   TargetPassConfig::addPostRegAlloc();
1027 
1028   // Equivalent of PEI for SGPRs.
1029   addPass(&SILowerSGPRSpillsID);
1030 }
1031 
1032 void GCNPassConfig::addPreSched2() {
1033   addPass(&SIPostRABundlerID);
1034 }
1035 
1036 void GCNPassConfig::addPreEmitPass() {
1037   addPass(createSIMemoryLegalizerPass());
1038   addPass(createSIInsertWaitcntsPass());
1039   addPass(createSIShrinkInstructionsPass());
1040   addPass(createSIModeRegisterPass());
1041 
1042   // The hazard recognizer that runs as part of the post-ra scheduler does not
1043   // guarantee to be able handle all hazards correctly. This is because if there
1044   // are multiple scheduling regions in a basic block, the regions are scheduled
1045   // bottom up, so when we begin to schedule a region we don't know what
1046   // instructions were emitted directly before it.
1047   //
1048   // Here we add a stand-alone hazard recognizer pass which can handle all
1049   // cases.
1050   //
1051   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
1052   // be better for it to emit S_NOP <N> when possible.
1053   addPass(&PostRAHazardRecognizerID);
1054   if (getOptLevel() > CodeGenOpt::None)
1055     addPass(&SIInsertHardClausesID);
1056 
1057   addPass(&SIRemoveShortExecBranchesID);
1058   addPass(&SIInsertSkipsPassID);
1059   addPass(&SIPreEmitPeepholeID);
1060   addPass(&BranchRelaxationPassID);
1061 }
1062 
1063 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1064   return new GCNPassConfig(*this, PM);
1065 }
1066 
1067 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1068   return new yaml::SIMachineFunctionInfo();
1069 }
1070 
1071 yaml::MachineFunctionInfo *
1072 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1073   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1074   return new yaml::SIMachineFunctionInfo(*MFI,
1075                                          *MF.getSubtarget().getRegisterInfo());
1076 }
1077 
1078 bool GCNTargetMachine::parseMachineFunctionInfo(
1079     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1080     SMDiagnostic &Error, SMRange &SourceRange) const {
1081   const yaml::SIMachineFunctionInfo &YamlMFI =
1082       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1083   MachineFunction &MF = PFS.MF;
1084   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1085 
1086   MFI->initializeBaseYamlFields(YamlMFI);
1087 
1088   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1089     Register TempReg;
1090     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1091       SourceRange = RegName.SourceRange;
1092       return true;
1093     }
1094     RegVal = TempReg;
1095 
1096     return false;
1097   };
1098 
1099   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1100     // Create a diagnostic for a the register string literal.
1101     const MemoryBuffer &Buffer =
1102         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1103     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1104                          RegName.Value.size(), SourceMgr::DK_Error,
1105                          "incorrect register class for field", RegName.Value,
1106                          None, None);
1107     SourceRange = RegName.SourceRange;
1108     return true;
1109   };
1110 
1111   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1112       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1113       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1114     return true;
1115 
1116   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1117       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1118     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1119   }
1120 
1121   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1122       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1123     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1124   }
1125 
1126   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1127       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1128     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1129   }
1130 
1131   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1132                                    const TargetRegisterClass &RC,
1133                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1134                                    unsigned SystemSGPRs) {
1135     // Skip parsing if it's not present.
1136     if (!A)
1137       return false;
1138 
1139     if (A->IsRegister) {
1140       Register Reg;
1141       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1142         SourceRange = A->RegisterName.SourceRange;
1143         return true;
1144       }
1145       if (!RC.contains(Reg))
1146         return diagnoseRegisterClass(A->RegisterName);
1147       Arg = ArgDescriptor::createRegister(Reg);
1148     } else
1149       Arg = ArgDescriptor::createStack(A->StackOffset);
1150     // Check and apply the optional mask.
1151     if (A->Mask)
1152       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1153 
1154     MFI->NumUserSGPRs += UserSGPRs;
1155     MFI->NumSystemSGPRs += SystemSGPRs;
1156     return false;
1157   };
1158 
1159   if (YamlMFI.ArgInfo &&
1160       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1161                              AMDGPU::SGPR_128RegClass,
1162                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1163        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1164                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1165                              2, 0) ||
1166        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1167                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1168        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1169                              AMDGPU::SReg_64RegClass,
1170                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1171        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1172                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1173                              2, 0) ||
1174        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1175                              AMDGPU::SReg_64RegClass,
1176                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1177        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1178                              AMDGPU::SGPR_32RegClass,
1179                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1180        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1181                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1182                              0, 1) ||
1183        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1184                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1185                              0, 1) ||
1186        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1187                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1188                              0, 1) ||
1189        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1190                              AMDGPU::SGPR_32RegClass,
1191                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1192        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1193                              AMDGPU::SGPR_32RegClass,
1194                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1195        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1196                              AMDGPU::SReg_64RegClass,
1197                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1198        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1199                              AMDGPU::SReg_64RegClass,
1200                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1201        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1202                              AMDGPU::VGPR_32RegClass,
1203                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1204        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1205                              AMDGPU::VGPR_32RegClass,
1206                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1207        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1208                              AMDGPU::VGPR_32RegClass,
1209                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1210     return true;
1211 
1212   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1213   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1214   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1215   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1216   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1217   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1218 
1219   return false;
1220 }
1221