1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600MachineScheduler.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIMachineScheduler.h"
27 #include "TargetInfo/AMDGPUTargetInfo.h"
28 #include "llvm/Analysis/CGSCCPassManager.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/Localizer.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MIRParser/MIParser.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/LegacyPassManager.h"
37 #include "llvm/IR/PassManager.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/Passes/PassBuilder.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Transforms/IPO.h"
42 #include "llvm/Transforms/IPO/AlwaysInliner.h"
43 #include "llvm/Transforms/IPO/GlobalDCE.h"
44 #include "llvm/Transforms/IPO/Internalize.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
49 #include "llvm/Transforms/Utils.h"
50 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
51 #include "llvm/Transforms/Vectorize.h"
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73             cl::desc("Run pre-RA exec mask optimizations"),
74             cl::init(true));
75 
76 static cl::opt<bool> EnableR600IfConvert(
77   "r600-if-convert",
78   cl::desc("Use if conversion pass"),
79   cl::ReallyHidden,
80   cl::init(true));
81 
82 // Option to disable vectorizer for tests.
83 static cl::opt<bool> EnableLoadStoreVectorizer(
84   "amdgpu-load-store-vectorizer",
85   cl::desc("Enable load store vectorizer"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to control global loads scalarization
90 static cl::opt<bool> ScalarizeGlobal(
91   "amdgpu-scalarize-global-loads",
92   cl::desc("Enable global load scalarization"),
93   cl::init(true),
94   cl::Hidden);
95 
96 // Option to run internalize pass.
97 static cl::opt<bool> InternalizeSymbols(
98   "amdgpu-internalize-symbols",
99   cl::desc("Enable elimination of non-kernel functions and unused globals"),
100   cl::init(false),
101   cl::Hidden);
102 
103 // Option to inline all early.
104 static cl::opt<bool> EarlyInlineAll(
105   "amdgpu-early-inline-all",
106   cl::desc("Inline all functions early"),
107   cl::init(false),
108   cl::Hidden);
109 
110 static cl::opt<bool> EnableSDWAPeephole(
111   "amdgpu-sdwa-peephole",
112   cl::desc("Enable SDWA peepholer"),
113   cl::init(true));
114 
115 static cl::opt<bool> EnableDPPCombine(
116   "amdgpu-dpp-combine",
117   cl::desc("Enable DPP combiner"),
118   cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122   cl::desc("Enable AMDGPU Alias Analysis"),
123   cl::init(true));
124 
125 // Option to run late CFG structurizer
126 static cl::opt<bool, true> LateCFGStructurize(
127   "amdgpu-late-structurize",
128   cl::desc("Enable late CFG structurization"),
129   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
130   cl::Hidden);
131 
132 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
133   "amdgpu-function-calls",
134   cl::desc("Enable AMDGPU function call support"),
135   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
136   cl::init(true),
137   cl::Hidden);
138 
139 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
140   "amdgpu-fixed-function-abi",
141   cl::desc("Enable all implicit function arguments"),
142   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
143   cl::init(false),
144   cl::Hidden);
145 
146 // Enable lib calls simplifications
147 static cl::opt<bool> EnableLibCallSimplify(
148   "amdgpu-simplify-libcall",
149   cl::desc("Enable amdgpu library simplifications"),
150   cl::init(true),
151   cl::Hidden);
152 
153 static cl::opt<bool> EnableLowerKernelArguments(
154   "amdgpu-ir-lower-kernel-arguments",
155   cl::desc("Lower kernel argument loads in IR pass"),
156   cl::init(true),
157   cl::Hidden);
158 
159 static cl::opt<bool> EnableRegReassign(
160   "amdgpu-reassign-regs",
161   cl::desc("Enable register reassign optimizations on gfx10+"),
162   cl::init(true),
163   cl::Hidden);
164 
165 // Enable atomic optimization
166 static cl::opt<bool> EnableAtomicOptimizations(
167   "amdgpu-atomic-optimizations",
168   cl::desc("Enable atomic optimizations"),
169   cl::init(false),
170   cl::Hidden);
171 
172 // Enable Mode register optimization
173 static cl::opt<bool> EnableSIModeRegisterPass(
174   "amdgpu-mode-register",
175   cl::desc("Enable mode register pass"),
176   cl::init(true),
177   cl::Hidden);
178 
179 // Option is used in lit tests to prevent deadcoding of patterns inspected.
180 static cl::opt<bool>
181 EnableDCEInRA("amdgpu-dce-in-ra",
182     cl::init(true), cl::Hidden,
183     cl::desc("Enable machine DCE inside regalloc"));
184 
185 static cl::opt<bool> EnableScalarIRPasses(
186   "amdgpu-scalar-ir-passes",
187   cl::desc("Enable scalar IR passes"),
188   cl::init(true),
189   cl::Hidden);
190 
191 static cl::opt<bool> EnableStructurizerWorkarounds(
192     "amdgpu-enable-structurizer-workarounds",
193     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
194     cl::Hidden);
195 
196 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
197   // Register the target
198   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
199   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
200 
201   PassRegistry *PR = PassRegistry::getPassRegistry();
202   initializeR600ClauseMergePassPass(*PR);
203   initializeR600ControlFlowFinalizerPass(*PR);
204   initializeR600PacketizerPass(*PR);
205   initializeR600ExpandSpecialInstrsPassPass(*PR);
206   initializeR600VectorRegMergerPass(*PR);
207   initializeGlobalISel(*PR);
208   initializeAMDGPUDAGToDAGISelPass(*PR);
209   initializeGCNDPPCombinePass(*PR);
210   initializeSILowerI1CopiesPass(*PR);
211   initializeSILowerSGPRSpillsPass(*PR);
212   initializeSIFixSGPRCopiesPass(*PR);
213   initializeSIFixVGPRCopiesPass(*PR);
214   initializeSIFoldOperandsPass(*PR);
215   initializeSIPeepholeSDWAPass(*PR);
216   initializeSIShrinkInstructionsPass(*PR);
217   initializeSIOptimizeExecMaskingPreRAPass(*PR);
218   initializeSILoadStoreOptimizerPass(*PR);
219   initializeAMDGPUFixFunctionBitcastsPass(*PR);
220   initializeAMDGPUAlwaysInlinePass(*PR);
221   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
222   initializeAMDGPUAnnotateUniformValuesPass(*PR);
223   initializeAMDGPUArgumentUsageInfoPass(*PR);
224   initializeAMDGPUAtomicOptimizerPass(*PR);
225   initializeAMDGPULowerKernelArgumentsPass(*PR);
226   initializeAMDGPULowerKernelAttributesPass(*PR);
227   initializeAMDGPULowerIntrinsicsPass(*PR);
228   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
229   initializeAMDGPUPostLegalizerCombinerPass(*PR);
230   initializeAMDGPUPreLegalizerCombinerPass(*PR);
231   initializeAMDGPUPromoteAllocaPass(*PR);
232   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
233   initializeAMDGPUCodeGenPreparePass(*PR);
234   initializeAMDGPULateCodeGenPreparePass(*PR);
235   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
236   initializeAMDGPUPropagateAttributesLatePass(*PR);
237   initializeAMDGPURewriteOutArgumentsPass(*PR);
238   initializeAMDGPUUnifyMetadataPass(*PR);
239   initializeSIAnnotateControlFlowPass(*PR);
240   initializeSIInsertHardClausesPass(*PR);
241   initializeSIInsertWaitcntsPass(*PR);
242   initializeSIModeRegisterPass(*PR);
243   initializeSIWholeQuadModePass(*PR);
244   initializeSILowerControlFlowPass(*PR);
245   initializeSIRemoveShortExecBranchesPass(*PR);
246   initializeSIPreEmitPeepholePass(*PR);
247   initializeSIInsertSkipsPass(*PR);
248   initializeSIMemoryLegalizerPass(*PR);
249   initializeSIOptimizeExecMaskingPass(*PR);
250   initializeSIPreAllocateWWMRegsPass(*PR);
251   initializeSIFormMemoryClausesPass(*PR);
252   initializeSIPostRABundlerPass(*PR);
253   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
254   initializeAMDGPUAAWrapperPassPass(*PR);
255   initializeAMDGPUExternalAAWrapperPass(*PR);
256   initializeAMDGPUUseNativeCallsPass(*PR);
257   initializeAMDGPUSimplifyLibCallsPass(*PR);
258   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
259   initializeGCNRegBankReassignPass(*PR);
260   initializeGCNNSAReassignPass(*PR);
261   initializeSIAddIMGInitPass(*PR);
262 }
263 
264 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
265   return std::make_unique<AMDGPUTargetObjectFile>();
266 }
267 
268 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
269   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
270 }
271 
272 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
273   return new SIScheduleDAGMI(C);
274 }
275 
276 static ScheduleDAGInstrs *
277 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
278   ScheduleDAGMILive *DAG =
279     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
280   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
281   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
282   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
283   return DAG;
284 }
285 
286 static ScheduleDAGInstrs *
287 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
288   auto DAG = new GCNIterativeScheduler(C,
289     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
290   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
291   return DAG;
292 }
293 
294 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
295   return new GCNIterativeScheduler(C,
296     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
297 }
298 
299 static ScheduleDAGInstrs *
300 createIterativeILPMachineScheduler(MachineSchedContext *C) {
301   auto DAG = new GCNIterativeScheduler(C,
302     GCNIterativeScheduler::SCHEDULE_ILP);
303   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
304   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
305   return DAG;
306 }
307 
308 static MachineSchedRegistry
309 R600SchedRegistry("r600", "Run R600's custom scheduler",
310                    createR600MachineScheduler);
311 
312 static MachineSchedRegistry
313 SISchedRegistry("si", "Run SI's custom scheduler",
314                 createSIMachineScheduler);
315 
316 static MachineSchedRegistry
317 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
318                              "Run GCN scheduler to maximize occupancy",
319                              createGCNMaxOccupancyMachineScheduler);
320 
321 static MachineSchedRegistry
322 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
323   "Run GCN scheduler to maximize occupancy (experimental)",
324   createIterativeGCNMaxOccupancyMachineScheduler);
325 
326 static MachineSchedRegistry
327 GCNMinRegSchedRegistry("gcn-minreg",
328   "Run GCN iterative scheduler for minimal register usage (experimental)",
329   createMinRegScheduler);
330 
331 static MachineSchedRegistry
332 GCNILPSchedRegistry("gcn-ilp",
333   "Run GCN iterative scheduler for ILP scheduling (experimental)",
334   createIterativeILPMachineScheduler);
335 
336 static StringRef computeDataLayout(const Triple &TT) {
337   if (TT.getArch() == Triple::r600) {
338     // 32-bit pointers.
339     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
340            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
341   }
342 
343   // 32-bit private, local, and region pointers. 64-bit global, constant and
344   // flat, non-integral buffer fat pointers.
345   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
346          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
347          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
348          "-ni:7";
349 }
350 
351 LLVM_READNONE
352 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
353   if (!GPU.empty())
354     return GPU;
355 
356   // Need to default to a target with flat support for HSA.
357   if (TT.getArch() == Triple::amdgcn)
358     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
359 
360   return "r600";
361 }
362 
363 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
364   // The AMDGPU toolchain only supports generating shared objects, so we
365   // must always use PIC.
366   return Reloc::PIC_;
367 }
368 
369 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
370                                          StringRef CPU, StringRef FS,
371                                          TargetOptions Options,
372                                          Optional<Reloc::Model> RM,
373                                          Optional<CodeModel::Model> CM,
374                                          CodeGenOpt::Level OptLevel)
375     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
376                         FS, Options, getEffectiveRelocModel(RM),
377                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
378       TLOF(createTLOF(getTargetTriple())) {
379   initAsmInfo();
380   if (TT.getArch() == Triple::amdgcn) {
381     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
382       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
383     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
384       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
385   }
386   // Set -fixed-function-abi to true if not provided..
387   if (TT.getOS() == Triple::AMDHSA &&
388       EnableAMDGPUFixedFunctionABIOpt.getNumOccurrences() == 0)
389     EnableFixedFunctionABI = true;
390 }
391 
392 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
393 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
394 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
395 
396 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
397 
398 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
399   Attribute GPUAttr = F.getFnAttribute("target-cpu");
400   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
401 }
402 
403 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
404   Attribute FSAttr = F.getFnAttribute("target-features");
405 
406   return FSAttr.isValid() ? FSAttr.getValueAsString()
407                           : getTargetFeatureString();
408 }
409 
410 /// Predicate for Internalize pass.
411 static bool mustPreserveGV(const GlobalValue &GV) {
412   if (const Function *F = dyn_cast<Function>(&GV))
413     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
414 
415   return !GV.use_empty();
416 }
417 
418 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
419   Builder.DivergentTarget = true;
420 
421   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
422   bool Internalize = InternalizeSymbols;
423   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
424   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
425   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
426 
427   if (EnableFunctionCalls) {
428     delete Builder.Inliner;
429     Builder.Inliner = createFunctionInliningPass();
430   }
431 
432   Builder.addExtension(
433     PassManagerBuilder::EP_ModuleOptimizerEarly,
434     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
435                                                legacy::PassManagerBase &PM) {
436       if (AMDGPUAA) {
437         PM.add(createAMDGPUAAWrapperPass());
438         PM.add(createAMDGPUExternalAAWrapperPass());
439       }
440       PM.add(createAMDGPUUnifyMetadataPass());
441       PM.add(createAMDGPUPrintfRuntimeBinding());
442       if (Internalize)
443         PM.add(createInternalizePass(mustPreserveGV));
444       PM.add(createAMDGPUPropagateAttributesLatePass(this));
445       if (Internalize)
446         PM.add(createGlobalDCEPass());
447       if (EarlyInline)
448         PM.add(createAMDGPUAlwaysInlinePass(false));
449   });
450 
451   Builder.addExtension(
452     PassManagerBuilder::EP_EarlyAsPossible,
453     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
454                                       legacy::PassManagerBase &PM) {
455       if (AMDGPUAA) {
456         PM.add(createAMDGPUAAWrapperPass());
457         PM.add(createAMDGPUExternalAAWrapperPass());
458       }
459       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
460       PM.add(llvm::createAMDGPUUseNativeCallsPass());
461       if (LibCallSimplify)
462         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
463   });
464 
465   Builder.addExtension(
466     PassManagerBuilder::EP_CGSCCOptimizerLate,
467     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
468       // Add infer address spaces pass to the opt pipeline after inlining
469       // but before SROA to increase SROA opportunities.
470       PM.add(createInferAddressSpacesPass());
471 
472       // This should run after inlining to have any chance of doing anything,
473       // and before other cleanup optimizations.
474       PM.add(createAMDGPULowerKernelAttributesPass());
475 
476       // Promote alloca to vector before SROA and loop unroll. If we manage
477       // to eliminate allocas before unroll we may choose to unroll less.
478       if (EnableOpt)
479         PM.add(createAMDGPUPromoteAllocaToVector());
480   });
481 }
482 
483 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
484   AAM.registerFunctionAnalysis<AMDGPUAA>();
485 }
486 
487 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
488                                                        bool DebugPassManager) {
489   PB.registerPipelineParsingCallback(
490       [this](StringRef PassName, ModulePassManager &PM,
491              ArrayRef<PassBuilder::PipelineElement>) {
492         if (PassName == "amdgpu-propagate-attributes-late") {
493           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
494           return true;
495         }
496         if (PassName == "amdgpu-unify-metadata") {
497           PM.addPass(AMDGPUUnifyMetadataPass());
498           return true;
499         }
500         if (PassName == "amdgpu-printf-runtime-binding") {
501           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
502           return true;
503         }
504         if (PassName == "amdgpu-always-inline") {
505           PM.addPass(AMDGPUAlwaysInlinePass());
506           return true;
507         }
508         return false;
509       });
510   PB.registerPipelineParsingCallback(
511       [this](StringRef PassName, FunctionPassManager &PM,
512              ArrayRef<PassBuilder::PipelineElement>) {
513         if (PassName == "amdgpu-simplifylib") {
514           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
515           return true;
516         }
517         if (PassName == "amdgpu-usenative") {
518           PM.addPass(AMDGPUUseNativeCallsPass());
519           return true;
520         }
521         if (PassName == "amdgpu-promote-alloca") {
522           PM.addPass(AMDGPUPromoteAllocaPass(*this));
523           return true;
524         }
525         if (PassName == "amdgpu-promote-alloca-to-vector") {
526           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
527           return true;
528         }
529         if (PassName == "amdgpu-lower-kernel-attributes") {
530           PM.addPass(AMDGPULowerKernelAttributesPass());
531           return true;
532         }
533         if (PassName == "amdgpu-propagate-attributes-early") {
534           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
535           return true;
536         }
537 
538         return false;
539       });
540 
541   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
542     FAM.registerPass([&] { return AMDGPUAA(); });
543   });
544 
545   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
546     if (AAName == "amdgpu-aa") {
547       AAM.registerFunctionAnalysis<AMDGPUAA>();
548       return true;
549     }
550     return false;
551   });
552 
553   PB.registerPipelineStartEPCallback([this, DebugPassManager](
554                                          ModulePassManager &PM,
555                                          PassBuilder::OptimizationLevel Level) {
556     FunctionPassManager FPM(DebugPassManager);
557     FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
558     FPM.addPass(AMDGPUUseNativeCallsPass());
559     if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
560       FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
561     PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
562   });
563 
564   PB.registerPipelineEarlySimplificationEPCallback(
565       [this](ModulePassManager &PM, PassBuilder::OptimizationLevel Level) {
566         if (Level == PassBuilder::OptimizationLevel::O0)
567           return;
568 
569         PM.addPass(AMDGPUUnifyMetadataPass());
570         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
571 
572         if (InternalizeSymbols) {
573           PM.addPass(InternalizePass(mustPreserveGV));
574         }
575         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
576         if (InternalizeSymbols) {
577           PM.addPass(GlobalDCEPass());
578         }
579         if (EarlyInlineAll && !EnableFunctionCalls)
580           PM.addPass(AMDGPUAlwaysInlinePass());
581       });
582 
583   PB.registerCGSCCOptimizerLateEPCallback(
584       [this, DebugPassManager](CGSCCPassManager &PM,
585                                PassBuilder::OptimizationLevel Level) {
586         if (Level == PassBuilder::OptimizationLevel::O0)
587           return;
588 
589         FunctionPassManager FPM(DebugPassManager);
590 
591         // Add infer address spaces pass to the opt pipeline after inlining
592         // but before SROA to increase SROA opportunities.
593         FPM.addPass(InferAddressSpacesPass());
594 
595         // This should run after inlining to have any chance of doing
596         // anything, and before other cleanup optimizations.
597         FPM.addPass(AMDGPULowerKernelAttributesPass());
598 
599         if (Level != PassBuilder::OptimizationLevel::O0) {
600           // Promote alloca to vector before SROA and loop unroll. If we
601           // manage to eliminate allocas before unroll we may choose to unroll
602           // less.
603           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
604         }
605 
606         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
607       });
608 }
609 
610 //===----------------------------------------------------------------------===//
611 // R600 Target Machine (R600 -> Cayman)
612 //===----------------------------------------------------------------------===//
613 
614 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
615                                      StringRef CPU, StringRef FS,
616                                      TargetOptions Options,
617                                      Optional<Reloc::Model> RM,
618                                      Optional<CodeModel::Model> CM,
619                                      CodeGenOpt::Level OL, bool JIT)
620     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
621   setRequiresStructuredCFG(true);
622 
623   // Override the default since calls aren't supported for r600.
624   if (EnableFunctionCalls &&
625       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
626     EnableFunctionCalls = false;
627 }
628 
629 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
630   const Function &F) const {
631   StringRef GPU = getGPUName(F);
632   StringRef FS = getFeatureString(F);
633 
634   SmallString<128> SubtargetKey(GPU);
635   SubtargetKey.append(FS);
636 
637   auto &I = SubtargetMap[SubtargetKey];
638   if (!I) {
639     // This needs to be done before we create a new subtarget since any
640     // creation will depend on the TM and the code generation flags on the
641     // function that reside in TargetOptions.
642     resetTargetOptions(F);
643     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
644   }
645 
646   return I.get();
647 }
648 
649 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
650   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
651           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
652           AddrSpace == AMDGPUAS::REGION_ADDRESS)
653              ? -1
654              : 0;
655 }
656 
657 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
658                                               unsigned DestAS) const {
659   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
660          AMDGPU::isFlatGlobalAddrSpace(DestAS);
661 }
662 
663 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
664   const auto *LD = dyn_cast<LoadInst>(V);
665   if (!LD)
666     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
667 
668   // It must be a generic pointer loaded.
669   assert(V->getType()->isPointerTy() &&
670          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
671 
672   const auto *Ptr = LD->getPointerOperand();
673   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
674     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
675   // For a generic pointer loaded from the constant memory, it could be assumed
676   // as a global pointer since the constant memory is only populated on the
677   // host side. As implied by the offload programming model, only global
678   // pointers could be referenced on the host side.
679   return AMDGPUAS::GLOBAL_ADDRESS;
680 }
681 
682 TargetTransformInfo
683 R600TargetMachine::getTargetTransformInfo(const Function &F) {
684   return TargetTransformInfo(R600TTIImpl(this, F));
685 }
686 
687 //===----------------------------------------------------------------------===//
688 // GCN Target Machine (SI+)
689 //===----------------------------------------------------------------------===//
690 
691 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
692                                    StringRef CPU, StringRef FS,
693                                    TargetOptions Options,
694                                    Optional<Reloc::Model> RM,
695                                    Optional<CodeModel::Model> CM,
696                                    CodeGenOpt::Level OL, bool JIT)
697     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
698 
699 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
700   StringRef GPU = getGPUName(F);
701   StringRef FS = getFeatureString(F);
702 
703   SmallString<128> SubtargetKey(GPU);
704   SubtargetKey.append(FS);
705 
706   auto &I = SubtargetMap[SubtargetKey];
707   if (!I) {
708     // This needs to be done before we create a new subtarget since any
709     // creation will depend on the TM and the code generation flags on the
710     // function that reside in TargetOptions.
711     resetTargetOptions(F);
712     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
713   }
714 
715   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
716 
717   return I.get();
718 }
719 
720 TargetTransformInfo
721 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
722   return TargetTransformInfo(GCNTTIImpl(this, F));
723 }
724 
725 //===----------------------------------------------------------------------===//
726 // AMDGPU Pass Setup
727 //===----------------------------------------------------------------------===//
728 
729 namespace {
730 
731 class AMDGPUPassConfig : public TargetPassConfig {
732 public:
733   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
734     : TargetPassConfig(TM, PM) {
735     // Exceptions and StackMaps are not supported, so these passes will never do
736     // anything.
737     disablePass(&StackMapLivenessID);
738     disablePass(&FuncletLayoutID);
739   }
740 
741   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
742     return getTM<AMDGPUTargetMachine>();
743   }
744 
745   ScheduleDAGInstrs *
746   createMachineScheduler(MachineSchedContext *C) const override {
747     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
748     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
749     return DAG;
750   }
751 
752   void addEarlyCSEOrGVNPass();
753   void addStraightLineScalarOptimizationPasses();
754   void addIRPasses() override;
755   void addCodeGenPrepare() override;
756   bool addPreISel() override;
757   bool addInstSelector() override;
758   bool addGCPasses() override;
759 
760   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
761 };
762 
763 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
764   return getStandardCSEConfigForOpt(TM->getOptLevel());
765 }
766 
767 class R600PassConfig final : public AMDGPUPassConfig {
768 public:
769   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
770     : AMDGPUPassConfig(TM, PM) {}
771 
772   ScheduleDAGInstrs *createMachineScheduler(
773     MachineSchedContext *C) const override {
774     return createR600MachineScheduler(C);
775   }
776 
777   bool addPreISel() override;
778   bool addInstSelector() override;
779   void addPreRegAlloc() override;
780   void addPreSched2() override;
781   void addPreEmitPass() override;
782 };
783 
784 class GCNPassConfig final : public AMDGPUPassConfig {
785 public:
786   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
787     : AMDGPUPassConfig(TM, PM) {
788     // It is necessary to know the register usage of the entire call graph.  We
789     // allow calls without EnableAMDGPUFunctionCalls if they are marked
790     // noinline, so this is always required.
791     setRequiresCodeGenSCCOrder(true);
792   }
793 
794   GCNTargetMachine &getGCNTargetMachine() const {
795     return getTM<GCNTargetMachine>();
796   }
797 
798   ScheduleDAGInstrs *
799   createMachineScheduler(MachineSchedContext *C) const override;
800 
801   bool addPreISel() override;
802   void addMachineSSAOptimization() override;
803   bool addILPOpts() override;
804   bool addInstSelector() override;
805   bool addIRTranslator() override;
806   void addPreLegalizeMachineIR() override;
807   bool addLegalizeMachineIR() override;
808   void addPreRegBankSelect() override;
809   bool addRegBankSelect() override;
810   bool addGlobalInstructionSelect() override;
811   void addFastRegAlloc() override;
812   void addOptimizedRegAlloc() override;
813   void addPreRegAlloc() override;
814   bool addPreRewrite() override;
815   void addPostRegAlloc() override;
816   void addPreSched2() override;
817   void addPreEmitPass() override;
818 };
819 
820 } // end anonymous namespace
821 
822 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
823   if (getOptLevel() == CodeGenOpt::Aggressive)
824     addPass(createGVNPass());
825   else
826     addPass(createEarlyCSEPass());
827 }
828 
829 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
830   addPass(createLICMPass());
831   addPass(createSeparateConstOffsetFromGEPPass());
832   addPass(createSpeculativeExecutionPass());
833   // ReassociateGEPs exposes more opportunites for SLSR. See
834   // the example in reassociate-geps-and-slsr.ll.
835   addPass(createStraightLineStrengthReducePass());
836   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
837   // EarlyCSE can reuse.
838   addEarlyCSEOrGVNPass();
839   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
840   addPass(createNaryReassociatePass());
841   // NaryReassociate on GEPs creates redundant common expressions, so run
842   // EarlyCSE after it.
843   addPass(createEarlyCSEPass());
844 }
845 
846 void AMDGPUPassConfig::addIRPasses() {
847   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
848 
849   // There is no reason to run these.
850   disablePass(&StackMapLivenessID);
851   disablePass(&FuncletLayoutID);
852   disablePass(&PatchableFunctionID);
853 
854   addPass(createAMDGPUPrintfRuntimeBinding());
855 
856   // This must occur before inlining, as the inliner will not look through
857   // bitcast calls.
858   addPass(createAMDGPUFixFunctionBitcastsPass());
859 
860   // A call to propagate attributes pass in the backend in case opt was not run.
861   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
862 
863   addPass(createAtomicExpandPass());
864 
865 
866   addPass(createAMDGPULowerIntrinsicsPass());
867 
868   // Function calls are not supported, so make sure we inline everything.
869   addPass(createAMDGPUAlwaysInlinePass());
870   addPass(createAlwaysInlinerLegacyPass());
871   // We need to add the barrier noop pass, otherwise adding the function
872   // inlining pass will cause all of the PassConfigs passes to be run
873   // one function at a time, which means if we have a nodule with two
874   // functions, then we will generate code for the first function
875   // without ever running any passes on the second.
876   addPass(createBarrierNoopPass());
877 
878   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
879   if (TM.getTargetTriple().getArch() == Triple::r600)
880     addPass(createR600OpenCLImageTypeLoweringPass());
881 
882   // Replace OpenCL enqueued block function pointers with global variables.
883   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
884 
885   if (TM.getOptLevel() > CodeGenOpt::None) {
886     addPass(createInferAddressSpacesPass());
887     addPass(createAMDGPUPromoteAlloca());
888 
889     if (EnableSROA)
890       addPass(createSROAPass());
891 
892     if (EnableScalarIRPasses)
893       addStraightLineScalarOptimizationPasses();
894 
895     if (EnableAMDGPUAliasAnalysis) {
896       addPass(createAMDGPUAAWrapperPass());
897       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
898                                              AAResults &AAR) {
899         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
900           AAR.addAAResult(WrapperPass->getResult());
901         }));
902     }
903   }
904 
905   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
906     // TODO: May want to move later or split into an early and late one.
907     addPass(createAMDGPUCodeGenPreparePass());
908   }
909 
910   TargetPassConfig::addIRPasses();
911 
912   // EarlyCSE is not always strong enough to clean up what LSR produces. For
913   // example, GVN can combine
914   //
915   //   %0 = add %a, %b
916   //   %1 = add %b, %a
917   //
918   // and
919   //
920   //   %0 = shl nsw %a, 2
921   //   %1 = shl %a, 2
922   //
923   // but EarlyCSE can do neither of them.
924   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
925     addEarlyCSEOrGVNPass();
926 }
927 
928 void AMDGPUPassConfig::addCodeGenPrepare() {
929   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
930     addPass(createAMDGPUAnnotateKernelFeaturesPass());
931 
932   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
933       EnableLowerKernelArguments)
934     addPass(createAMDGPULowerKernelArgumentsPass());
935 
936   addPass(&AMDGPUPerfHintAnalysisID);
937 
938   TargetPassConfig::addCodeGenPrepare();
939 
940   if (EnableLoadStoreVectorizer)
941     addPass(createLoadStoreVectorizerPass());
942 
943   // LowerSwitch pass may introduce unreachable blocks that can
944   // cause unexpected behavior for subsequent passes. Placing it
945   // here seems better that these blocks would get cleaned up by
946   // UnreachableBlockElim inserted next in the pass flow.
947   addPass(createLowerSwitchPass());
948 }
949 
950 bool AMDGPUPassConfig::addPreISel() {
951   addPass(createFlattenCFGPass());
952   return false;
953 }
954 
955 bool AMDGPUPassConfig::addInstSelector() {
956   // Defer the verifier until FinalizeISel.
957   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
958   return false;
959 }
960 
961 bool AMDGPUPassConfig::addGCPasses() {
962   // Do nothing. GC is not supported.
963   return false;
964 }
965 
966 //===----------------------------------------------------------------------===//
967 // R600 Pass Setup
968 //===----------------------------------------------------------------------===//
969 
970 bool R600PassConfig::addPreISel() {
971   AMDGPUPassConfig::addPreISel();
972 
973   if (EnableR600StructurizeCFG)
974     addPass(createStructurizeCFGPass());
975   return false;
976 }
977 
978 bool R600PassConfig::addInstSelector() {
979   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
980   return false;
981 }
982 
983 void R600PassConfig::addPreRegAlloc() {
984   addPass(createR600VectorRegMerger());
985 }
986 
987 void R600PassConfig::addPreSched2() {
988   addPass(createR600EmitClauseMarkers(), false);
989   if (EnableR600IfConvert)
990     addPass(&IfConverterID, false);
991   addPass(createR600ClauseMergePass(), false);
992 }
993 
994 void R600PassConfig::addPreEmitPass() {
995   addPass(createAMDGPUCFGStructurizerPass(), false);
996   addPass(createR600ExpandSpecialInstrsPass(), false);
997   addPass(&FinalizeMachineBundlesID, false);
998   addPass(createR600Packetizer(), false);
999   addPass(createR600ControlFlowFinalizer(), false);
1000 }
1001 
1002 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
1003   return new R600PassConfig(*this, PM);
1004 }
1005 
1006 //===----------------------------------------------------------------------===//
1007 // GCN Pass Setup
1008 //===----------------------------------------------------------------------===//
1009 
1010 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1011   MachineSchedContext *C) const {
1012   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1013   if (ST.enableSIScheduler())
1014     return createSIMachineScheduler(C);
1015   return createGCNMaxOccupancyMachineScheduler(C);
1016 }
1017 
1018 bool GCNPassConfig::addPreISel() {
1019   AMDGPUPassConfig::addPreISel();
1020 
1021   addPass(createAMDGPULateCodeGenPreparePass());
1022   if (EnableAtomicOptimizations) {
1023     addPass(createAMDGPUAtomicOptimizerPass());
1024   }
1025 
1026   // FIXME: We need to run a pass to propagate the attributes when calls are
1027   // supported.
1028 
1029   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1030   // regions formed by them.
1031   addPass(&AMDGPUUnifyDivergentExitNodesID);
1032   if (!LateCFGStructurize) {
1033     if (EnableStructurizerWorkarounds) {
1034       addPass(createFixIrreduciblePass());
1035       addPass(createUnifyLoopExitsPass());
1036     }
1037     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1038   }
1039   addPass(createSinkingPass());
1040   addPass(createAMDGPUAnnotateUniformValues());
1041   if (!LateCFGStructurize) {
1042     addPass(createSIAnnotateControlFlowPass());
1043   }
1044   addPass(createLCSSAPass());
1045 
1046   return false;
1047 }
1048 
1049 void GCNPassConfig::addMachineSSAOptimization() {
1050   TargetPassConfig::addMachineSSAOptimization();
1051 
1052   // We want to fold operands after PeepholeOptimizer has run (or as part of
1053   // it), because it will eliminate extra copies making it easier to fold the
1054   // real source operand. We want to eliminate dead instructions after, so that
1055   // we see fewer uses of the copies. We then need to clean up the dead
1056   // instructions leftover after the operands are folded as well.
1057   //
1058   // XXX - Can we get away without running DeadMachineInstructionElim again?
1059   addPass(&SIFoldOperandsID);
1060   if (EnableDPPCombine)
1061     addPass(&GCNDPPCombineID);
1062   addPass(&DeadMachineInstructionElimID);
1063   addPass(&SILoadStoreOptimizerID);
1064   if (EnableSDWAPeephole) {
1065     addPass(&SIPeepholeSDWAID);
1066     addPass(&EarlyMachineLICMID);
1067     addPass(&MachineCSEID);
1068     addPass(&SIFoldOperandsID);
1069     addPass(&DeadMachineInstructionElimID);
1070   }
1071   addPass(createSIShrinkInstructionsPass());
1072 }
1073 
1074 bool GCNPassConfig::addILPOpts() {
1075   if (EnableEarlyIfConversion)
1076     addPass(&EarlyIfConverterID);
1077 
1078   TargetPassConfig::addILPOpts();
1079   return false;
1080 }
1081 
1082 bool GCNPassConfig::addInstSelector() {
1083   AMDGPUPassConfig::addInstSelector();
1084   addPass(&SIFixSGPRCopiesID);
1085   addPass(createSILowerI1CopiesPass());
1086   addPass(createSIAddIMGInitPass());
1087   return false;
1088 }
1089 
1090 bool GCNPassConfig::addIRTranslator() {
1091   addPass(new IRTranslator(getOptLevel()));
1092   return false;
1093 }
1094 
1095 void GCNPassConfig::addPreLegalizeMachineIR() {
1096   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1097   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1098   addPass(new Localizer());
1099 }
1100 
1101 bool GCNPassConfig::addLegalizeMachineIR() {
1102   addPass(new Legalizer());
1103   return false;
1104 }
1105 
1106 void GCNPassConfig::addPreRegBankSelect() {
1107   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1108   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1109 }
1110 
1111 bool GCNPassConfig::addRegBankSelect() {
1112   addPass(new RegBankSelect());
1113   return false;
1114 }
1115 
1116 bool GCNPassConfig::addGlobalInstructionSelect() {
1117   addPass(new InstructionSelect(getOptLevel()));
1118   // TODO: Fix instruction selection to do the right thing for image
1119   // instructions with tfe or lwe in the first place, instead of running a
1120   // separate pass to fix them up?
1121   addPass(createSIAddIMGInitPass());
1122   return false;
1123 }
1124 
1125 void GCNPassConfig::addPreRegAlloc() {
1126   if (LateCFGStructurize) {
1127     addPass(createAMDGPUMachineCFGStructurizerPass());
1128   }
1129 }
1130 
1131 void GCNPassConfig::addFastRegAlloc() {
1132   // FIXME: We have to disable the verifier here because of PHIElimination +
1133   // TwoAddressInstructions disabling it.
1134 
1135   // This must be run immediately after phi elimination and before
1136   // TwoAddressInstructions, otherwise the processing of the tied operand of
1137   // SI_ELSE will introduce a copy of the tied operand source after the else.
1138   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1139 
1140   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1141   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1142 
1143   TargetPassConfig::addFastRegAlloc();
1144 }
1145 
1146 void GCNPassConfig::addOptimizedRegAlloc() {
1147   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1148   // instructions that cause scheduling barriers.
1149   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1150   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1151 
1152   if (OptExecMaskPreRA)
1153     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1154   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1155 
1156   // This must be run immediately after phi elimination and before
1157   // TwoAddressInstructions, otherwise the processing of the tied operand of
1158   // SI_ELSE will introduce a copy of the tied operand source after the else.
1159   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1160 
1161   if (EnableDCEInRA)
1162     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1163 
1164   TargetPassConfig::addOptimizedRegAlloc();
1165 }
1166 
1167 bool GCNPassConfig::addPreRewrite() {
1168   if (EnableRegReassign) {
1169     addPass(&GCNNSAReassignID);
1170     addPass(&GCNRegBankReassignID);
1171   }
1172   return true;
1173 }
1174 
1175 void GCNPassConfig::addPostRegAlloc() {
1176   addPass(&SIFixVGPRCopiesID);
1177   if (getOptLevel() > CodeGenOpt::None)
1178     addPass(&SIOptimizeExecMaskingID);
1179   TargetPassConfig::addPostRegAlloc();
1180 
1181   // Equivalent of PEI for SGPRs.
1182   addPass(&SILowerSGPRSpillsID);
1183 }
1184 
1185 void GCNPassConfig::addPreSched2() {
1186   addPass(&SIPostRABundlerID);
1187 }
1188 
1189 void GCNPassConfig::addPreEmitPass() {
1190   addPass(createSIMemoryLegalizerPass());
1191   addPass(createSIInsertWaitcntsPass());
1192   addPass(createSIShrinkInstructionsPass());
1193   addPass(createSIModeRegisterPass());
1194 
1195   if (getOptLevel() > CodeGenOpt::None)
1196     addPass(&SIInsertHardClausesID);
1197 
1198   addPass(&SIRemoveShortExecBranchesID);
1199   addPass(&SIInsertSkipsPassID);
1200   addPass(&SIPreEmitPeepholeID);
1201   // The hazard recognizer that runs as part of the post-ra scheduler does not
1202   // guarantee to be able handle all hazards correctly. This is because if there
1203   // are multiple scheduling regions in a basic block, the regions are scheduled
1204   // bottom up, so when we begin to schedule a region we don't know what
1205   // instructions were emitted directly before it.
1206   //
1207   // Here we add a stand-alone hazard recognizer pass which can handle all
1208   // cases.
1209   addPass(&PostRAHazardRecognizerID);
1210   addPass(&BranchRelaxationPassID);
1211 }
1212 
1213 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1214   return new GCNPassConfig(*this, PM);
1215 }
1216 
1217 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1218   return new yaml::SIMachineFunctionInfo();
1219 }
1220 
1221 yaml::MachineFunctionInfo *
1222 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1223   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1224   return new yaml::SIMachineFunctionInfo(*MFI,
1225                                          *MF.getSubtarget().getRegisterInfo());
1226 }
1227 
1228 bool GCNTargetMachine::parseMachineFunctionInfo(
1229     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1230     SMDiagnostic &Error, SMRange &SourceRange) const {
1231   const yaml::SIMachineFunctionInfo &YamlMFI =
1232       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1233   MachineFunction &MF = PFS.MF;
1234   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1235 
1236   MFI->initializeBaseYamlFields(YamlMFI);
1237 
1238   if (MFI->Occupancy == 0) {
1239     // Fixup the subtarget dependent default value.
1240     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1241     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1242   }
1243 
1244   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1245     Register TempReg;
1246     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1247       SourceRange = RegName.SourceRange;
1248       return true;
1249     }
1250     RegVal = TempReg;
1251 
1252     return false;
1253   };
1254 
1255   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1256     // Create a diagnostic for a the register string literal.
1257     const MemoryBuffer &Buffer =
1258         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1259     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1260                          RegName.Value.size(), SourceMgr::DK_Error,
1261                          "incorrect register class for field", RegName.Value,
1262                          None, None);
1263     SourceRange = RegName.SourceRange;
1264     return true;
1265   };
1266 
1267   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1268       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1269       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1270     return true;
1271 
1272   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1273       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1274     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1275   }
1276 
1277   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1278       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1279     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1280   }
1281 
1282   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1283       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1284     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1285   }
1286 
1287   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1288                                    const TargetRegisterClass &RC,
1289                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1290                                    unsigned SystemSGPRs) {
1291     // Skip parsing if it's not present.
1292     if (!A)
1293       return false;
1294 
1295     if (A->IsRegister) {
1296       Register Reg;
1297       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1298         SourceRange = A->RegisterName.SourceRange;
1299         return true;
1300       }
1301       if (!RC.contains(Reg))
1302         return diagnoseRegisterClass(A->RegisterName);
1303       Arg = ArgDescriptor::createRegister(Reg);
1304     } else
1305       Arg = ArgDescriptor::createStack(A->StackOffset);
1306     // Check and apply the optional mask.
1307     if (A->Mask)
1308       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1309 
1310     MFI->NumUserSGPRs += UserSGPRs;
1311     MFI->NumSystemSGPRs += SystemSGPRs;
1312     return false;
1313   };
1314 
1315   if (YamlMFI.ArgInfo &&
1316       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1317                              AMDGPU::SGPR_128RegClass,
1318                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1319        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1320                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1321                              2, 0) ||
1322        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1323                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1324        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1325                              AMDGPU::SReg_64RegClass,
1326                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1327        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1328                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1329                              2, 0) ||
1330        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1331                              AMDGPU::SReg_64RegClass,
1332                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1333        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1334                              AMDGPU::SGPR_32RegClass,
1335                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1336        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1337                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1338                              0, 1) ||
1339        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1340                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1341                              0, 1) ||
1342        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1343                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1344                              0, 1) ||
1345        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1346                              AMDGPU::SGPR_32RegClass,
1347                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1348        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1349                              AMDGPU::SGPR_32RegClass,
1350                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1351        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1352                              AMDGPU::SReg_64RegClass,
1353                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1354        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1355                              AMDGPU::SReg_64RegClass,
1356                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1357        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1358                              AMDGPU::VGPR_32RegClass,
1359                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1360        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1361                              AMDGPU::VGPR_32RegClass,
1362                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1363        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1364                              AMDGPU::VGPR_32RegClass,
1365                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1366     return true;
1367 
1368   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1369   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1370   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1371   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1372   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1373   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1374 
1375   return false;
1376 }
1377