1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110   cl::desc("Enable AMDGPU Alias Analysis"),
111   cl::init(true));
112 
113 // Option to enable new waitcnt insertion pass.
114 static cl::opt<bool> EnableSIInsertWaitcntsPass(
115   "enable-si-insert-waitcnts",
116   cl::desc("Use new waitcnt insertion pass"),
117   cl::init(true));
118 
119 // Option to run late CFG structurizer
120 static cl::opt<bool, true> LateCFGStructurize(
121   "amdgpu-late-structurize",
122   cl::desc("Enable late CFG structurization"),
123   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
124   cl::Hidden);
125 
126 static cl::opt<bool> EnableAMDGPUFunctionCalls(
127   "amdgpu-function-calls",
128   cl::Hidden,
129   cl::desc("Enable AMDGPU function call support"),
130   cl::init(false));
131 
132 // Enable lib calls simplifications
133 static cl::opt<bool> EnableLibCallSimplify(
134   "amdgpu-simplify-libcall",
135   cl::desc("Enable mdgpu library simplifications"),
136   cl::init(true),
137   cl::Hidden);
138 
139 extern "C" void LLVMInitializeAMDGPUTarget() {
140   // Register the target
141   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
142   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
143 
144   PassRegistry *PR = PassRegistry::getPassRegistry();
145   initializeR600ClauseMergePassPass(*PR);
146   initializeR600ControlFlowFinalizerPass(*PR);
147   initializeR600PacketizerPass(*PR);
148   initializeR600ExpandSpecialInstrsPassPass(*PR);
149   initializeR600VectorRegMergerPass(*PR);
150   initializeAMDGPUDAGToDAGISelPass(*PR);
151   initializeSILowerI1CopiesPass(*PR);
152   initializeSIFixSGPRCopiesPass(*PR);
153   initializeSIFixVGPRCopiesPass(*PR);
154   initializeSIFoldOperandsPass(*PR);
155   initializeSIPeepholeSDWAPass(*PR);
156   initializeSIShrinkInstructionsPass(*PR);
157   initializeSIOptimizeExecMaskingPreRAPass(*PR);
158   initializeSILoadStoreOptimizerPass(*PR);
159   initializeAMDGPUAlwaysInlinePass(*PR);
160   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
161   initializeAMDGPUAnnotateUniformValuesPass(*PR);
162   initializeAMDGPUArgumentUsageInfoPass(*PR);
163   initializeAMDGPULowerIntrinsicsPass(*PR);
164   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
165   initializeAMDGPUPromoteAllocaPass(*PR);
166   initializeAMDGPUCodeGenPreparePass(*PR);
167   initializeAMDGPURewriteOutArgumentsPass(*PR);
168   initializeAMDGPUUnifyMetadataPass(*PR);
169   initializeSIAnnotateControlFlowPass(*PR);
170   initializeSIInsertWaitsPass(*PR);
171   initializeSIInsertWaitcntsPass(*PR);
172   initializeSIWholeQuadModePass(*PR);
173   initializeSILowerControlFlowPass(*PR);
174   initializeSIInsertSkipsPass(*PR);
175   initializeSIMemoryLegalizerPass(*PR);
176   initializeSIDebuggerInsertNopsPass(*PR);
177   initializeSIOptimizeExecMaskingPass(*PR);
178   initializeSIFixWWMLivenessPass(*PR);
179   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
180   initializeAMDGPUAAWrapperPassPass(*PR);
181   initializeAMDGPUUseNativeCallsPass(*PR);
182   initializeAMDGPUSimplifyLibCallsPass(*PR);
183   initializeAMDGPUInlinerPass(*PR);
184 }
185 
186 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
187   return llvm::make_unique<AMDGPUTargetObjectFile>();
188 }
189 
190 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
191   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
192 }
193 
194 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
195   return new SIScheduleDAGMI(C);
196 }
197 
198 static ScheduleDAGInstrs *
199 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
200   ScheduleDAGMILive *DAG =
201     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
202   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
203   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
204   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
205   return DAG;
206 }
207 
208 static ScheduleDAGInstrs *
209 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
210   auto DAG = new GCNIterativeScheduler(C,
211     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
212   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
213   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
214   return DAG;
215 }
216 
217 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
218   return new GCNIterativeScheduler(C,
219     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
220 }
221 
222 static MachineSchedRegistry
223 R600SchedRegistry("r600", "Run R600's custom scheduler",
224                    createR600MachineScheduler);
225 
226 static MachineSchedRegistry
227 SISchedRegistry("si", "Run SI's custom scheduler",
228                 createSIMachineScheduler);
229 
230 static MachineSchedRegistry
231 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
232                              "Run GCN scheduler to maximize occupancy",
233                              createGCNMaxOccupancyMachineScheduler);
234 
235 static MachineSchedRegistry
236 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
237   "Run GCN scheduler to maximize occupancy (experimental)",
238   createIterativeGCNMaxOccupancyMachineScheduler);
239 
240 static MachineSchedRegistry
241 GCNMinRegSchedRegistry("gcn-minreg",
242   "Run GCN iterative scheduler for minimal register usage (experimental)",
243   createMinRegScheduler);
244 
245 static StringRef computeDataLayout(const Triple &TT) {
246   if (TT.getArch() == Triple::r600) {
247     // 32-bit pointers.
248     if (TT.getEnvironmentName() == "amdgiz" ||
249         TT.getEnvironmentName() == "amdgizcl")
250       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
251              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
252     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
253             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
254   }
255 
256   // 32-bit private, local, and region pointers. 64-bit global, constant and
257   // flat.
258   if (TT.getEnvironmentName() == "amdgiz" ||
259       TT.getEnvironmentName() == "amdgizcl")
260     return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
261          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
262          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
263   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
264       "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
265       "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
266 }
267 
268 LLVM_READNONE
269 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
270   if (!GPU.empty())
271     return GPU;
272 
273   if (TT.getArch() == Triple::amdgcn)
274     return "generic";
275 
276   return "r600";
277 }
278 
279 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
280   // The AMDGPU toolchain only supports generating shared objects, so we
281   // must always use PIC.
282   return Reloc::PIC_;
283 }
284 
285 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
286   if (CM)
287     return *CM;
288   return CodeModel::Small;
289 }
290 
291 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
292                                          StringRef CPU, StringRef FS,
293                                          TargetOptions Options,
294                                          Optional<Reloc::Model> RM,
295                                          Optional<CodeModel::Model> CM,
296                                          CodeGenOpt::Level OptLevel)
297     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
298                         FS, Options, getEffectiveRelocModel(RM),
299                         getEffectiveCodeModel(CM), OptLevel),
300       TLOF(createTLOF(getTargetTriple())) {
301   AS = AMDGPU::getAMDGPUAS(TT);
302   initAsmInfo();
303 }
304 
305 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
306 
307 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
308 
309 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
310   Attribute GPUAttr = F.getFnAttribute("target-cpu");
311   return GPUAttr.hasAttribute(Attribute::None) ?
312     getTargetCPU() : GPUAttr.getValueAsString();
313 }
314 
315 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
316   Attribute FSAttr = F.getFnAttribute("target-features");
317 
318   return FSAttr.hasAttribute(Attribute::None) ?
319     getTargetFeatureString() :
320     FSAttr.getValueAsString();
321 }
322 
323 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
324   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
325       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
326         AAR.addAAResult(WrapperPass->getResult());
327       });
328 }
329 
330 /// Predicate for Internalize pass.
331 static bool mustPreserveGV(const GlobalValue &GV) {
332   if (const Function *F = dyn_cast<Function>(&GV))
333     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
334 
335   return !GV.use_empty();
336 }
337 
338 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
339   Builder.DivergentTarget = true;
340 
341   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
342   bool Internalize = InternalizeSymbols;
343   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
344   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
345   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
346 
347   if (EnableAMDGPUFunctionCalls) {
348     delete Builder.Inliner;
349     Builder.Inliner = createAMDGPUFunctionInliningPass();
350   }
351 
352   if (Internalize) {
353     // If we're generating code, we always have the whole program available. The
354     // relocations expected for externally visible functions aren't supported,
355     // so make sure every non-entry function is hidden.
356     Builder.addExtension(
357       PassManagerBuilder::EP_EnabledOnOptLevel0,
358       [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
359         PM.add(createInternalizePass(mustPreserveGV));
360       });
361   }
362 
363   Builder.addExtension(
364     PassManagerBuilder::EP_ModuleOptimizerEarly,
365     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
366                                          legacy::PassManagerBase &PM) {
367       if (AMDGPUAA) {
368         PM.add(createAMDGPUAAWrapperPass());
369         PM.add(createAMDGPUExternalAAWrapperPass());
370       }
371       PM.add(createAMDGPUUnifyMetadataPass());
372       if (Internalize) {
373         PM.add(createInternalizePass(mustPreserveGV));
374         PM.add(createGlobalDCEPass());
375       }
376       if (EarlyInline)
377         PM.add(createAMDGPUAlwaysInlinePass(false));
378   });
379 
380   const auto &Opt = Options;
381   Builder.addExtension(
382     PassManagerBuilder::EP_EarlyAsPossible,
383     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
384                                       legacy::PassManagerBase &PM) {
385       if (AMDGPUAA) {
386         PM.add(createAMDGPUAAWrapperPass());
387         PM.add(createAMDGPUExternalAAWrapperPass());
388       }
389       PM.add(llvm::createAMDGPUUseNativeCallsPass());
390       if (LibCallSimplify)
391         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
392   });
393 
394   Builder.addExtension(
395     PassManagerBuilder::EP_CGSCCOptimizerLate,
396     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
397       // Add infer address spaces pass to the opt pipeline after inlining
398       // but before SROA to increase SROA opportunities.
399       PM.add(createInferAddressSpacesPass());
400   });
401 }
402 
403 //===----------------------------------------------------------------------===//
404 // R600 Target Machine (R600 -> Cayman)
405 //===----------------------------------------------------------------------===//
406 
407 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
408                                      StringRef CPU, StringRef FS,
409                                      TargetOptions Options,
410                                      Optional<Reloc::Model> RM,
411                                      Optional<CodeModel::Model> CM,
412                                      CodeGenOpt::Level OL, bool JIT)
413     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
414   setRequiresStructuredCFG(true);
415 }
416 
417 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
418   const Function &F) const {
419   StringRef GPU = getGPUName(F);
420   StringRef FS = getFeatureString(F);
421 
422   SmallString<128> SubtargetKey(GPU);
423   SubtargetKey.append(FS);
424 
425   auto &I = SubtargetMap[SubtargetKey];
426   if (!I) {
427     // This needs to be done before we create a new subtarget since any
428     // creation will depend on the TM and the code generation flags on the
429     // function that reside in TargetOptions.
430     resetTargetOptions(F);
431     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
432   }
433 
434   return I.get();
435 }
436 
437 //===----------------------------------------------------------------------===//
438 // GCN Target Machine (SI+)
439 //===----------------------------------------------------------------------===//
440 
441 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
442                                    StringRef CPU, StringRef FS,
443                                    TargetOptions Options,
444                                    Optional<Reloc::Model> RM,
445                                    Optional<CodeModel::Model> CM,
446                                    CodeGenOpt::Level OL, bool JIT)
447     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
448 
449 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
450   StringRef GPU = getGPUName(F);
451   StringRef FS = getFeatureString(F);
452 
453   SmallString<128> SubtargetKey(GPU);
454   SubtargetKey.append(FS);
455 
456   auto &I = SubtargetMap[SubtargetKey];
457   if (!I) {
458     // This needs to be done before we create a new subtarget since any
459     // creation will depend on the TM and the code generation flags on the
460     // function that reside in TargetOptions.
461     resetTargetOptions(F);
462     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
463   }
464 
465   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
466 
467   return I.get();
468 }
469 
470 //===----------------------------------------------------------------------===//
471 // AMDGPU Pass Setup
472 //===----------------------------------------------------------------------===//
473 
474 namespace {
475 
476 class AMDGPUPassConfig : public TargetPassConfig {
477 public:
478   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
479     : TargetPassConfig(TM, PM) {
480     // Exceptions and StackMaps are not supported, so these passes will never do
481     // anything.
482     disablePass(&StackMapLivenessID);
483     disablePass(&FuncletLayoutID);
484   }
485 
486   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
487     return getTM<AMDGPUTargetMachine>();
488   }
489 
490   ScheduleDAGInstrs *
491   createMachineScheduler(MachineSchedContext *C) const override {
492     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
493     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
494     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
495     return DAG;
496   }
497 
498   void addEarlyCSEOrGVNPass();
499   void addStraightLineScalarOptimizationPasses();
500   void addIRPasses() override;
501   void addCodeGenPrepare() override;
502   bool addPreISel() override;
503   bool addInstSelector() override;
504   bool addGCPasses() override;
505 };
506 
507 class R600PassConfig final : public AMDGPUPassConfig {
508 public:
509   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
510     : AMDGPUPassConfig(TM, PM) {}
511 
512   ScheduleDAGInstrs *createMachineScheduler(
513     MachineSchedContext *C) const override {
514     return createR600MachineScheduler(C);
515   }
516 
517   bool addPreISel() override;
518   bool addInstSelector() override;
519   void addPreRegAlloc() override;
520   void addPreSched2() override;
521   void addPreEmitPass() override;
522 };
523 
524 class GCNPassConfig final : public AMDGPUPassConfig {
525 public:
526   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
527     : AMDGPUPassConfig(TM, PM) {
528     // It is necessary to know the register usage of the entire call graph.  We
529     // allow calls without EnableAMDGPUFunctionCalls if they are marked
530     // noinline, so this is always required.
531     setRequiresCodeGenSCCOrder(true);
532   }
533 
534   GCNTargetMachine &getGCNTargetMachine() const {
535     return getTM<GCNTargetMachine>();
536   }
537 
538   ScheduleDAGInstrs *
539   createMachineScheduler(MachineSchedContext *C) const override;
540 
541   bool addPreISel() override;
542   void addMachineSSAOptimization() override;
543   bool addILPOpts() override;
544   bool addInstSelector() override;
545   bool addIRTranslator() override;
546   bool addLegalizeMachineIR() override;
547   bool addRegBankSelect() override;
548   bool addGlobalInstructionSelect() override;
549   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
550   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
551   void addPreRegAlloc() override;
552   void addPostRegAlloc() override;
553   void addPreSched2() override;
554   void addPreEmitPass() override;
555 };
556 
557 } // end anonymous namespace
558 
559 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
560   return TargetIRAnalysis([this](const Function &F) {
561     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
562   });
563 }
564 
565 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
566   if (getOptLevel() == CodeGenOpt::Aggressive)
567     addPass(createGVNPass());
568   else
569     addPass(createEarlyCSEPass());
570 }
571 
572 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
573   addPass(createSeparateConstOffsetFromGEPPass());
574   addPass(createSpeculativeExecutionPass());
575   // ReassociateGEPs exposes more opportunites for SLSR. See
576   // the example in reassociate-geps-and-slsr.ll.
577   addPass(createStraightLineStrengthReducePass());
578   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
579   // EarlyCSE can reuse.
580   addEarlyCSEOrGVNPass();
581   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
582   addPass(createNaryReassociatePass());
583   // NaryReassociate on GEPs creates redundant common expressions, so run
584   // EarlyCSE after it.
585   addPass(createEarlyCSEPass());
586 }
587 
588 void AMDGPUPassConfig::addIRPasses() {
589   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
590 
591   // There is no reason to run these.
592   disablePass(&StackMapLivenessID);
593   disablePass(&FuncletLayoutID);
594   disablePass(&PatchableFunctionID);
595 
596   addPass(createAMDGPULowerIntrinsicsPass());
597 
598   if (TM.getTargetTriple().getArch() == Triple::r600 ||
599       !EnableAMDGPUFunctionCalls) {
600     // Function calls are not supported, so make sure we inline everything.
601     addPass(createAMDGPUAlwaysInlinePass());
602     addPass(createAlwaysInlinerLegacyPass());
603     // We need to add the barrier noop pass, otherwise adding the function
604     // inlining pass will cause all of the PassConfigs passes to be run
605     // one function at a time, which means if we have a nodule with two
606     // functions, then we will generate code for the first function
607     // without ever running any passes on the second.
608     addPass(createBarrierNoopPass());
609   }
610 
611   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
612     // TODO: May want to move later or split into an early and late one.
613 
614     addPass(createAMDGPUCodeGenPreparePass());
615   }
616 
617   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
618   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
619 
620   // Replace OpenCL enqueued block function pointers with global variables.
621   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
622 
623   if (TM.getOptLevel() > CodeGenOpt::None) {
624     addPass(createInferAddressSpacesPass());
625     addPass(createAMDGPUPromoteAlloca());
626 
627     if (EnableSROA)
628       addPass(createSROAPass());
629 
630     addStraightLineScalarOptimizationPasses();
631 
632     if (EnableAMDGPUAliasAnalysis) {
633       addPass(createAMDGPUAAWrapperPass());
634       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
635                                              AAResults &AAR) {
636         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
637           AAR.addAAResult(WrapperPass->getResult());
638         }));
639     }
640   }
641 
642   TargetPassConfig::addIRPasses();
643 
644   // EarlyCSE is not always strong enough to clean up what LSR produces. For
645   // example, GVN can combine
646   //
647   //   %0 = add %a, %b
648   //   %1 = add %b, %a
649   //
650   // and
651   //
652   //   %0 = shl nsw %a, 2
653   //   %1 = shl %a, 2
654   //
655   // but EarlyCSE can do neither of them.
656   if (getOptLevel() != CodeGenOpt::None)
657     addEarlyCSEOrGVNPass();
658 }
659 
660 void AMDGPUPassConfig::addCodeGenPrepare() {
661   TargetPassConfig::addCodeGenPrepare();
662 
663   if (EnableLoadStoreVectorizer)
664     addPass(createLoadStoreVectorizerPass());
665 }
666 
667 bool AMDGPUPassConfig::addPreISel() {
668   addPass(createFlattenCFGPass());
669   return false;
670 }
671 
672 bool AMDGPUPassConfig::addInstSelector() {
673   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
674   return false;
675 }
676 
677 bool AMDGPUPassConfig::addGCPasses() {
678   // Do nothing. GC is not supported.
679   return false;
680 }
681 
682 //===----------------------------------------------------------------------===//
683 // R600 Pass Setup
684 //===----------------------------------------------------------------------===//
685 
686 bool R600PassConfig::addPreISel() {
687   AMDGPUPassConfig::addPreISel();
688 
689   if (EnableR600StructurizeCFG)
690     addPass(createStructurizeCFGPass());
691   return false;
692 }
693 
694 bool R600PassConfig::addInstSelector() {
695   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
696   return false;
697 }
698 
699 void R600PassConfig::addPreRegAlloc() {
700   addPass(createR600VectorRegMerger());
701 }
702 
703 void R600PassConfig::addPreSched2() {
704   addPass(createR600EmitClauseMarkers(), false);
705   if (EnableR600IfConvert)
706     addPass(&IfConverterID, false);
707   addPass(createR600ClauseMergePass(), false);
708 }
709 
710 void R600PassConfig::addPreEmitPass() {
711   addPass(createAMDGPUCFGStructurizerPass(), false);
712   addPass(createR600ExpandSpecialInstrsPass(), false);
713   addPass(&FinalizeMachineBundlesID, false);
714   addPass(createR600Packetizer(), false);
715   addPass(createR600ControlFlowFinalizer(), false);
716 }
717 
718 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
719   return new R600PassConfig(*this, PM);
720 }
721 
722 //===----------------------------------------------------------------------===//
723 // GCN Pass Setup
724 //===----------------------------------------------------------------------===//
725 
726 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
727   MachineSchedContext *C) const {
728   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
729   if (ST.enableSIScheduler())
730     return createSIMachineScheduler(C);
731   return createGCNMaxOccupancyMachineScheduler(C);
732 }
733 
734 bool GCNPassConfig::addPreISel() {
735   AMDGPUPassConfig::addPreISel();
736 
737   // FIXME: We need to run a pass to propagate the attributes when calls are
738   // supported.
739   addPass(createAMDGPUAnnotateKernelFeaturesPass());
740 
741   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
742   // regions formed by them.
743   addPass(&AMDGPUUnifyDivergentExitNodesID);
744   if (!LateCFGStructurize) {
745     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
746   }
747   addPass(createSinkingPass());
748   addPass(createAMDGPUAnnotateUniformValues());
749   if (!LateCFGStructurize) {
750     addPass(createSIAnnotateControlFlowPass());
751   }
752 
753   return false;
754 }
755 
756 void GCNPassConfig::addMachineSSAOptimization() {
757   TargetPassConfig::addMachineSSAOptimization();
758 
759   // We want to fold operands after PeepholeOptimizer has run (or as part of
760   // it), because it will eliminate extra copies making it easier to fold the
761   // real source operand. We want to eliminate dead instructions after, so that
762   // we see fewer uses of the copies. We then need to clean up the dead
763   // instructions leftover after the operands are folded as well.
764   //
765   // XXX - Can we get away without running DeadMachineInstructionElim again?
766   addPass(&SIFoldOperandsID);
767   addPass(&DeadMachineInstructionElimID);
768   addPass(&SILoadStoreOptimizerID);
769   if (EnableSDWAPeephole) {
770     addPass(&SIPeepholeSDWAID);
771     addPass(&MachineLICMID);
772     addPass(&MachineCSEID);
773     addPass(&SIFoldOperandsID);
774     addPass(&DeadMachineInstructionElimID);
775   }
776   addPass(createSIShrinkInstructionsPass());
777 }
778 
779 bool GCNPassConfig::addILPOpts() {
780   if (EnableEarlyIfConversion)
781     addPass(&EarlyIfConverterID);
782 
783   TargetPassConfig::addILPOpts();
784   return false;
785 }
786 
787 bool GCNPassConfig::addInstSelector() {
788   AMDGPUPassConfig::addInstSelector();
789   addPass(createSILowerI1CopiesPass());
790   addPass(&SIFixSGPRCopiesID);
791   return false;
792 }
793 
794 bool GCNPassConfig::addIRTranslator() {
795   addPass(new IRTranslator());
796   return false;
797 }
798 
799 bool GCNPassConfig::addLegalizeMachineIR() {
800   addPass(new Legalizer());
801   return false;
802 }
803 
804 bool GCNPassConfig::addRegBankSelect() {
805   addPass(new RegBankSelect());
806   return false;
807 }
808 
809 bool GCNPassConfig::addGlobalInstructionSelect() {
810   addPass(new InstructionSelect());
811   return false;
812 }
813 
814 void GCNPassConfig::addPreRegAlloc() {
815   if (LateCFGStructurize) {
816     addPass(createAMDGPUMachineCFGStructurizerPass());
817   }
818   addPass(createSIWholeQuadModePass());
819 }
820 
821 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
822   // FIXME: We have to disable the verifier here because of PHIElimination +
823   // TwoAddressInstructions disabling it.
824 
825   // This must be run immediately after phi elimination and before
826   // TwoAddressInstructions, otherwise the processing of the tied operand of
827   // SI_ELSE will introduce a copy of the tied operand source after the else.
828   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
829 
830   // This must be run after SILowerControlFlow, since it needs to use the
831   // machine-level CFG, but before register allocation.
832   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
833 
834   TargetPassConfig::addFastRegAlloc(RegAllocPass);
835 }
836 
837 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
838   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
839 
840   // This must be run immediately after phi elimination and before
841   // TwoAddressInstructions, otherwise the processing of the tied operand of
842   // SI_ELSE will introduce a copy of the tied operand source after the else.
843   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
844 
845   // This must be run after SILowerControlFlow, since it needs to use the
846   // machine-level CFG, but before register allocation.
847   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
848 
849   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
850 }
851 
852 void GCNPassConfig::addPostRegAlloc() {
853   addPass(&SIFixVGPRCopiesID);
854   addPass(&SIOptimizeExecMaskingID);
855   TargetPassConfig::addPostRegAlloc();
856 }
857 
858 void GCNPassConfig::addPreSched2() {
859 }
860 
861 void GCNPassConfig::addPreEmitPass() {
862   // The hazard recognizer that runs as part of the post-ra scheduler does not
863   // guarantee to be able handle all hazards correctly. This is because if there
864   // are multiple scheduling regions in a basic block, the regions are scheduled
865   // bottom up, so when we begin to schedule a region we don't know what
866   // instructions were emitted directly before it.
867   //
868   // Here we add a stand-alone hazard recognizer pass which can handle all
869   // cases.
870   addPass(&PostRAHazardRecognizerID);
871 
872   if (EnableSIInsertWaitcntsPass)
873     addPass(createSIInsertWaitcntsPass());
874   else
875     addPass(createSIInsertWaitsPass());
876   addPass(createSIShrinkInstructionsPass());
877   addPass(&SIInsertSkipsPassID);
878   addPass(createSIMemoryLegalizerPass());
879   addPass(createSIDebuggerInsertNopsPass());
880   addPass(&BranchRelaxationPassID);
881 }
882 
883 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
884   return new GCNPassConfig(*this, PM);
885 }
886 
887