1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUTargetObjectFile.h"
20 #include "AMDGPUTargetTransformInfo.h"
21 #include "GCNSchedStrategy.h"
22 #include "R600MachineScheduler.h"
23 #include "SIMachineScheduler.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/MachineScheduler.h"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/CodeGen/TargetPassConfig.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Transforms/IPO.h"
35 #include "llvm/Transforms/IPO/AlwaysInliner.h"
36 #include "llvm/Transforms/Scalar.h"
37 #include "llvm/Transforms/Scalar/GVN.h"
38 #include "llvm/Transforms/Vectorize.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/LegacyPassManager.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Target/TargetLoweringObjectFile.h"
46 #include <memory>
47 
48 using namespace llvm;
49 
50 static cl::opt<bool> EnableR600StructurizeCFG(
51   "r600-ir-structurize",
52   cl::desc("Use StructurizeCFG IR pass"),
53   cl::init(true));
54 
55 static cl::opt<bool> EnableSROA(
56   "amdgpu-sroa",
57   cl::desc("Run SROA after promote alloca pass"),
58   cl::ReallyHidden,
59   cl::init(true));
60 
61 static cl::opt<bool> EnableR600IfConvert(
62   "r600-if-convert",
63   cl::desc("Use if conversion pass"),
64   cl::ReallyHidden,
65   cl::init(true));
66 
67 // Option to disable vectorizer for tests.
68 static cl::opt<bool> EnableLoadStoreVectorizer(
69   "amdgpu-load-store-vectorizer",
70   cl::desc("Enable load store vectorizer"),
71   cl::init(true),
72   cl::Hidden);
73 
74 // Option to to control global loads scalarization
75 static cl::opt<bool> ScalarizeGlobal(
76   "amdgpu-scalarize-global-loads",
77   cl::desc("Enable global load scalarization"),
78   cl::init(false),
79   cl::Hidden);
80 
81 extern "C" void LLVMInitializeAMDGPUTarget() {
82   // Register the target
83   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
84   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
85 
86   PassRegistry *PR = PassRegistry::getPassRegistry();
87   initializeSILowerI1CopiesPass(*PR);
88   initializeSIFixSGPRCopiesPass(*PR);
89   initializeSIFixVGPRCopiesPass(*PR);
90   initializeSIFoldOperandsPass(*PR);
91   initializeSIShrinkInstructionsPass(*PR);
92   initializeSIFixControlFlowLiveIntervalsPass(*PR);
93   initializeSILoadStoreOptimizerPass(*PR);
94   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
95   initializeAMDGPUAnnotateUniformValuesPass(*PR);
96   initializeAMDGPUPromoteAllocaPass(*PR);
97   initializeAMDGPUCodeGenPreparePass(*PR);
98   initializeAMDGPUUnifyMetadataPass(*PR);
99   initializeSIAnnotateControlFlowPass(*PR);
100   initializeSIInsertWaitsPass(*PR);
101   initializeSIWholeQuadModePass(*PR);
102   initializeSILowerControlFlowPass(*PR);
103   initializeSIInsertSkipsPass(*PR);
104   initializeSIDebuggerInsertNopsPass(*PR);
105   initializeSIOptimizeExecMaskingPass(*PR);
106 }
107 
108 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
109   return llvm::make_unique<AMDGPUTargetObjectFile>();
110 }
111 
112 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
113   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
114 }
115 
116 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
117   return new SIScheduleDAGMI(C);
118 }
119 
120 static ScheduleDAGInstrs *
121 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
122   ScheduleDAGMILive *DAG =
123       new ScheduleDAGMILive(C,
124                             llvm::make_unique<GCNMaxOccupancySchedStrategy>(C));
125   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
126   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
127   return DAG;
128 }
129 
130 static MachineSchedRegistry
131 R600SchedRegistry("r600", "Run R600's custom scheduler",
132                    createR600MachineScheduler);
133 
134 static MachineSchedRegistry
135 SISchedRegistry("si", "Run SI's custom scheduler",
136                 createSIMachineScheduler);
137 
138 static MachineSchedRegistry
139 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
140                              "Run GCN scheduler to maximize occupancy",
141                              createGCNMaxOccupancyMachineScheduler);
142 
143 static StringRef computeDataLayout(const Triple &TT) {
144   if (TT.getArch() == Triple::r600) {
145     // 32-bit pointers.
146     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
147             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
148   }
149 
150   // 32-bit private, local, and region pointers. 64-bit global, constant and
151   // flat.
152   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
153          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
154          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
155 }
156 
157 LLVM_READNONE
158 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
159   if (!GPU.empty())
160     return GPU;
161 
162   // HSA only supports CI+, so change the default GPU to a CI for HSA.
163   if (TT.getArch() == Triple::amdgcn)
164     return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
165 
166   return "r600";
167 }
168 
169 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
170   // The AMDGPU toolchain only supports generating shared objects, so we
171   // must always use PIC.
172   return Reloc::PIC_;
173 }
174 
175 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
176                                          StringRef CPU, StringRef FS,
177                                          TargetOptions Options,
178                                          Optional<Reloc::Model> RM,
179                                          CodeModel::Model CM,
180                                          CodeGenOpt::Level OptLevel)
181   : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
182                       FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
183     TLOF(createTLOF(getTargetTriple())) {
184   initAsmInfo();
185 }
186 
187 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
188 
189 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
190   Attribute GPUAttr = F.getFnAttribute("target-cpu");
191   return GPUAttr.hasAttribute(Attribute::None) ?
192     getTargetCPU() : GPUAttr.getValueAsString();
193 }
194 
195 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
196   Attribute FSAttr = F.getFnAttribute("target-features");
197 
198   return FSAttr.hasAttribute(Attribute::None) ?
199     getTargetFeatureString() :
200     FSAttr.getValueAsString();
201 }
202 
203 void AMDGPUTargetMachine::addEarlyAsPossiblePasses(PassManagerBase &PM) {
204   PM.add(createAMDGPUUnifyMetadataPass());
205 }
206 
207 //===----------------------------------------------------------------------===//
208 // R600 Target Machine (R600 -> Cayman)
209 //===----------------------------------------------------------------------===//
210 
211 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
212                                      StringRef CPU, StringRef FS,
213                                      TargetOptions Options,
214                                      Optional<Reloc::Model> RM,
215                                      CodeModel::Model CM, CodeGenOpt::Level OL)
216   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
217   setRequiresStructuredCFG(true);
218 }
219 
220 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
221   const Function &F) const {
222   StringRef GPU = getGPUName(F);
223   StringRef FS = getFeatureString(F);
224 
225   SmallString<128> SubtargetKey(GPU);
226   SubtargetKey.append(FS);
227 
228   auto &I = SubtargetMap[SubtargetKey];
229   if (!I) {
230     // This needs to be done before we create a new subtarget since any
231     // creation will depend on the TM and the code generation flags on the
232     // function that reside in TargetOptions.
233     resetTargetOptions(F);
234     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
235   }
236 
237   return I.get();
238 }
239 
240 //===----------------------------------------------------------------------===//
241 // GCN Target Machine (SI+)
242 //===----------------------------------------------------------------------===//
243 
244 #ifdef LLVM_BUILD_GLOBAL_ISEL
245 namespace {
246 
247 struct SIGISelActualAccessor : public GISelAccessor {
248   std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
249   const AMDGPUCallLowering *getCallLowering() const override {
250     return CallLoweringInfo.get();
251   }
252 };
253 
254 } // end anonymous namespace
255 #endif
256 
257 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
258                                    StringRef CPU, StringRef FS,
259                                    TargetOptions Options,
260                                    Optional<Reloc::Model> RM,
261                                    CodeModel::Model CM, CodeGenOpt::Level OL)
262   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
263 
264 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
265   StringRef GPU = getGPUName(F);
266   StringRef FS = getFeatureString(F);
267 
268   SmallString<128> SubtargetKey(GPU);
269   SubtargetKey.append(FS);
270 
271   auto &I = SubtargetMap[SubtargetKey];
272   if (!I) {
273     // This needs to be done before we create a new subtarget since any
274     // creation will depend on the TM and the code generation flags on the
275     // function that reside in TargetOptions.
276     resetTargetOptions(F);
277     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
278 
279 #ifndef LLVM_BUILD_GLOBAL_ISEL
280     GISelAccessor *GISel = new GISelAccessor();
281 #else
282     SIGISelActualAccessor *GISel = new SIGISelActualAccessor();
283     GISel->CallLoweringInfo.reset(
284       new AMDGPUCallLowering(*I->getTargetLowering()));
285 #endif
286 
287     I->setGISelAccessor(*GISel);
288   }
289 
290   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
291 
292   return I.get();
293 }
294 
295 //===----------------------------------------------------------------------===//
296 // AMDGPU Pass Setup
297 //===----------------------------------------------------------------------===//
298 
299 namespace {
300 
301 class AMDGPUPassConfig : public TargetPassConfig {
302 public:
303   AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
304     : TargetPassConfig(TM, PM) {
305     // Exceptions and StackMaps are not supported, so these passes will never do
306     // anything.
307     disablePass(&StackMapLivenessID);
308     disablePass(&FuncletLayoutID);
309   }
310 
311   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
312     return getTM<AMDGPUTargetMachine>();
313   }
314 
315   ScheduleDAGInstrs *
316   createMachineScheduler(MachineSchedContext *C) const override {
317     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
318     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
319     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
320     return DAG;
321   }
322 
323   void addEarlyCSEOrGVNPass();
324   void addStraightLineScalarOptimizationPasses();
325   void addIRPasses() override;
326   void addCodeGenPrepare() override;
327   bool addPreISel() override;
328   bool addInstSelector() override;
329   bool addGCPasses() override;
330 };
331 
332 class R600PassConfig final : public AMDGPUPassConfig {
333 public:
334   R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
335     : AMDGPUPassConfig(TM, PM) {}
336 
337   ScheduleDAGInstrs *createMachineScheduler(
338     MachineSchedContext *C) const override {
339     return createR600MachineScheduler(C);
340   }
341 
342   bool addPreISel() override;
343   void addPreRegAlloc() override;
344   void addPreSched2() override;
345   void addPreEmitPass() override;
346 };
347 
348 class GCNPassConfig final : public AMDGPUPassConfig {
349 public:
350   GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
351     : AMDGPUPassConfig(TM, PM) {}
352 
353   GCNTargetMachine &getGCNTargetMachine() const {
354     return getTM<GCNTargetMachine>();
355   }
356 
357   ScheduleDAGInstrs *
358   createMachineScheduler(MachineSchedContext *C) const override;
359 
360   void addIRPasses() override;
361   bool addPreISel() override;
362   void addMachineSSAOptimization() override;
363   bool addInstSelector() override;
364 #ifdef LLVM_BUILD_GLOBAL_ISEL
365   bool addIRTranslator() override;
366   bool addLegalizeMachineIR() override;
367   bool addRegBankSelect() override;
368   bool addGlobalInstructionSelect() override;
369 #endif
370   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
371   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
372   void addPreRegAlloc() override;
373   void addPostRegAlloc() override;
374   void addPreSched2() override;
375   void addPreEmitPass() override;
376 };
377 
378 } // end anonymous namespace
379 
380 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
381   return TargetIRAnalysis([this](const Function &F) {
382     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
383   });
384 }
385 
386 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
387   if (getOptLevel() == CodeGenOpt::Aggressive)
388     addPass(createGVNPass());
389   else
390     addPass(createEarlyCSEPass());
391 }
392 
393 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
394   addPass(createSeparateConstOffsetFromGEPPass());
395   addPass(createSpeculativeExecutionPass());
396   // ReassociateGEPs exposes more opportunites for SLSR. See
397   // the example in reassociate-geps-and-slsr.ll.
398   addPass(createStraightLineStrengthReducePass());
399   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
400   // EarlyCSE can reuse.
401   addEarlyCSEOrGVNPass();
402   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
403   addPass(createNaryReassociatePass());
404   // NaryReassociate on GEPs creates redundant common expressions, so run
405   // EarlyCSE after it.
406   addPass(createEarlyCSEPass());
407 }
408 
409 void AMDGPUPassConfig::addIRPasses() {
410   // There is no reason to run these.
411   disablePass(&StackMapLivenessID);
412   disablePass(&FuncletLayoutID);
413   disablePass(&PatchableFunctionID);
414 
415   // Function calls are not supported, so make sure we inline everything.
416   addPass(createAMDGPUAlwaysInlinePass());
417   addPass(createAlwaysInlinerLegacyPass());
418   // We need to add the barrier noop pass, otherwise adding the function
419   // inlining pass will cause all of the PassConfigs passes to be run
420   // one function at a time, which means if we have a nodule with two
421   // functions, then we will generate code for the first function
422   // without ever running any passes on the second.
423   addPass(createBarrierNoopPass());
424 
425   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
426   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
427 
428   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
429   if (TM.getOptLevel() > CodeGenOpt::None) {
430     addPass(createAMDGPUPromoteAlloca(&TM));
431 
432     if (EnableSROA)
433       addPass(createSROAPass());
434 
435     addStraightLineScalarOptimizationPasses();
436   }
437 
438   TargetPassConfig::addIRPasses();
439 
440   // EarlyCSE is not always strong enough to clean up what LSR produces. For
441   // example, GVN can combine
442   //
443   //   %0 = add %a, %b
444   //   %1 = add %b, %a
445   //
446   // and
447   //
448   //   %0 = shl nsw %a, 2
449   //   %1 = shl %a, 2
450   //
451   // but EarlyCSE can do neither of them.
452   if (getOptLevel() != CodeGenOpt::None)
453     addEarlyCSEOrGVNPass();
454 }
455 
456 void AMDGPUPassConfig::addCodeGenPrepare() {
457   TargetPassConfig::addCodeGenPrepare();
458 
459   if (EnableLoadStoreVectorizer)
460     addPass(createLoadStoreVectorizerPass());
461 }
462 
463 bool AMDGPUPassConfig::addPreISel() {
464   addPass(createFlattenCFGPass());
465   return false;
466 }
467 
468 bool AMDGPUPassConfig::addInstSelector() {
469   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));
470   return false;
471 }
472 
473 bool AMDGPUPassConfig::addGCPasses() {
474   // Do nothing. GC is not supported.
475   return false;
476 }
477 
478 //===----------------------------------------------------------------------===//
479 // R600 Pass Setup
480 //===----------------------------------------------------------------------===//
481 
482 bool R600PassConfig::addPreISel() {
483   AMDGPUPassConfig::addPreISel();
484 
485   if (EnableR600StructurizeCFG)
486     addPass(createStructurizeCFGPass());
487   return false;
488 }
489 
490 void R600PassConfig::addPreRegAlloc() {
491   addPass(createR600VectorRegMerger(*TM));
492 }
493 
494 void R600PassConfig::addPreSched2() {
495   addPass(createR600EmitClauseMarkers(), false);
496   if (EnableR600IfConvert)
497     addPass(&IfConverterID, false);
498   addPass(createR600ClauseMergePass(*TM), false);
499 }
500 
501 void R600PassConfig::addPreEmitPass() {
502   addPass(createAMDGPUCFGStructurizerPass(), false);
503   addPass(createR600ExpandSpecialInstrsPass(*TM), false);
504   addPass(&FinalizeMachineBundlesID, false);
505   addPass(createR600Packetizer(*TM), false);
506   addPass(createR600ControlFlowFinalizer(*TM), false);
507 }
508 
509 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
510   return new R600PassConfig(this, PM);
511 }
512 
513 //===----------------------------------------------------------------------===//
514 // GCN Pass Setup
515 //===----------------------------------------------------------------------===//
516 
517 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
518   MachineSchedContext *C) const {
519   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
520   if (ST.enableSIScheduler())
521     return createSIMachineScheduler(C);
522   return createGCNMaxOccupancyMachineScheduler(C);
523 }
524 
525 bool GCNPassConfig::addPreISel() {
526   AMDGPUPassConfig::addPreISel();
527 
528   // FIXME: We need to run a pass to propagate the attributes when calls are
529   // supported.
530   addPass(&AMDGPUAnnotateKernelFeaturesID);
531   addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
532   addPass(createSinkingPass());
533   addPass(createSITypeRewriter());
534   addPass(createAMDGPUAnnotateUniformValues());
535   addPass(createSIAnnotateControlFlowPass());
536 
537   return false;
538 }
539 
540 void GCNPassConfig::addMachineSSAOptimization() {
541   TargetPassConfig::addMachineSSAOptimization();
542 
543   // We want to fold operands after PeepholeOptimizer has run (or as part of
544   // it), because it will eliminate extra copies making it easier to fold the
545   // real source operand. We want to eliminate dead instructions after, so that
546   // we see fewer uses of the copies. We then need to clean up the dead
547   // instructions leftover after the operands are folded as well.
548   //
549   // XXX - Can we get away without running DeadMachineInstructionElim again?
550   addPass(&SIFoldOperandsID);
551   addPass(&DeadMachineInstructionElimID);
552   addPass(&SILoadStoreOptimizerID);
553 }
554 
555 void GCNPassConfig::addIRPasses() {
556   // TODO: May want to move later or split into an early and late one.
557   addPass(createAMDGPUCodeGenPreparePass(&getGCNTargetMachine()));
558 
559   AMDGPUPassConfig::addIRPasses();
560 }
561 
562 bool GCNPassConfig::addInstSelector() {
563   AMDGPUPassConfig::addInstSelector();
564   addPass(createSILowerI1CopiesPass());
565   addPass(&SIFixSGPRCopiesID);
566   return false;
567 }
568 
569 #ifdef LLVM_BUILD_GLOBAL_ISEL
570 bool GCNPassConfig::addIRTranslator() {
571   addPass(new IRTranslator());
572   return false;
573 }
574 
575 bool GCNPassConfig::addLegalizeMachineIR() {
576   return false;
577 }
578 
579 bool GCNPassConfig::addRegBankSelect() {
580   return false;
581 }
582 
583 bool GCNPassConfig::addGlobalInstructionSelect() {
584   return false;
585 }
586 #endif
587 
588 void GCNPassConfig::addPreRegAlloc() {
589   addPass(createSIShrinkInstructionsPass());
590   addPass(createSIWholeQuadModePass());
591 }
592 
593 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
594   // FIXME: We have to disable the verifier here because of PHIElimination +
595   // TwoAddressInstructions disabling it.
596 
597   // This must be run immediately after phi elimination and before
598   // TwoAddressInstructions, otherwise the processing of the tied operand of
599   // SI_ELSE will introduce a copy of the tied operand source after the else.
600   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
601 
602   TargetPassConfig::addFastRegAlloc(RegAllocPass);
603 }
604 
605 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
606   // This needs to be run directly before register allocation because earlier
607   // passes might recompute live intervals.
608   insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
609 
610   // This must be run immediately after phi elimination and before
611   // TwoAddressInstructions, otherwise the processing of the tied operand of
612   // SI_ELSE will introduce a copy of the tied operand source after the else.
613   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
614 
615   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
616 }
617 
618 void GCNPassConfig::addPostRegAlloc() {
619   addPass(&SIFixVGPRCopiesID);
620   addPass(&SIOptimizeExecMaskingID);
621   TargetPassConfig::addPostRegAlloc();
622 }
623 
624 void GCNPassConfig::addPreSched2() {
625 }
626 
627 void GCNPassConfig::addPreEmitPass() {
628   // The hazard recognizer that runs as part of the post-ra scheduler does not
629   // guarantee to be able handle all hazards correctly. This is because if there
630   // are multiple scheduling regions in a basic block, the regions are scheduled
631   // bottom up, so when we begin to schedule a region we don't know what
632   // instructions were emitted directly before it.
633   //
634   // Here we add a stand-alone hazard recognizer pass which can handle all
635   // cases.
636   addPass(&PostRAHazardRecognizerID);
637 
638   addPass(createSIInsertWaitsPass());
639   addPass(createSIShrinkInstructionsPass());
640   addPass(&SIInsertSkipsPassID);
641   addPass(createSIDebuggerInsertNopsPass());
642   addPass(&BranchRelaxationPassID);
643 }
644 
645 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
646   return new GCNPassConfig(this, PM);
647 }
648