1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110   cl::desc("Enable AMDGPU Alias Analysis"),
111   cl::init(true));
112 
113 // Option to run late CFG structurizer
114 static cl::opt<bool, true> LateCFGStructurize(
115   "amdgpu-late-structurize",
116   cl::desc("Enable late CFG structurization"),
117   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
118   cl::Hidden);
119 
120 static cl::opt<bool> EnableAMDGPUFunctionCalls(
121   "amdgpu-function-calls",
122   cl::Hidden,
123   cl::desc("Enable AMDGPU function call support"),
124   cl::init(false));
125 
126 // Enable lib calls simplifications
127 static cl::opt<bool> EnableLibCallSimplify(
128   "amdgpu-simplify-libcall",
129   cl::desc("Enable amdgpu library simplifications"),
130   cl::init(true),
131   cl::Hidden);
132 
133 static cl::opt<bool> EnableLowerKernelArguments(
134   "amdgpu-ir-lower-kernel-arguments",
135   cl::desc("Lower kernel argument loads in IR pass"),
136   cl::init(true),
137   cl::Hidden);
138 
139 extern "C" void LLVMInitializeAMDGPUTarget() {
140   // Register the target
141   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
142   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
143 
144   PassRegistry *PR = PassRegistry::getPassRegistry();
145   initializeR600ClauseMergePassPass(*PR);
146   initializeR600ControlFlowFinalizerPass(*PR);
147   initializeR600PacketizerPass(*PR);
148   initializeR600ExpandSpecialInstrsPassPass(*PR);
149   initializeR600VectorRegMergerPass(*PR);
150   initializeGlobalISel(*PR);
151   initializeAMDGPUDAGToDAGISelPass(*PR);
152   initializeSILowerI1CopiesPass(*PR);
153   initializeSIFixSGPRCopiesPass(*PR);
154   initializeSIFixVGPRCopiesPass(*PR);
155   initializeSIFoldOperandsPass(*PR);
156   initializeSIPeepholeSDWAPass(*PR);
157   initializeSIShrinkInstructionsPass(*PR);
158   initializeSIOptimizeExecMaskingPreRAPass(*PR);
159   initializeSILoadStoreOptimizerPass(*PR);
160   initializeAMDGPUAlwaysInlinePass(*PR);
161   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
162   initializeAMDGPUAnnotateUniformValuesPass(*PR);
163   initializeAMDGPUArgumentUsageInfoPass(*PR);
164   initializeAMDGPULowerKernelArgumentsPass(*PR);
165   initializeAMDGPULowerKernelAttributesPass(*PR);
166   initializeAMDGPULowerIntrinsicsPass(*PR);
167   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
168   initializeAMDGPUPromoteAllocaPass(*PR);
169   initializeAMDGPUCodeGenPreparePass(*PR);
170   initializeAMDGPURewriteOutArgumentsPass(*PR);
171   initializeAMDGPUUnifyMetadataPass(*PR);
172   initializeSIAnnotateControlFlowPass(*PR);
173   initializeSIInsertWaitcntsPass(*PR);
174   initializeSIWholeQuadModePass(*PR);
175   initializeSILowerControlFlowPass(*PR);
176   initializeSIInsertSkipsPass(*PR);
177   initializeSIMemoryLegalizerPass(*PR);
178   initializeSIDebuggerInsertNopsPass(*PR);
179   initializeSIOptimizeExecMaskingPass(*PR);
180   initializeSIFixWWMLivenessPass(*PR);
181   initializeSIFormMemoryClausesPass(*PR);
182   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
183   initializeAMDGPUAAWrapperPassPass(*PR);
184   initializeAMDGPUUseNativeCallsPass(*PR);
185   initializeAMDGPUSimplifyLibCallsPass(*PR);
186   initializeAMDGPUInlinerPass(*PR);
187 }
188 
189 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
190   return llvm::make_unique<AMDGPUTargetObjectFile>();
191 }
192 
193 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
194   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
195 }
196 
197 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
198   return new SIScheduleDAGMI(C);
199 }
200 
201 static ScheduleDAGInstrs *
202 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
203   ScheduleDAGMILive *DAG =
204     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
205   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
206   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
207   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
208   return DAG;
209 }
210 
211 static ScheduleDAGInstrs *
212 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
213   auto DAG = new GCNIterativeScheduler(C,
214     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
215   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
216   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
217   return DAG;
218 }
219 
220 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
221   return new GCNIterativeScheduler(C,
222     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
223 }
224 
225 static ScheduleDAGInstrs *
226 createIterativeILPMachineScheduler(MachineSchedContext *C) {
227   auto DAG = new GCNIterativeScheduler(C,
228     GCNIterativeScheduler::SCHEDULE_ILP);
229   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
230   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
231   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
232   return DAG;
233 }
234 
235 static MachineSchedRegistry
236 R600SchedRegistry("r600", "Run R600's custom scheduler",
237                    createR600MachineScheduler);
238 
239 static MachineSchedRegistry
240 SISchedRegistry("si", "Run SI's custom scheduler",
241                 createSIMachineScheduler);
242 
243 static MachineSchedRegistry
244 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
245                              "Run GCN scheduler to maximize occupancy",
246                              createGCNMaxOccupancyMachineScheduler);
247 
248 static MachineSchedRegistry
249 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
250   "Run GCN scheduler to maximize occupancy (experimental)",
251   createIterativeGCNMaxOccupancyMachineScheduler);
252 
253 static MachineSchedRegistry
254 GCNMinRegSchedRegistry("gcn-minreg",
255   "Run GCN iterative scheduler for minimal register usage (experimental)",
256   createMinRegScheduler);
257 
258 static MachineSchedRegistry
259 GCNILPSchedRegistry("gcn-ilp",
260   "Run GCN iterative scheduler for ILP scheduling (experimental)",
261   createIterativeILPMachineScheduler);
262 
263 static StringRef computeDataLayout(const Triple &TT) {
264   if (TT.getArch() == Triple::r600) {
265     // 32-bit pointers.
266       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
267              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
268   }
269 
270   // 32-bit private, local, and region pointers. 64-bit global, constant and
271   // flat.
272     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
273          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
274          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
275 }
276 
277 LLVM_READNONE
278 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
279   if (!GPU.empty())
280     return GPU;
281 
282   if (TT.getArch() == Triple::amdgcn)
283     return "generic";
284 
285   return "r600";
286 }
287 
288 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
289   // The AMDGPU toolchain only supports generating shared objects, so we
290   // must always use PIC.
291   return Reloc::PIC_;
292 }
293 
294 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
295   if (CM)
296     return *CM;
297   return CodeModel::Small;
298 }
299 
300 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
301                                          StringRef CPU, StringRef FS,
302                                          TargetOptions Options,
303                                          Optional<Reloc::Model> RM,
304                                          Optional<CodeModel::Model> CM,
305                                          CodeGenOpt::Level OptLevel)
306     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
307                         FS, Options, getEffectiveRelocModel(RM),
308                         getEffectiveCodeModel(CM), OptLevel),
309       TLOF(createTLOF(getTargetTriple())) {
310   AS = AMDGPU::getAMDGPUAS(TT);
311   initAsmInfo();
312 }
313 
314 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
315 
316 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
317 
318 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
319   Attribute GPUAttr = F.getFnAttribute("target-cpu");
320   return GPUAttr.hasAttribute(Attribute::None) ?
321     getTargetCPU() : GPUAttr.getValueAsString();
322 }
323 
324 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
325   Attribute FSAttr = F.getFnAttribute("target-features");
326 
327   return FSAttr.hasAttribute(Attribute::None) ?
328     getTargetFeatureString() :
329     FSAttr.getValueAsString();
330 }
331 
332 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
333   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
334       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
335         AAR.addAAResult(WrapperPass->getResult());
336       });
337 }
338 
339 /// Predicate for Internalize pass.
340 static bool mustPreserveGV(const GlobalValue &GV) {
341   if (const Function *F = dyn_cast<Function>(&GV))
342     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
343 
344   return !GV.use_empty();
345 }
346 
347 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
348   Builder.DivergentTarget = true;
349 
350   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
351   bool Internalize = InternalizeSymbols;
352   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
353   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
354   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
355 
356   if (EnableAMDGPUFunctionCalls) {
357     delete Builder.Inliner;
358     Builder.Inliner = createAMDGPUFunctionInliningPass();
359   }
360 
361   if (Internalize) {
362     // If we're generating code, we always have the whole program available. The
363     // relocations expected for externally visible functions aren't supported,
364     // so make sure every non-entry function is hidden.
365     Builder.addExtension(
366       PassManagerBuilder::EP_EnabledOnOptLevel0,
367       [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
368         PM.add(createInternalizePass(mustPreserveGV));
369       });
370   }
371 
372   Builder.addExtension(
373     PassManagerBuilder::EP_ModuleOptimizerEarly,
374     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
375                                          legacy::PassManagerBase &PM) {
376       if (AMDGPUAA) {
377         PM.add(createAMDGPUAAWrapperPass());
378         PM.add(createAMDGPUExternalAAWrapperPass());
379       }
380       PM.add(createAMDGPUUnifyMetadataPass());
381       if (Internalize) {
382         PM.add(createInternalizePass(mustPreserveGV));
383         PM.add(createGlobalDCEPass());
384       }
385       if (EarlyInline)
386         PM.add(createAMDGPUAlwaysInlinePass(false));
387   });
388 
389   const auto &Opt = Options;
390   Builder.addExtension(
391     PassManagerBuilder::EP_EarlyAsPossible,
392     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
393                                       legacy::PassManagerBase &PM) {
394       if (AMDGPUAA) {
395         PM.add(createAMDGPUAAWrapperPass());
396         PM.add(createAMDGPUExternalAAWrapperPass());
397       }
398       PM.add(llvm::createAMDGPUUseNativeCallsPass());
399       if (LibCallSimplify)
400         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
401   });
402 
403   Builder.addExtension(
404     PassManagerBuilder::EP_CGSCCOptimizerLate,
405     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
406       // Add infer address spaces pass to the opt pipeline after inlining
407       // but before SROA to increase SROA opportunities.
408       PM.add(createInferAddressSpacesPass());
409 
410       // This should run after inlining to have any chance of doing anything,
411       // and before other cleanup optimizations.
412       PM.add(createAMDGPULowerKernelAttributesPass());
413   });
414 }
415 
416 //===----------------------------------------------------------------------===//
417 // R600 Target Machine (R600 -> Cayman)
418 //===----------------------------------------------------------------------===//
419 
420 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
421                                      StringRef CPU, StringRef FS,
422                                      TargetOptions Options,
423                                      Optional<Reloc::Model> RM,
424                                      Optional<CodeModel::Model> CM,
425                                      CodeGenOpt::Level OL, bool JIT)
426     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
427   setRequiresStructuredCFG(true);
428 }
429 
430 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
431   const Function &F) const {
432   StringRef GPU = getGPUName(F);
433   StringRef FS = getFeatureString(F);
434 
435   SmallString<128> SubtargetKey(GPU);
436   SubtargetKey.append(FS);
437 
438   auto &I = SubtargetMap[SubtargetKey];
439   if (!I) {
440     // This needs to be done before we create a new subtarget since any
441     // creation will depend on the TM and the code generation flags on the
442     // function that reside in TargetOptions.
443     resetTargetOptions(F);
444     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
445   }
446 
447   return I.get();
448 }
449 
450 TargetTransformInfo
451 R600TargetMachine::getTargetTransformInfo(const Function &F) {
452   return TargetTransformInfo(R600TTIImpl(this, F));
453 }
454 
455 //===----------------------------------------------------------------------===//
456 // GCN Target Machine (SI+)
457 //===----------------------------------------------------------------------===//
458 
459 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
460                                    StringRef CPU, StringRef FS,
461                                    TargetOptions Options,
462                                    Optional<Reloc::Model> RM,
463                                    Optional<CodeModel::Model> CM,
464                                    CodeGenOpt::Level OL, bool JIT)
465     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
466 
467 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
468   StringRef GPU = getGPUName(F);
469   StringRef FS = getFeatureString(F);
470 
471   SmallString<128> SubtargetKey(GPU);
472   SubtargetKey.append(FS);
473 
474   auto &I = SubtargetMap[SubtargetKey];
475   if (!I) {
476     // This needs to be done before we create a new subtarget since any
477     // creation will depend on the TM and the code generation flags on the
478     // function that reside in TargetOptions.
479     resetTargetOptions(F);
480     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
481   }
482 
483   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
484 
485   return I.get();
486 }
487 
488 TargetTransformInfo
489 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
490   return TargetTransformInfo(GCNTTIImpl(this, F));
491 }
492 
493 //===----------------------------------------------------------------------===//
494 // AMDGPU Pass Setup
495 //===----------------------------------------------------------------------===//
496 
497 namespace {
498 
499 class AMDGPUPassConfig : public TargetPassConfig {
500 public:
501   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
502     : TargetPassConfig(TM, PM) {
503     // Exceptions and StackMaps are not supported, so these passes will never do
504     // anything.
505     disablePass(&StackMapLivenessID);
506     disablePass(&FuncletLayoutID);
507   }
508 
509   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
510     return getTM<AMDGPUTargetMachine>();
511   }
512 
513   ScheduleDAGInstrs *
514   createMachineScheduler(MachineSchedContext *C) const override {
515     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
516     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
517     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
518     return DAG;
519   }
520 
521   void addEarlyCSEOrGVNPass();
522   void addStraightLineScalarOptimizationPasses();
523   void addIRPasses() override;
524   void addCodeGenPrepare() override;
525   bool addPreISel() override;
526   bool addInstSelector() override;
527   bool addGCPasses() override;
528 };
529 
530 class R600PassConfig final : public AMDGPUPassConfig {
531 public:
532   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
533     : AMDGPUPassConfig(TM, PM) {}
534 
535   ScheduleDAGInstrs *createMachineScheduler(
536     MachineSchedContext *C) const override {
537     return createR600MachineScheduler(C);
538   }
539 
540   bool addPreISel() override;
541   bool addInstSelector() override;
542   void addPreRegAlloc() override;
543   void addPreSched2() override;
544   void addPreEmitPass() override;
545 };
546 
547 class GCNPassConfig final : public AMDGPUPassConfig {
548 public:
549   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
550     : AMDGPUPassConfig(TM, PM) {
551     // It is necessary to know the register usage of the entire call graph.  We
552     // allow calls without EnableAMDGPUFunctionCalls if they are marked
553     // noinline, so this is always required.
554     setRequiresCodeGenSCCOrder(true);
555   }
556 
557   GCNTargetMachine &getGCNTargetMachine() const {
558     return getTM<GCNTargetMachine>();
559   }
560 
561   ScheduleDAGInstrs *
562   createMachineScheduler(MachineSchedContext *C) const override;
563 
564   bool addPreISel() override;
565   void addMachineSSAOptimization() override;
566   bool addILPOpts() override;
567   bool addInstSelector() override;
568   bool addIRTranslator() override;
569   bool addLegalizeMachineIR() override;
570   bool addRegBankSelect() override;
571   bool addGlobalInstructionSelect() override;
572   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
573   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
574   void addPreRegAlloc() override;
575   void addPostRegAlloc() override;
576   void addPreSched2() override;
577   void addPreEmitPass() override;
578 };
579 
580 } // end anonymous namespace
581 
582 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
583   if (getOptLevel() == CodeGenOpt::Aggressive)
584     addPass(createGVNPass());
585   else
586     addPass(createEarlyCSEPass());
587 }
588 
589 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
590   addPass(createLICMPass());
591   addPass(createSeparateConstOffsetFromGEPPass());
592   addPass(createSpeculativeExecutionPass());
593   // ReassociateGEPs exposes more opportunites for SLSR. See
594   // the example in reassociate-geps-and-slsr.ll.
595   addPass(createStraightLineStrengthReducePass());
596   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
597   // EarlyCSE can reuse.
598   addEarlyCSEOrGVNPass();
599   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
600   addPass(createNaryReassociatePass());
601   // NaryReassociate on GEPs creates redundant common expressions, so run
602   // EarlyCSE after it.
603   addPass(createEarlyCSEPass());
604 }
605 
606 void AMDGPUPassConfig::addIRPasses() {
607   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
608 
609   // There is no reason to run these.
610   disablePass(&StackMapLivenessID);
611   disablePass(&FuncletLayoutID);
612   disablePass(&PatchableFunctionID);
613 
614   addPass(createAMDGPULowerIntrinsicsPass());
615 
616   if (TM.getTargetTriple().getArch() == Triple::r600 ||
617       !EnableAMDGPUFunctionCalls) {
618     // Function calls are not supported, so make sure we inline everything.
619     addPass(createAMDGPUAlwaysInlinePass());
620     addPass(createAlwaysInlinerLegacyPass());
621     // We need to add the barrier noop pass, otherwise adding the function
622     // inlining pass will cause all of the PassConfigs passes to be run
623     // one function at a time, which means if we have a nodule with two
624     // functions, then we will generate code for the first function
625     // without ever running any passes on the second.
626     addPass(createBarrierNoopPass());
627   }
628 
629   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
630     // TODO: May want to move later or split into an early and late one.
631 
632     addPass(createAMDGPUCodeGenPreparePass());
633   }
634 
635   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
636   if (TM.getTargetTriple().getArch() == Triple::r600)
637     addPass(createR600OpenCLImageTypeLoweringPass());
638 
639   // Replace OpenCL enqueued block function pointers with global variables.
640   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
641 
642   if (TM.getOptLevel() > CodeGenOpt::None) {
643     addPass(createInferAddressSpacesPass());
644     addPass(createAMDGPUPromoteAlloca());
645 
646     if (EnableSROA)
647       addPass(createSROAPass());
648 
649     addStraightLineScalarOptimizationPasses();
650 
651     if (EnableAMDGPUAliasAnalysis) {
652       addPass(createAMDGPUAAWrapperPass());
653       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
654                                              AAResults &AAR) {
655         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
656           AAR.addAAResult(WrapperPass->getResult());
657         }));
658     }
659   }
660 
661   TargetPassConfig::addIRPasses();
662 
663   // EarlyCSE is not always strong enough to clean up what LSR produces. For
664   // example, GVN can combine
665   //
666   //   %0 = add %a, %b
667   //   %1 = add %b, %a
668   //
669   // and
670   //
671   //   %0 = shl nsw %a, 2
672   //   %1 = shl %a, 2
673   //
674   // but EarlyCSE can do neither of them.
675   if (getOptLevel() != CodeGenOpt::None)
676     addEarlyCSEOrGVNPass();
677 }
678 
679 void AMDGPUPassConfig::addCodeGenPrepare() {
680   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
681       EnableLowerKernelArguments)
682     addPass(createAMDGPULowerKernelArgumentsPass());
683 
684   TargetPassConfig::addCodeGenPrepare();
685 
686   if (EnableLoadStoreVectorizer)
687     addPass(createLoadStoreVectorizerPass());
688 }
689 
690 bool AMDGPUPassConfig::addPreISel() {
691   addPass(createFlattenCFGPass());
692   return false;
693 }
694 
695 bool AMDGPUPassConfig::addInstSelector() {
696   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
697   return false;
698 }
699 
700 bool AMDGPUPassConfig::addGCPasses() {
701   // Do nothing. GC is not supported.
702   return false;
703 }
704 
705 //===----------------------------------------------------------------------===//
706 // R600 Pass Setup
707 //===----------------------------------------------------------------------===//
708 
709 bool R600PassConfig::addPreISel() {
710   AMDGPUPassConfig::addPreISel();
711 
712   if (EnableR600StructurizeCFG)
713     addPass(createStructurizeCFGPass());
714   return false;
715 }
716 
717 bool R600PassConfig::addInstSelector() {
718   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
719   return false;
720 }
721 
722 void R600PassConfig::addPreRegAlloc() {
723   addPass(createR600VectorRegMerger());
724 }
725 
726 void R600PassConfig::addPreSched2() {
727   addPass(createR600EmitClauseMarkers(), false);
728   if (EnableR600IfConvert)
729     addPass(&IfConverterID, false);
730   addPass(createR600ClauseMergePass(), false);
731 }
732 
733 void R600PassConfig::addPreEmitPass() {
734   addPass(createAMDGPUCFGStructurizerPass(), false);
735   addPass(createR600ExpandSpecialInstrsPass(), false);
736   addPass(&FinalizeMachineBundlesID, false);
737   addPass(createR600Packetizer(), false);
738   addPass(createR600ControlFlowFinalizer(), false);
739 }
740 
741 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
742   return new R600PassConfig(*this, PM);
743 }
744 
745 //===----------------------------------------------------------------------===//
746 // GCN Pass Setup
747 //===----------------------------------------------------------------------===//
748 
749 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
750   MachineSchedContext *C) const {
751   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
752   if (ST.enableSIScheduler())
753     return createSIMachineScheduler(C);
754   return createGCNMaxOccupancyMachineScheduler(C);
755 }
756 
757 bool GCNPassConfig::addPreISel() {
758   AMDGPUPassConfig::addPreISel();
759 
760   // FIXME: We need to run a pass to propagate the attributes when calls are
761   // supported.
762   addPass(createAMDGPUAnnotateKernelFeaturesPass());
763 
764   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
765   // regions formed by them.
766   addPass(&AMDGPUUnifyDivergentExitNodesID);
767   if (!LateCFGStructurize) {
768     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
769   }
770   addPass(createSinkingPass());
771   addPass(createAMDGPUAnnotateUniformValues());
772   if (!LateCFGStructurize) {
773     addPass(createSIAnnotateControlFlowPass());
774   }
775 
776   return false;
777 }
778 
779 void GCNPassConfig::addMachineSSAOptimization() {
780   TargetPassConfig::addMachineSSAOptimization();
781 
782   // We want to fold operands after PeepholeOptimizer has run (or as part of
783   // it), because it will eliminate extra copies making it easier to fold the
784   // real source operand. We want to eliminate dead instructions after, so that
785   // we see fewer uses of the copies. We then need to clean up the dead
786   // instructions leftover after the operands are folded as well.
787   //
788   // XXX - Can we get away without running DeadMachineInstructionElim again?
789   addPass(&SIFoldOperandsID);
790   addPass(&DeadMachineInstructionElimID);
791   addPass(&SILoadStoreOptimizerID);
792   if (EnableSDWAPeephole) {
793     addPass(&SIPeepholeSDWAID);
794     addPass(&EarlyMachineLICMID);
795     addPass(&MachineCSEID);
796     addPass(&SIFoldOperandsID);
797     addPass(&DeadMachineInstructionElimID);
798   }
799   addPass(createSIShrinkInstructionsPass());
800 }
801 
802 bool GCNPassConfig::addILPOpts() {
803   if (EnableEarlyIfConversion)
804     addPass(&EarlyIfConverterID);
805 
806   TargetPassConfig::addILPOpts();
807   return false;
808 }
809 
810 bool GCNPassConfig::addInstSelector() {
811   AMDGPUPassConfig::addInstSelector();
812   addPass(createSILowerI1CopiesPass());
813   addPass(&SIFixSGPRCopiesID);
814   return false;
815 }
816 
817 bool GCNPassConfig::addIRTranslator() {
818   addPass(new IRTranslator());
819   return false;
820 }
821 
822 bool GCNPassConfig::addLegalizeMachineIR() {
823   addPass(new Legalizer());
824   return false;
825 }
826 
827 bool GCNPassConfig::addRegBankSelect() {
828   addPass(new RegBankSelect());
829   return false;
830 }
831 
832 bool GCNPassConfig::addGlobalInstructionSelect() {
833   addPass(new InstructionSelect());
834   return false;
835 }
836 
837 void GCNPassConfig::addPreRegAlloc() {
838   if (LateCFGStructurize) {
839     addPass(createAMDGPUMachineCFGStructurizerPass());
840   }
841   addPass(createSIWholeQuadModePass());
842 }
843 
844 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
845   // FIXME: We have to disable the verifier here because of PHIElimination +
846   // TwoAddressInstructions disabling it.
847 
848   // This must be run immediately after phi elimination and before
849   // TwoAddressInstructions, otherwise the processing of the tied operand of
850   // SI_ELSE will introduce a copy of the tied operand source after the else.
851   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
852 
853   // This must be run after SILowerControlFlow, since it needs to use the
854   // machine-level CFG, but before register allocation.
855   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
856 
857   TargetPassConfig::addFastRegAlloc(RegAllocPass);
858 }
859 
860 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
861   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
862 
863   insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
864 
865   // This must be run immediately after phi elimination and before
866   // TwoAddressInstructions, otherwise the processing of the tied operand of
867   // SI_ELSE will introduce a copy of the tied operand source after the else.
868   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
869 
870   // This must be run after SILowerControlFlow, since it needs to use the
871   // machine-level CFG, but before register allocation.
872   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
873 
874   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
875 }
876 
877 void GCNPassConfig::addPostRegAlloc() {
878   addPass(&SIFixVGPRCopiesID);
879   addPass(&SIOptimizeExecMaskingID);
880   TargetPassConfig::addPostRegAlloc();
881 }
882 
883 void GCNPassConfig::addPreSched2() {
884 }
885 
886 void GCNPassConfig::addPreEmitPass() {
887   // The hazard recognizer that runs as part of the post-ra scheduler does not
888   // guarantee to be able handle all hazards correctly. This is because if there
889   // are multiple scheduling regions in a basic block, the regions are scheduled
890   // bottom up, so when we begin to schedule a region we don't know what
891   // instructions were emitted directly before it.
892   //
893   // Here we add a stand-alone hazard recognizer pass which can handle all
894   // cases.
895   addPass(&PostRAHazardRecognizerID);
896 
897   addPass(createSIMemoryLegalizerPass());
898   addPass(createSIInsertWaitcntsPass());
899   addPass(createSIShrinkInstructionsPass());
900   addPass(&SIInsertSkipsPassID);
901   addPass(createSIDebuggerInsertNopsPass());
902   addPass(&BranchRelaxationPassID);
903 }
904 
905 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
906   return new GCNPassConfig(*this, PM);
907 }
908