1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUExportClustering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
28 #include "R600MachineScheduler.h"
29 #include "SIMachineFunctionInfo.h"
30 #include "SIMachineScheduler.h"
31 #include "TargetInfo/AMDGPUTargetInfo.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
35 #include "llvm/CodeGen/GlobalISel/Localizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MIRParser/MIParser.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/LegacyPassManager.h"
43 #include "llvm/IR/PassManager.h"
44 #include "llvm/InitializePasses.h"
45 #include "llvm/Pass.h"
46 #include "llvm/Passes/PassBuilder.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Target/TargetLoweringObjectFile.h"
51 #include "llvm/Transforms/IPO.h"
52 #include "llvm/Transforms/IPO/AlwaysInliner.h"
53 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
54 #include "llvm/Transforms/Scalar.h"
55 #include "llvm/Transforms/Scalar/GVN.h"
56 #include "llvm/Transforms/Utils.h"
57 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
58 #include "llvm/Transforms/Vectorize.h"
59 #include <memory>
60 
61 using namespace llvm;
62 
63 static cl::opt<bool> EnableR600StructurizeCFG(
64   "r600-ir-structurize",
65   cl::desc("Use StructurizeCFG IR pass"),
66   cl::init(true));
67 
68 static cl::opt<bool> EnableSROA(
69   "amdgpu-sroa",
70   cl::desc("Run SROA after promote alloca pass"),
71   cl::ReallyHidden,
72   cl::init(true));
73 
74 static cl::opt<bool>
75 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
76                         cl::desc("Run early if-conversion"),
77                         cl::init(false));
78 
79 static cl::opt<bool>
80 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
81             cl::desc("Run pre-RA exec mask optimizations"),
82             cl::init(true));
83 
84 static cl::opt<bool> EnableR600IfConvert(
85   "r600-if-convert",
86   cl::desc("Use if conversion pass"),
87   cl::ReallyHidden,
88   cl::init(true));
89 
90 // Option to disable vectorizer for tests.
91 static cl::opt<bool> EnableLoadStoreVectorizer(
92   "amdgpu-load-store-vectorizer",
93   cl::desc("Enable load store vectorizer"),
94   cl::init(true),
95   cl::Hidden);
96 
97 // Option to control global loads scalarization
98 static cl::opt<bool> ScalarizeGlobal(
99   "amdgpu-scalarize-global-loads",
100   cl::desc("Enable global load scalarization"),
101   cl::init(true),
102   cl::Hidden);
103 
104 // Option to run internalize pass.
105 static cl::opt<bool> InternalizeSymbols(
106   "amdgpu-internalize-symbols",
107   cl::desc("Enable elimination of non-kernel functions and unused globals"),
108   cl::init(false),
109   cl::Hidden);
110 
111 // Option to inline all early.
112 static cl::opt<bool> EarlyInlineAll(
113   "amdgpu-early-inline-all",
114   cl::desc("Inline all functions early"),
115   cl::init(false),
116   cl::Hidden);
117 
118 static cl::opt<bool> EnableSDWAPeephole(
119   "amdgpu-sdwa-peephole",
120   cl::desc("Enable SDWA peepholer"),
121   cl::init(true));
122 
123 static cl::opt<bool> EnableDPPCombine(
124   "amdgpu-dpp-combine",
125   cl::desc("Enable DPP combiner"),
126   cl::init(true));
127 
128 // Enable address space based alias analysis
129 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
130   cl::desc("Enable AMDGPU Alias Analysis"),
131   cl::init(true));
132 
133 // Option to run late CFG structurizer
134 static cl::opt<bool, true> LateCFGStructurize(
135   "amdgpu-late-structurize",
136   cl::desc("Enable late CFG structurization"),
137   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
138   cl::Hidden);
139 
140 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
141   "amdgpu-function-calls",
142   cl::desc("Enable AMDGPU function call support"),
143   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
144   cl::init(true),
145   cl::Hidden);
146 
147 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
148   "amdgpu-fixed-function-abi",
149   cl::desc("Enable all implicit function arguments"),
150   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
151   cl::init(false),
152   cl::Hidden);
153 
154 // Enable lib calls simplifications
155 static cl::opt<bool> EnableLibCallSimplify(
156   "amdgpu-simplify-libcall",
157   cl::desc("Enable amdgpu library simplifications"),
158   cl::init(true),
159   cl::Hidden);
160 
161 static cl::opt<bool> EnableLowerKernelArguments(
162   "amdgpu-ir-lower-kernel-arguments",
163   cl::desc("Lower kernel argument loads in IR pass"),
164   cl::init(true),
165   cl::Hidden);
166 
167 static cl::opt<bool> EnableRegReassign(
168   "amdgpu-reassign-regs",
169   cl::desc("Enable register reassign optimizations on gfx10+"),
170   cl::init(true),
171   cl::Hidden);
172 
173 // Enable atomic optimization
174 static cl::opt<bool> EnableAtomicOptimizations(
175   "amdgpu-atomic-optimizations",
176   cl::desc("Enable atomic optimizations"),
177   cl::init(false),
178   cl::Hidden);
179 
180 // Enable Mode register optimization
181 static cl::opt<bool> EnableSIModeRegisterPass(
182   "amdgpu-mode-register",
183   cl::desc("Enable mode register pass"),
184   cl::init(true),
185   cl::Hidden);
186 
187 // Option is used in lit tests to prevent deadcoding of patterns inspected.
188 static cl::opt<bool>
189 EnableDCEInRA("amdgpu-dce-in-ra",
190     cl::init(true), cl::Hidden,
191     cl::desc("Enable machine DCE inside regalloc"));
192 
193 static cl::opt<bool> EnableScalarIRPasses(
194   "amdgpu-scalar-ir-passes",
195   cl::desc("Enable scalar IR passes"),
196   cl::init(true),
197   cl::Hidden);
198 
199 static cl::opt<bool> EnableStructurizerWorkarounds(
200     "amdgpu-enable-structurizer-workarounds",
201     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
202     cl::Hidden);
203 
204 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
205   // Register the target
206   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
207   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
208 
209   PassRegistry *PR = PassRegistry::getPassRegistry();
210   initializeR600ClauseMergePassPass(*PR);
211   initializeR600ControlFlowFinalizerPass(*PR);
212   initializeR600PacketizerPass(*PR);
213   initializeR600ExpandSpecialInstrsPassPass(*PR);
214   initializeR600VectorRegMergerPass(*PR);
215   initializeGlobalISel(*PR);
216   initializeAMDGPUDAGToDAGISelPass(*PR);
217   initializeGCNDPPCombinePass(*PR);
218   initializeSILowerI1CopiesPass(*PR);
219   initializeSILowerSGPRSpillsPass(*PR);
220   initializeSIFixSGPRCopiesPass(*PR);
221   initializeSIFixVGPRCopiesPass(*PR);
222   initializeSIFoldOperandsPass(*PR);
223   initializeSIPeepholeSDWAPass(*PR);
224   initializeSIShrinkInstructionsPass(*PR);
225   initializeSIOptimizeExecMaskingPreRAPass(*PR);
226   initializeSILoadStoreOptimizerPass(*PR);
227   initializeAMDGPUFixFunctionBitcastsPass(*PR);
228   initializeAMDGPUAlwaysInlinePass(*PR);
229   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
230   initializeAMDGPUAnnotateUniformValuesPass(*PR);
231   initializeAMDGPUArgumentUsageInfoPass(*PR);
232   initializeAMDGPUAtomicOptimizerPass(*PR);
233   initializeAMDGPULowerKernelArgumentsPass(*PR);
234   initializeAMDGPULowerKernelAttributesPass(*PR);
235   initializeAMDGPULowerIntrinsicsPass(*PR);
236   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
237   initializeAMDGPUPostLegalizerCombinerPass(*PR);
238   initializeAMDGPUPreLegalizerCombinerPass(*PR);
239   initializeAMDGPUPromoteAllocaPass(*PR);
240   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
241   initializeAMDGPUCodeGenPreparePass(*PR);
242   initializeAMDGPULateCodeGenPreparePass(*PR);
243   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
244   initializeAMDGPUPropagateAttributesLatePass(*PR);
245   initializeAMDGPURewriteOutArgumentsPass(*PR);
246   initializeAMDGPUUnifyMetadataPass(*PR);
247   initializeSIAnnotateControlFlowPass(*PR);
248   initializeSIInsertHardClausesPass(*PR);
249   initializeSIInsertWaitcntsPass(*PR);
250   initializeSIModeRegisterPass(*PR);
251   initializeSIWholeQuadModePass(*PR);
252   initializeSILowerControlFlowPass(*PR);
253   initializeSIRemoveShortExecBranchesPass(*PR);
254   initializeSIPreEmitPeepholePass(*PR);
255   initializeSIInsertSkipsPass(*PR);
256   initializeSIMemoryLegalizerPass(*PR);
257   initializeSIOptimizeExecMaskingPass(*PR);
258   initializeSIPreAllocateWWMRegsPass(*PR);
259   initializeSIFormMemoryClausesPass(*PR);
260   initializeSIPostRABundlerPass(*PR);
261   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
262   initializeAMDGPUAAWrapperPassPass(*PR);
263   initializeAMDGPUExternalAAWrapperPass(*PR);
264   initializeAMDGPUUseNativeCallsPass(*PR);
265   initializeAMDGPUSimplifyLibCallsPass(*PR);
266   initializeAMDGPUInlinerPass(*PR);
267   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
268   initializeGCNRegBankReassignPass(*PR);
269   initializeGCNNSAReassignPass(*PR);
270   initializeSIAddIMGInitPass(*PR);
271 }
272 
273 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
274   return std::make_unique<AMDGPUTargetObjectFile>();
275 }
276 
277 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
278   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
279 }
280 
281 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
282   return new SIScheduleDAGMI(C);
283 }
284 
285 static ScheduleDAGInstrs *
286 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
287   ScheduleDAGMILive *DAG =
288     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
289   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
290   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
291   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
292   return DAG;
293 }
294 
295 static ScheduleDAGInstrs *
296 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
297   auto DAG = new GCNIterativeScheduler(C,
298     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
299   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
300   return DAG;
301 }
302 
303 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
304   return new GCNIterativeScheduler(C,
305     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
306 }
307 
308 static ScheduleDAGInstrs *
309 createIterativeILPMachineScheduler(MachineSchedContext *C) {
310   auto DAG = new GCNIterativeScheduler(C,
311     GCNIterativeScheduler::SCHEDULE_ILP);
312   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
313   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
314   return DAG;
315 }
316 
317 static MachineSchedRegistry
318 R600SchedRegistry("r600", "Run R600's custom scheduler",
319                    createR600MachineScheduler);
320 
321 static MachineSchedRegistry
322 SISchedRegistry("si", "Run SI's custom scheduler",
323                 createSIMachineScheduler);
324 
325 static MachineSchedRegistry
326 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
327                              "Run GCN scheduler to maximize occupancy",
328                              createGCNMaxOccupancyMachineScheduler);
329 
330 static MachineSchedRegistry
331 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
332   "Run GCN scheduler to maximize occupancy (experimental)",
333   createIterativeGCNMaxOccupancyMachineScheduler);
334 
335 static MachineSchedRegistry
336 GCNMinRegSchedRegistry("gcn-minreg",
337   "Run GCN iterative scheduler for minimal register usage (experimental)",
338   createMinRegScheduler);
339 
340 static MachineSchedRegistry
341 GCNILPSchedRegistry("gcn-ilp",
342   "Run GCN iterative scheduler for ILP scheduling (experimental)",
343   createIterativeILPMachineScheduler);
344 
345 static StringRef computeDataLayout(const Triple &TT) {
346   if (TT.getArch() == Triple::r600) {
347     // 32-bit pointers.
348     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
349            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
350   }
351 
352   // 32-bit private, local, and region pointers. 64-bit global, constant and
353   // flat, non-integral buffer fat pointers.
354   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
355          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
356          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
357          "-ni:7";
358 }
359 
360 LLVM_READNONE
361 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
362   if (!GPU.empty())
363     return GPU;
364 
365   // Need to default to a target with flat support for HSA.
366   if (TT.getArch() == Triple::amdgcn)
367     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
368 
369   return "r600";
370 }
371 
372 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
373   // The AMDGPU toolchain only supports generating shared objects, so we
374   // must always use PIC.
375   return Reloc::PIC_;
376 }
377 
378 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
379                                          StringRef CPU, StringRef FS,
380                                          TargetOptions Options,
381                                          Optional<Reloc::Model> RM,
382                                          Optional<CodeModel::Model> CM,
383                                          CodeGenOpt::Level OptLevel)
384     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
385                         FS, Options, getEffectiveRelocModel(RM),
386                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
387       TLOF(createTLOF(getTargetTriple())) {
388   initAsmInfo();
389   if (TT.getArch() == Triple::amdgcn) {
390     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
391       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
392     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
393       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
394   }
395 }
396 
397 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
398 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
399 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
400 
401 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
402 
403 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
404   Attribute GPUAttr = F.getFnAttribute("target-cpu");
405   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
406 }
407 
408 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
409   Attribute FSAttr = F.getFnAttribute("target-features");
410 
411   return FSAttr.isValid() ? FSAttr.getValueAsString()
412                           : getTargetFeatureString();
413 }
414 
415 /// Predicate for Internalize pass.
416 static bool mustPreserveGV(const GlobalValue &GV) {
417   if (const Function *F = dyn_cast<Function>(&GV))
418     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
419 
420   return !GV.use_empty();
421 }
422 
423 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
424   Builder.DivergentTarget = true;
425 
426   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
427   bool Internalize = InternalizeSymbols;
428   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
429   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
430   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
431 
432   if (EnableFunctionCalls) {
433     delete Builder.Inliner;
434     Builder.Inliner = createAMDGPUFunctionInliningPass();
435   }
436 
437   Builder.addExtension(
438     PassManagerBuilder::EP_ModuleOptimizerEarly,
439     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
440                                                legacy::PassManagerBase &PM) {
441       if (AMDGPUAA) {
442         PM.add(createAMDGPUAAWrapperPass());
443         PM.add(createAMDGPUExternalAAWrapperPass());
444       }
445       PM.add(createAMDGPUUnifyMetadataPass());
446       PM.add(createAMDGPUPrintfRuntimeBinding());
447       if (Internalize)
448         PM.add(createInternalizePass(mustPreserveGV));
449       PM.add(createAMDGPUPropagateAttributesLatePass(this));
450       if (Internalize)
451         PM.add(createGlobalDCEPass());
452       if (EarlyInline)
453         PM.add(createAMDGPUAlwaysInlinePass(false));
454   });
455 
456   Builder.addExtension(
457     PassManagerBuilder::EP_EarlyAsPossible,
458     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
459                                       legacy::PassManagerBase &PM) {
460       if (AMDGPUAA) {
461         PM.add(createAMDGPUAAWrapperPass());
462         PM.add(createAMDGPUExternalAAWrapperPass());
463       }
464       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
465       PM.add(llvm::createAMDGPUUseNativeCallsPass());
466       if (LibCallSimplify)
467         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
468   });
469 
470   Builder.addExtension(
471     PassManagerBuilder::EP_CGSCCOptimizerLate,
472     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
473       // Add infer address spaces pass to the opt pipeline after inlining
474       // but before SROA to increase SROA opportunities.
475       PM.add(createInferAddressSpacesPass());
476 
477       // This should run after inlining to have any chance of doing anything,
478       // and before other cleanup optimizations.
479       PM.add(createAMDGPULowerKernelAttributesPass());
480 
481       // Promote alloca to vector before SROA and loop unroll. If we manage
482       // to eliminate allocas before unroll we may choose to unroll less.
483       if (EnableOpt)
484         PM.add(createAMDGPUPromoteAllocaToVector());
485   });
486 }
487 
488 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
489                                                        bool DebugPassManager) {
490   PB.registerPipelineParsingCallback(
491       [](StringRef PassName, FunctionPassManager &PM,
492          ArrayRef<PassBuilder::PipelineElement>) {
493         if (PassName == "amdgpu-simplifylib") {
494           PM.addPass(AMDGPUSimplifyLibCallsPass());
495           return true;
496         }
497         if (PassName == "amdgpu-usenative") {
498           PM.addPass(AMDGPUUseNativeCallsPass());
499           return true;
500         }
501         return false;
502       });
503 
504   PB.registerPipelineStartEPCallback([DebugPassManager](
505                                          ModulePassManager &PM,
506                                          PassBuilder::OptimizationLevel Level) {
507     FunctionPassManager FPM(DebugPassManager);
508     FPM.addPass(AMDGPUUseNativeCallsPass());
509     if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
510       FPM.addPass(AMDGPUSimplifyLibCallsPass());
511     PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
512   });
513 }
514 
515 //===----------------------------------------------------------------------===//
516 // R600 Target Machine (R600 -> Cayman)
517 //===----------------------------------------------------------------------===//
518 
519 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
520                                      StringRef CPU, StringRef FS,
521                                      TargetOptions Options,
522                                      Optional<Reloc::Model> RM,
523                                      Optional<CodeModel::Model> CM,
524                                      CodeGenOpt::Level OL, bool JIT)
525     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
526   setRequiresStructuredCFG(true);
527 
528   // Override the default since calls aren't supported for r600.
529   if (EnableFunctionCalls &&
530       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
531     EnableFunctionCalls = false;
532 }
533 
534 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
535   const Function &F) const {
536   StringRef GPU = getGPUName(F);
537   StringRef FS = getFeatureString(F);
538 
539   SmallString<128> SubtargetKey(GPU);
540   SubtargetKey.append(FS);
541 
542   auto &I = SubtargetMap[SubtargetKey];
543   if (!I) {
544     // This needs to be done before we create a new subtarget since any
545     // creation will depend on the TM and the code generation flags on the
546     // function that reside in TargetOptions.
547     resetTargetOptions(F);
548     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
549   }
550 
551   return I.get();
552 }
553 
554 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
555                                               unsigned DestAS) const {
556   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
557          AMDGPU::isFlatGlobalAddrSpace(DestAS);
558 }
559 
560 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
561   const auto *LD = dyn_cast<LoadInst>(V);
562   if (!LD)
563     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
564 
565   // It must be a generic pointer loaded.
566   assert(V->getType()->isPointerTy() &&
567          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
568 
569   const auto *Ptr = LD->getPointerOperand();
570   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
571     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
572   // For a generic pointer loaded from the constant memory, it could be assumed
573   // as a global pointer since the constant memory is only populated on the
574   // host side. As implied by the offload programming model, only global
575   // pointers could be referenced on the host side.
576   return AMDGPUAS::GLOBAL_ADDRESS;
577 }
578 
579 TargetTransformInfo
580 R600TargetMachine::getTargetTransformInfo(const Function &F) {
581   return TargetTransformInfo(R600TTIImpl(this, F));
582 }
583 
584 //===----------------------------------------------------------------------===//
585 // GCN Target Machine (SI+)
586 //===----------------------------------------------------------------------===//
587 
588 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
589                                    StringRef CPU, StringRef FS,
590                                    TargetOptions Options,
591                                    Optional<Reloc::Model> RM,
592                                    Optional<CodeModel::Model> CM,
593                                    CodeGenOpt::Level OL, bool JIT)
594     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
595 
596 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
597   StringRef GPU = getGPUName(F);
598   StringRef FS = getFeatureString(F);
599 
600   SmallString<128> SubtargetKey(GPU);
601   SubtargetKey.append(FS);
602 
603   auto &I = SubtargetMap[SubtargetKey];
604   if (!I) {
605     // This needs to be done before we create a new subtarget since any
606     // creation will depend on the TM and the code generation flags on the
607     // function that reside in TargetOptions.
608     resetTargetOptions(F);
609     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
610   }
611 
612   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
613 
614   return I.get();
615 }
616 
617 TargetTransformInfo
618 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
619   return TargetTransformInfo(GCNTTIImpl(this, F));
620 }
621 
622 //===----------------------------------------------------------------------===//
623 // AMDGPU Pass Setup
624 //===----------------------------------------------------------------------===//
625 
626 namespace {
627 
628 class AMDGPUPassConfig : public TargetPassConfig {
629 public:
630   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
631     : TargetPassConfig(TM, PM) {
632     // Exceptions and StackMaps are not supported, so these passes will never do
633     // anything.
634     disablePass(&StackMapLivenessID);
635     disablePass(&FuncletLayoutID);
636   }
637 
638   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
639     return getTM<AMDGPUTargetMachine>();
640   }
641 
642   ScheduleDAGInstrs *
643   createMachineScheduler(MachineSchedContext *C) const override {
644     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
645     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
646     return DAG;
647   }
648 
649   void addEarlyCSEOrGVNPass();
650   void addStraightLineScalarOptimizationPasses();
651   void addIRPasses() override;
652   void addCodeGenPrepare() override;
653   bool addPreISel() override;
654   bool addInstSelector() override;
655   bool addGCPasses() override;
656 
657   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
658 };
659 
660 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
661   return getStandardCSEConfigForOpt(TM->getOptLevel());
662 }
663 
664 class R600PassConfig final : public AMDGPUPassConfig {
665 public:
666   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
667     : AMDGPUPassConfig(TM, PM) {}
668 
669   ScheduleDAGInstrs *createMachineScheduler(
670     MachineSchedContext *C) const override {
671     return createR600MachineScheduler(C);
672   }
673 
674   bool addPreISel() override;
675   bool addInstSelector() override;
676   void addPreRegAlloc() override;
677   void addPreSched2() override;
678   void addPreEmitPass() override;
679 };
680 
681 class GCNPassConfig final : public AMDGPUPassConfig {
682 public:
683   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
684     : AMDGPUPassConfig(TM, PM) {
685     // It is necessary to know the register usage of the entire call graph.  We
686     // allow calls without EnableAMDGPUFunctionCalls if they are marked
687     // noinline, so this is always required.
688     setRequiresCodeGenSCCOrder(true);
689   }
690 
691   GCNTargetMachine &getGCNTargetMachine() const {
692     return getTM<GCNTargetMachine>();
693   }
694 
695   ScheduleDAGInstrs *
696   createMachineScheduler(MachineSchedContext *C) const override;
697 
698   bool addPreISel() override;
699   void addMachineSSAOptimization() override;
700   bool addILPOpts() override;
701   bool addInstSelector() override;
702   bool addIRTranslator() override;
703   void addPreLegalizeMachineIR() override;
704   bool addLegalizeMachineIR() override;
705   void addPreRegBankSelect() override;
706   bool addRegBankSelect() override;
707   bool addGlobalInstructionSelect() override;
708   void addFastRegAlloc() override;
709   void addOptimizedRegAlloc() override;
710   void addPreRegAlloc() override;
711   bool addPreRewrite() override;
712   void addPostRegAlloc() override;
713   void addPreSched2() override;
714   void addPreEmitPass() override;
715 };
716 
717 } // end anonymous namespace
718 
719 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
720   if (getOptLevel() == CodeGenOpt::Aggressive)
721     addPass(createGVNPass());
722   else
723     addPass(createEarlyCSEPass());
724 }
725 
726 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
727   addPass(createLICMPass());
728   addPass(createSeparateConstOffsetFromGEPPass());
729   addPass(createSpeculativeExecutionPass());
730   // ReassociateGEPs exposes more opportunites for SLSR. See
731   // the example in reassociate-geps-and-slsr.ll.
732   addPass(createStraightLineStrengthReducePass());
733   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
734   // EarlyCSE can reuse.
735   addEarlyCSEOrGVNPass();
736   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
737   addPass(createNaryReassociatePass());
738   // NaryReassociate on GEPs creates redundant common expressions, so run
739   // EarlyCSE after it.
740   addPass(createEarlyCSEPass());
741 }
742 
743 void AMDGPUPassConfig::addIRPasses() {
744   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
745 
746   // There is no reason to run these.
747   disablePass(&StackMapLivenessID);
748   disablePass(&FuncletLayoutID);
749   disablePass(&PatchableFunctionID);
750 
751   addPass(createAMDGPUPrintfRuntimeBinding());
752 
753   // This must occur before inlining, as the inliner will not look through
754   // bitcast calls.
755   addPass(createAMDGPUFixFunctionBitcastsPass());
756 
757   // A call to propagate attributes pass in the backend in case opt was not run.
758   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
759 
760   addPass(createAtomicExpandPass());
761 
762 
763   addPass(createAMDGPULowerIntrinsicsPass());
764 
765   // Function calls are not supported, so make sure we inline everything.
766   addPass(createAMDGPUAlwaysInlinePass());
767   addPass(createAlwaysInlinerLegacyPass());
768   // We need to add the barrier noop pass, otherwise adding the function
769   // inlining pass will cause all of the PassConfigs passes to be run
770   // one function at a time, which means if we have a nodule with two
771   // functions, then we will generate code for the first function
772   // without ever running any passes on the second.
773   addPass(createBarrierNoopPass());
774 
775   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
776   if (TM.getTargetTriple().getArch() == Triple::r600)
777     addPass(createR600OpenCLImageTypeLoweringPass());
778 
779   // Replace OpenCL enqueued block function pointers with global variables.
780   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
781 
782   if (TM.getOptLevel() > CodeGenOpt::None) {
783     addPass(createInferAddressSpacesPass());
784     addPass(createAMDGPUPromoteAlloca());
785 
786     if (EnableSROA)
787       addPass(createSROAPass());
788 
789     if (EnableScalarIRPasses)
790       addStraightLineScalarOptimizationPasses();
791 
792     if (EnableAMDGPUAliasAnalysis) {
793       addPass(createAMDGPUAAWrapperPass());
794       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
795                                              AAResults &AAR) {
796         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
797           AAR.addAAResult(WrapperPass->getResult());
798         }));
799     }
800   }
801 
802   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
803     // TODO: May want to move later or split into an early and late one.
804     addPass(createAMDGPUCodeGenPreparePass());
805   }
806 
807   TargetPassConfig::addIRPasses();
808 
809   // EarlyCSE is not always strong enough to clean up what LSR produces. For
810   // example, GVN can combine
811   //
812   //   %0 = add %a, %b
813   //   %1 = add %b, %a
814   //
815   // and
816   //
817   //   %0 = shl nsw %a, 2
818   //   %1 = shl %a, 2
819   //
820   // but EarlyCSE can do neither of them.
821   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
822     addEarlyCSEOrGVNPass();
823 }
824 
825 void AMDGPUPassConfig::addCodeGenPrepare() {
826   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
827     addPass(createAMDGPUAnnotateKernelFeaturesPass());
828 
829   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
830       EnableLowerKernelArguments)
831     addPass(createAMDGPULowerKernelArgumentsPass());
832 
833   addPass(&AMDGPUPerfHintAnalysisID);
834 
835   TargetPassConfig::addCodeGenPrepare();
836 
837   if (EnableLoadStoreVectorizer)
838     addPass(createLoadStoreVectorizerPass());
839 
840   // LowerSwitch pass may introduce unreachable blocks that can
841   // cause unexpected behavior for subsequent passes. Placing it
842   // here seems better that these blocks would get cleaned up by
843   // UnreachableBlockElim inserted next in the pass flow.
844   addPass(createLowerSwitchPass());
845 }
846 
847 bool AMDGPUPassConfig::addPreISel() {
848   addPass(createFlattenCFGPass());
849   return false;
850 }
851 
852 bool AMDGPUPassConfig::addInstSelector() {
853   // Defer the verifier until FinalizeISel.
854   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
855   return false;
856 }
857 
858 bool AMDGPUPassConfig::addGCPasses() {
859   // Do nothing. GC is not supported.
860   return false;
861 }
862 
863 //===----------------------------------------------------------------------===//
864 // R600 Pass Setup
865 //===----------------------------------------------------------------------===//
866 
867 bool R600PassConfig::addPreISel() {
868   AMDGPUPassConfig::addPreISel();
869 
870   if (EnableR600StructurizeCFG)
871     addPass(createStructurizeCFGPass());
872   return false;
873 }
874 
875 bool R600PassConfig::addInstSelector() {
876   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
877   return false;
878 }
879 
880 void R600PassConfig::addPreRegAlloc() {
881   addPass(createR600VectorRegMerger());
882 }
883 
884 void R600PassConfig::addPreSched2() {
885   addPass(createR600EmitClauseMarkers(), false);
886   if (EnableR600IfConvert)
887     addPass(&IfConverterID, false);
888   addPass(createR600ClauseMergePass(), false);
889 }
890 
891 void R600PassConfig::addPreEmitPass() {
892   addPass(createAMDGPUCFGStructurizerPass(), false);
893   addPass(createR600ExpandSpecialInstrsPass(), false);
894   addPass(&FinalizeMachineBundlesID, false);
895   addPass(createR600Packetizer(), false);
896   addPass(createR600ControlFlowFinalizer(), false);
897 }
898 
899 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
900   return new R600PassConfig(*this, PM);
901 }
902 
903 //===----------------------------------------------------------------------===//
904 // GCN Pass Setup
905 //===----------------------------------------------------------------------===//
906 
907 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
908   MachineSchedContext *C) const {
909   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
910   if (ST.enableSIScheduler())
911     return createSIMachineScheduler(C);
912   return createGCNMaxOccupancyMachineScheduler(C);
913 }
914 
915 bool GCNPassConfig::addPreISel() {
916   AMDGPUPassConfig::addPreISel();
917 
918   addPass(createAMDGPULateCodeGenPreparePass());
919   if (EnableAtomicOptimizations) {
920     addPass(createAMDGPUAtomicOptimizerPass());
921   }
922 
923   // FIXME: We need to run a pass to propagate the attributes when calls are
924   // supported.
925 
926   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
927   // regions formed by them.
928   addPass(&AMDGPUUnifyDivergentExitNodesID);
929   if (!LateCFGStructurize) {
930     if (EnableStructurizerWorkarounds) {
931       addPass(createFixIrreduciblePass());
932       addPass(createUnifyLoopExitsPass());
933     }
934     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
935   }
936   addPass(createSinkingPass());
937   addPass(createAMDGPUAnnotateUniformValues());
938   if (!LateCFGStructurize) {
939     addPass(createSIAnnotateControlFlowPass());
940   }
941   addPass(createLCSSAPass());
942 
943   return false;
944 }
945 
946 void GCNPassConfig::addMachineSSAOptimization() {
947   TargetPassConfig::addMachineSSAOptimization();
948 
949   // We want to fold operands after PeepholeOptimizer has run (or as part of
950   // it), because it will eliminate extra copies making it easier to fold the
951   // real source operand. We want to eliminate dead instructions after, so that
952   // we see fewer uses of the copies. We then need to clean up the dead
953   // instructions leftover after the operands are folded as well.
954   //
955   // XXX - Can we get away without running DeadMachineInstructionElim again?
956   addPass(&SIFoldOperandsID);
957   if (EnableDPPCombine)
958     addPass(&GCNDPPCombineID);
959   addPass(&DeadMachineInstructionElimID);
960   addPass(&SILoadStoreOptimizerID);
961   if (EnableSDWAPeephole) {
962     addPass(&SIPeepholeSDWAID);
963     addPass(&EarlyMachineLICMID);
964     addPass(&MachineCSEID);
965     addPass(&SIFoldOperandsID);
966     addPass(&DeadMachineInstructionElimID);
967   }
968   addPass(createSIShrinkInstructionsPass());
969 }
970 
971 bool GCNPassConfig::addILPOpts() {
972   if (EnableEarlyIfConversion)
973     addPass(&EarlyIfConverterID);
974 
975   TargetPassConfig::addILPOpts();
976   return false;
977 }
978 
979 bool GCNPassConfig::addInstSelector() {
980   AMDGPUPassConfig::addInstSelector();
981   addPass(&SIFixSGPRCopiesID);
982   addPass(createSILowerI1CopiesPass());
983   addPass(createSIAddIMGInitPass());
984   return false;
985 }
986 
987 bool GCNPassConfig::addIRTranslator() {
988   addPass(new IRTranslator(getOptLevel()));
989   return false;
990 }
991 
992 void GCNPassConfig::addPreLegalizeMachineIR() {
993   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
994   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
995   addPass(new Localizer());
996 }
997 
998 bool GCNPassConfig::addLegalizeMachineIR() {
999   addPass(new Legalizer());
1000   return false;
1001 }
1002 
1003 void GCNPassConfig::addPreRegBankSelect() {
1004   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1005   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1006 }
1007 
1008 bool GCNPassConfig::addRegBankSelect() {
1009   addPass(new RegBankSelect());
1010   return false;
1011 }
1012 
1013 bool GCNPassConfig::addGlobalInstructionSelect() {
1014   addPass(new InstructionSelect());
1015   return false;
1016 }
1017 
1018 void GCNPassConfig::addPreRegAlloc() {
1019   if (LateCFGStructurize) {
1020     addPass(createAMDGPUMachineCFGStructurizerPass());
1021   }
1022 }
1023 
1024 void GCNPassConfig::addFastRegAlloc() {
1025   // FIXME: We have to disable the verifier here because of PHIElimination +
1026   // TwoAddressInstructions disabling it.
1027 
1028   // This must be run immediately after phi elimination and before
1029   // TwoAddressInstructions, otherwise the processing of the tied operand of
1030   // SI_ELSE will introduce a copy of the tied operand source after the else.
1031   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1032 
1033   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1034   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1035 
1036   TargetPassConfig::addFastRegAlloc();
1037 }
1038 
1039 void GCNPassConfig::addOptimizedRegAlloc() {
1040   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1041   // instructions that cause scheduling barriers.
1042   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1043   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1044 
1045   if (OptExecMaskPreRA)
1046     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1047   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1048 
1049   // This must be run immediately after phi elimination and before
1050   // TwoAddressInstructions, otherwise the processing of the tied operand of
1051   // SI_ELSE will introduce a copy of the tied operand source after the else.
1052   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1053 
1054   if (EnableDCEInRA)
1055     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1056 
1057   TargetPassConfig::addOptimizedRegAlloc();
1058 }
1059 
1060 bool GCNPassConfig::addPreRewrite() {
1061   if (EnableRegReassign) {
1062     addPass(&GCNNSAReassignID);
1063     addPass(&GCNRegBankReassignID);
1064   }
1065   return true;
1066 }
1067 
1068 void GCNPassConfig::addPostRegAlloc() {
1069   addPass(&SIFixVGPRCopiesID);
1070   if (getOptLevel() > CodeGenOpt::None)
1071     addPass(&SIOptimizeExecMaskingID);
1072   TargetPassConfig::addPostRegAlloc();
1073 
1074   // Equivalent of PEI for SGPRs.
1075   addPass(&SILowerSGPRSpillsID);
1076 }
1077 
1078 void GCNPassConfig::addPreSched2() {
1079   addPass(&SIPostRABundlerID);
1080 }
1081 
1082 void GCNPassConfig::addPreEmitPass() {
1083   addPass(createSIMemoryLegalizerPass());
1084   addPass(createSIInsertWaitcntsPass());
1085   addPass(createSIShrinkInstructionsPass());
1086   addPass(createSIModeRegisterPass());
1087 
1088   if (getOptLevel() > CodeGenOpt::None)
1089     addPass(&SIInsertHardClausesID);
1090 
1091   addPass(&SIRemoveShortExecBranchesID);
1092   addPass(&SIInsertSkipsPassID);
1093   addPass(&SIPreEmitPeepholeID);
1094   // The hazard recognizer that runs as part of the post-ra scheduler does not
1095   // guarantee to be able handle all hazards correctly. This is because if there
1096   // are multiple scheduling regions in a basic block, the regions are scheduled
1097   // bottom up, so when we begin to schedule a region we don't know what
1098   // instructions were emitted directly before it.
1099   //
1100   // Here we add a stand-alone hazard recognizer pass which can handle all
1101   // cases.
1102   addPass(&PostRAHazardRecognizerID);
1103   addPass(&BranchRelaxationPassID);
1104 }
1105 
1106 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1107   return new GCNPassConfig(*this, PM);
1108 }
1109 
1110 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1111   return new yaml::SIMachineFunctionInfo();
1112 }
1113 
1114 yaml::MachineFunctionInfo *
1115 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1116   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1117   return new yaml::SIMachineFunctionInfo(*MFI,
1118                                          *MF.getSubtarget().getRegisterInfo());
1119 }
1120 
1121 bool GCNTargetMachine::parseMachineFunctionInfo(
1122     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1123     SMDiagnostic &Error, SMRange &SourceRange) const {
1124   const yaml::SIMachineFunctionInfo &YamlMFI =
1125       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1126   MachineFunction &MF = PFS.MF;
1127   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1128 
1129   MFI->initializeBaseYamlFields(YamlMFI);
1130 
1131   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1132     Register TempReg;
1133     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1134       SourceRange = RegName.SourceRange;
1135       return true;
1136     }
1137     RegVal = TempReg;
1138 
1139     return false;
1140   };
1141 
1142   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1143     // Create a diagnostic for a the register string literal.
1144     const MemoryBuffer &Buffer =
1145         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1146     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1147                          RegName.Value.size(), SourceMgr::DK_Error,
1148                          "incorrect register class for field", RegName.Value,
1149                          None, None);
1150     SourceRange = RegName.SourceRange;
1151     return true;
1152   };
1153 
1154   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1155       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1156       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1157     return true;
1158 
1159   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1160       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1161     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1162   }
1163 
1164   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1165       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1166     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1167   }
1168 
1169   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1170       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1171     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1172   }
1173 
1174   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1175                                    const TargetRegisterClass &RC,
1176                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1177                                    unsigned SystemSGPRs) {
1178     // Skip parsing if it's not present.
1179     if (!A)
1180       return false;
1181 
1182     if (A->IsRegister) {
1183       Register Reg;
1184       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1185         SourceRange = A->RegisterName.SourceRange;
1186         return true;
1187       }
1188       if (!RC.contains(Reg))
1189         return diagnoseRegisterClass(A->RegisterName);
1190       Arg = ArgDescriptor::createRegister(Reg);
1191     } else
1192       Arg = ArgDescriptor::createStack(A->StackOffset);
1193     // Check and apply the optional mask.
1194     if (A->Mask)
1195       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1196 
1197     MFI->NumUserSGPRs += UserSGPRs;
1198     MFI->NumSystemSGPRs += SystemSGPRs;
1199     return false;
1200   };
1201 
1202   if (YamlMFI.ArgInfo &&
1203       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1204                              AMDGPU::SGPR_128RegClass,
1205                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1206        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1207                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1208                              2, 0) ||
1209        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1210                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1211        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1212                              AMDGPU::SReg_64RegClass,
1213                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1214        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1215                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1216                              2, 0) ||
1217        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1218                              AMDGPU::SReg_64RegClass,
1219                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1220        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1221                              AMDGPU::SGPR_32RegClass,
1222                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1223        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1224                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1225                              0, 1) ||
1226        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1227                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1228                              0, 1) ||
1229        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1230                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1231                              0, 1) ||
1232        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1233                              AMDGPU::SGPR_32RegClass,
1234                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1235        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1236                              AMDGPU::SGPR_32RegClass,
1237                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1238        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1239                              AMDGPU::SReg_64RegClass,
1240                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1241        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1242                              AMDGPU::SReg_64RegClass,
1243                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1244        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1245                              AMDGPU::VGPR_32RegClass,
1246                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1247        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1248                              AMDGPU::VGPR_32RegClass,
1249                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1250        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1251                              AMDGPU::VGPR_32RegClass,
1252                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1253     return true;
1254 
1255   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1256   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1257   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1258   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1259   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1260   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1261 
1262   return false;
1263 }
1264