1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110   cl::desc("Enable AMDGPU Alias Analysis"),
111   cl::init(true));
112 
113 // Option to enable new waitcnt insertion pass.
114 static cl::opt<bool> EnableSIInsertWaitcntsPass(
115   "enable-si-insert-waitcnts",
116   cl::desc("Use new waitcnt insertion pass"),
117   cl::init(true));
118 
119 // Option to run late CFG structurizer
120 static cl::opt<bool, true> LateCFGStructurize(
121   "amdgpu-late-structurize",
122   cl::desc("Enable late CFG structurization"),
123   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
124   cl::Hidden);
125 
126 static cl::opt<bool> EnableAMDGPUFunctionCalls(
127   "amdgpu-function-calls",
128   cl::Hidden,
129   cl::desc("Enable AMDGPU function call support"),
130   cl::init(false));
131 
132 // Enable lib calls simplifications
133 static cl::opt<bool> EnableLibCallSimplify(
134   "amdgpu-simplify-libcall",
135   cl::desc("Enable mdgpu library simplifications"),
136   cl::init(true),
137   cl::Hidden);
138 
139 extern "C" void LLVMInitializeAMDGPUTarget() {
140   // Register the target
141   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
142   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
143 
144   PassRegistry *PR = PassRegistry::getPassRegistry();
145   initializeR600ClauseMergePassPass(*PR);
146   initializeR600ControlFlowFinalizerPass(*PR);
147   initializeR600PacketizerPass(*PR);
148   initializeR600ExpandSpecialInstrsPassPass(*PR);
149   initializeR600VectorRegMergerPass(*PR);
150   initializeGlobalISel(*PR);
151   initializeAMDGPUDAGToDAGISelPass(*PR);
152   initializeSILowerI1CopiesPass(*PR);
153   initializeSIFixSGPRCopiesPass(*PR);
154   initializeSIFixVGPRCopiesPass(*PR);
155   initializeSIFoldOperandsPass(*PR);
156   initializeSIPeepholeSDWAPass(*PR);
157   initializeSIShrinkInstructionsPass(*PR);
158   initializeSIOptimizeExecMaskingPreRAPass(*PR);
159   initializeSILoadStoreOptimizerPass(*PR);
160   initializeAMDGPUAlwaysInlinePass(*PR);
161   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
162   initializeAMDGPUAnnotateUniformValuesPass(*PR);
163   initializeAMDGPUArgumentUsageInfoPass(*PR);
164   initializeAMDGPULowerIntrinsicsPass(*PR);
165   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
166   initializeAMDGPUPromoteAllocaPass(*PR);
167   initializeAMDGPUCodeGenPreparePass(*PR);
168   initializeAMDGPURewriteOutArgumentsPass(*PR);
169   initializeAMDGPUUnifyMetadataPass(*PR);
170   initializeSIAnnotateControlFlowPass(*PR);
171   initializeSIInsertWaitcntsPass(*PR);
172   initializeSIWholeQuadModePass(*PR);
173   initializeSILowerControlFlowPass(*PR);
174   initializeSIInsertSkipsPass(*PR);
175   initializeSIMemoryLegalizerPass(*PR);
176   initializeSIDebuggerInsertNopsPass(*PR);
177   initializeSIOptimizeExecMaskingPass(*PR);
178   initializeSIFixWWMLivenessPass(*PR);
179   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
180   initializeAMDGPUAAWrapperPassPass(*PR);
181   initializeAMDGPUUseNativeCallsPass(*PR);
182   initializeAMDGPUSimplifyLibCallsPass(*PR);
183   initializeAMDGPUInlinerPass(*PR);
184 }
185 
186 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
187   return llvm::make_unique<AMDGPUTargetObjectFile>();
188 }
189 
190 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
191   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
192 }
193 
194 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
195   return new SIScheduleDAGMI(C);
196 }
197 
198 static ScheduleDAGInstrs *
199 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
200   ScheduleDAGMILive *DAG =
201     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
202   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
203   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
204   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
205   return DAG;
206 }
207 
208 static ScheduleDAGInstrs *
209 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
210   auto DAG = new GCNIterativeScheduler(C,
211     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
212   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
213   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
214   return DAG;
215 }
216 
217 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
218   return new GCNIterativeScheduler(C,
219     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
220 }
221 
222 static ScheduleDAGInstrs *
223 createIterativeILPMachineScheduler(MachineSchedContext *C) {
224   auto DAG = new GCNIterativeScheduler(C,
225     GCNIterativeScheduler::SCHEDULE_ILP);
226   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
227   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
228   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
229   return DAG;
230 }
231 
232 static MachineSchedRegistry
233 R600SchedRegistry("r600", "Run R600's custom scheduler",
234                    createR600MachineScheduler);
235 
236 static MachineSchedRegistry
237 SISchedRegistry("si", "Run SI's custom scheduler",
238                 createSIMachineScheduler);
239 
240 static MachineSchedRegistry
241 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
242                              "Run GCN scheduler to maximize occupancy",
243                              createGCNMaxOccupancyMachineScheduler);
244 
245 static MachineSchedRegistry
246 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
247   "Run GCN scheduler to maximize occupancy (experimental)",
248   createIterativeGCNMaxOccupancyMachineScheduler);
249 
250 static MachineSchedRegistry
251 GCNMinRegSchedRegistry("gcn-minreg",
252   "Run GCN iterative scheduler for minimal register usage (experimental)",
253   createMinRegScheduler);
254 
255 static MachineSchedRegistry
256 GCNILPSchedRegistry("gcn-ilp",
257   "Run GCN iterative scheduler for ILP scheduling (experimental)",
258   createIterativeILPMachineScheduler);
259 
260 static StringRef computeDataLayout(const Triple &TT) {
261   if (TT.getArch() == Triple::r600) {
262     // 32-bit pointers.
263       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
264              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
265   }
266 
267   // 32-bit private, local, and region pointers. 64-bit global, constant and
268   // flat.
269     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
270          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
271          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
272 }
273 
274 LLVM_READNONE
275 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
276   if (!GPU.empty())
277     return GPU;
278 
279   if (TT.getArch() == Triple::amdgcn)
280     return "generic";
281 
282   return "r600";
283 }
284 
285 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
286   // The AMDGPU toolchain only supports generating shared objects, so we
287   // must always use PIC.
288   return Reloc::PIC_;
289 }
290 
291 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
292   if (CM)
293     return *CM;
294   return CodeModel::Small;
295 }
296 
297 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
298                                          StringRef CPU, StringRef FS,
299                                          TargetOptions Options,
300                                          Optional<Reloc::Model> RM,
301                                          Optional<CodeModel::Model> CM,
302                                          CodeGenOpt::Level OptLevel)
303     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
304                         FS, Options, getEffectiveRelocModel(RM),
305                         getEffectiveCodeModel(CM), OptLevel),
306       TLOF(createTLOF(getTargetTriple())) {
307   AS = AMDGPU::getAMDGPUAS(TT);
308   initAsmInfo();
309 }
310 
311 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
312 
313 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
314 
315 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
316   Attribute GPUAttr = F.getFnAttribute("target-cpu");
317   return GPUAttr.hasAttribute(Attribute::None) ?
318     getTargetCPU() : GPUAttr.getValueAsString();
319 }
320 
321 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
322   Attribute FSAttr = F.getFnAttribute("target-features");
323 
324   return FSAttr.hasAttribute(Attribute::None) ?
325     getTargetFeatureString() :
326     FSAttr.getValueAsString();
327 }
328 
329 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
330   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
331       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
332         AAR.addAAResult(WrapperPass->getResult());
333       });
334 }
335 
336 /// Predicate for Internalize pass.
337 static bool mustPreserveGV(const GlobalValue &GV) {
338   if (const Function *F = dyn_cast<Function>(&GV))
339     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
340 
341   return !GV.use_empty();
342 }
343 
344 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
345   Builder.DivergentTarget = true;
346 
347   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
348   bool Internalize = InternalizeSymbols;
349   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
350   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
351   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
352 
353   if (EnableAMDGPUFunctionCalls) {
354     delete Builder.Inliner;
355     Builder.Inliner = createAMDGPUFunctionInliningPass();
356   }
357 
358   if (Internalize) {
359     // If we're generating code, we always have the whole program available. The
360     // relocations expected for externally visible functions aren't supported,
361     // so make sure every non-entry function is hidden.
362     Builder.addExtension(
363       PassManagerBuilder::EP_EnabledOnOptLevel0,
364       [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
365         PM.add(createInternalizePass(mustPreserveGV));
366       });
367   }
368 
369   Builder.addExtension(
370     PassManagerBuilder::EP_ModuleOptimizerEarly,
371     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
372                                          legacy::PassManagerBase &PM) {
373       if (AMDGPUAA) {
374         PM.add(createAMDGPUAAWrapperPass());
375         PM.add(createAMDGPUExternalAAWrapperPass());
376       }
377       PM.add(createAMDGPUUnifyMetadataPass());
378       if (Internalize) {
379         PM.add(createInternalizePass(mustPreserveGV));
380         PM.add(createGlobalDCEPass());
381       }
382       if (EarlyInline)
383         PM.add(createAMDGPUAlwaysInlinePass(false));
384   });
385 
386   const auto &Opt = Options;
387   Builder.addExtension(
388     PassManagerBuilder::EP_EarlyAsPossible,
389     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
390                                       legacy::PassManagerBase &PM) {
391       if (AMDGPUAA) {
392         PM.add(createAMDGPUAAWrapperPass());
393         PM.add(createAMDGPUExternalAAWrapperPass());
394       }
395       PM.add(llvm::createAMDGPUUseNativeCallsPass());
396       if (LibCallSimplify)
397         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
398   });
399 
400   Builder.addExtension(
401     PassManagerBuilder::EP_CGSCCOptimizerLate,
402     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
403       // Add infer address spaces pass to the opt pipeline after inlining
404       // but before SROA to increase SROA opportunities.
405       PM.add(createInferAddressSpacesPass());
406   });
407 }
408 
409 //===----------------------------------------------------------------------===//
410 // R600 Target Machine (R600 -> Cayman)
411 //===----------------------------------------------------------------------===//
412 
413 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
414                                      StringRef CPU, StringRef FS,
415                                      TargetOptions Options,
416                                      Optional<Reloc::Model> RM,
417                                      Optional<CodeModel::Model> CM,
418                                      CodeGenOpt::Level OL, bool JIT)
419     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
420   setRequiresStructuredCFG(true);
421 }
422 
423 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
424   const Function &F) const {
425   StringRef GPU = getGPUName(F);
426   StringRef FS = getFeatureString(F);
427 
428   SmallString<128> SubtargetKey(GPU);
429   SubtargetKey.append(FS);
430 
431   auto &I = SubtargetMap[SubtargetKey];
432   if (!I) {
433     // This needs to be done before we create a new subtarget since any
434     // creation will depend on the TM and the code generation flags on the
435     // function that reside in TargetOptions.
436     resetTargetOptions(F);
437     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
438   }
439 
440   return I.get();
441 }
442 
443 //===----------------------------------------------------------------------===//
444 // GCN Target Machine (SI+)
445 //===----------------------------------------------------------------------===//
446 
447 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
448                                    StringRef CPU, StringRef FS,
449                                    TargetOptions Options,
450                                    Optional<Reloc::Model> RM,
451                                    Optional<CodeModel::Model> CM,
452                                    CodeGenOpt::Level OL, bool JIT)
453     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
454 
455 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
456   StringRef GPU = getGPUName(F);
457   StringRef FS = getFeatureString(F);
458 
459   SmallString<128> SubtargetKey(GPU);
460   SubtargetKey.append(FS);
461 
462   auto &I = SubtargetMap[SubtargetKey];
463   if (!I) {
464     // This needs to be done before we create a new subtarget since any
465     // creation will depend on the TM and the code generation flags on the
466     // function that reside in TargetOptions.
467     resetTargetOptions(F);
468     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
469   }
470 
471   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
472 
473   return I.get();
474 }
475 
476 //===----------------------------------------------------------------------===//
477 // AMDGPU Pass Setup
478 //===----------------------------------------------------------------------===//
479 
480 namespace {
481 
482 class AMDGPUPassConfig : public TargetPassConfig {
483 public:
484   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
485     : TargetPassConfig(TM, PM) {
486     // Exceptions and StackMaps are not supported, so these passes will never do
487     // anything.
488     disablePass(&StackMapLivenessID);
489     disablePass(&FuncletLayoutID);
490   }
491 
492   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
493     return getTM<AMDGPUTargetMachine>();
494   }
495 
496   ScheduleDAGInstrs *
497   createMachineScheduler(MachineSchedContext *C) const override {
498     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
499     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
500     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
501     return DAG;
502   }
503 
504   void addEarlyCSEOrGVNPass();
505   void addStraightLineScalarOptimizationPasses();
506   void addIRPasses() override;
507   void addCodeGenPrepare() override;
508   bool addPreISel() override;
509   bool addInstSelector() override;
510   bool addGCPasses() override;
511 };
512 
513 class R600PassConfig final : public AMDGPUPassConfig {
514 public:
515   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
516     : AMDGPUPassConfig(TM, PM) {}
517 
518   ScheduleDAGInstrs *createMachineScheduler(
519     MachineSchedContext *C) const override {
520     return createR600MachineScheduler(C);
521   }
522 
523   bool addPreISel() override;
524   bool addInstSelector() override;
525   void addPreRegAlloc() override;
526   void addPreSched2() override;
527   void addPreEmitPass() override;
528 };
529 
530 class GCNPassConfig final : public AMDGPUPassConfig {
531 public:
532   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
533     : AMDGPUPassConfig(TM, PM) {
534     // It is necessary to know the register usage of the entire call graph.  We
535     // allow calls without EnableAMDGPUFunctionCalls if they are marked
536     // noinline, so this is always required.
537     setRequiresCodeGenSCCOrder(true);
538   }
539 
540   GCNTargetMachine &getGCNTargetMachine() const {
541     return getTM<GCNTargetMachine>();
542   }
543 
544   ScheduleDAGInstrs *
545   createMachineScheduler(MachineSchedContext *C) const override;
546 
547   bool addPreISel() override;
548   void addMachineSSAOptimization() override;
549   bool addILPOpts() override;
550   bool addInstSelector() override;
551   bool addIRTranslator() override;
552   bool addLegalizeMachineIR() override;
553   bool addRegBankSelect() override;
554   bool addGlobalInstructionSelect() override;
555   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
556   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
557   void addPreRegAlloc() override;
558   void addPostRegAlloc() override;
559   void addPreSched2() override;
560   void addPreEmitPass() override;
561 };
562 
563 } // end anonymous namespace
564 
565 TargetTransformInfo
566 AMDGPUTargetMachine::getTargetTransformInfo(const Function &F) {
567   return TargetTransformInfo(AMDGPUTTIImpl(this, F));
568 }
569 
570 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
571   if (getOptLevel() == CodeGenOpt::Aggressive)
572     addPass(createGVNPass());
573   else
574     addPass(createEarlyCSEPass());
575 }
576 
577 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
578   addPass(createSeparateConstOffsetFromGEPPass());
579   addPass(createSpeculativeExecutionPass());
580   // ReassociateGEPs exposes more opportunites for SLSR. See
581   // the example in reassociate-geps-and-slsr.ll.
582   addPass(createStraightLineStrengthReducePass());
583   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
584   // EarlyCSE can reuse.
585   addEarlyCSEOrGVNPass();
586   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
587   addPass(createNaryReassociatePass());
588   // NaryReassociate on GEPs creates redundant common expressions, so run
589   // EarlyCSE after it.
590   addPass(createEarlyCSEPass());
591 }
592 
593 void AMDGPUPassConfig::addIRPasses() {
594   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
595 
596   // There is no reason to run these.
597   disablePass(&StackMapLivenessID);
598   disablePass(&FuncletLayoutID);
599   disablePass(&PatchableFunctionID);
600 
601   addPass(createAMDGPULowerIntrinsicsPass());
602 
603   if (TM.getTargetTriple().getArch() == Triple::r600 ||
604       !EnableAMDGPUFunctionCalls) {
605     // Function calls are not supported, so make sure we inline everything.
606     addPass(createAMDGPUAlwaysInlinePass());
607     addPass(createAlwaysInlinerLegacyPass());
608     // We need to add the barrier noop pass, otherwise adding the function
609     // inlining pass will cause all of the PassConfigs passes to be run
610     // one function at a time, which means if we have a nodule with two
611     // functions, then we will generate code for the first function
612     // without ever running any passes on the second.
613     addPass(createBarrierNoopPass());
614   }
615 
616   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
617     // TODO: May want to move later or split into an early and late one.
618 
619     addPass(createAMDGPUCodeGenPreparePass());
620   }
621 
622   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
623   if (TM.getTargetTriple().getArch() == Triple::r600)
624     addPass(createR600OpenCLImageTypeLoweringPass());
625 
626   // Replace OpenCL enqueued block function pointers with global variables.
627   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
628 
629   if (TM.getOptLevel() > CodeGenOpt::None) {
630     addPass(createInferAddressSpacesPass());
631     addPass(createAMDGPUPromoteAlloca());
632 
633     if (EnableSROA)
634       addPass(createSROAPass());
635 
636     addStraightLineScalarOptimizationPasses();
637 
638     if (EnableAMDGPUAliasAnalysis) {
639       addPass(createAMDGPUAAWrapperPass());
640       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
641                                              AAResults &AAR) {
642         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
643           AAR.addAAResult(WrapperPass->getResult());
644         }));
645     }
646   }
647 
648   TargetPassConfig::addIRPasses();
649 
650   // EarlyCSE is not always strong enough to clean up what LSR produces. For
651   // example, GVN can combine
652   //
653   //   %0 = add %a, %b
654   //   %1 = add %b, %a
655   //
656   // and
657   //
658   //   %0 = shl nsw %a, 2
659   //   %1 = shl %a, 2
660   //
661   // but EarlyCSE can do neither of them.
662   if (getOptLevel() != CodeGenOpt::None)
663     addEarlyCSEOrGVNPass();
664 }
665 
666 void AMDGPUPassConfig::addCodeGenPrepare() {
667   TargetPassConfig::addCodeGenPrepare();
668 
669   if (EnableLoadStoreVectorizer)
670     addPass(createLoadStoreVectorizerPass());
671 }
672 
673 bool AMDGPUPassConfig::addPreISel() {
674   addPass(createFlattenCFGPass());
675   return false;
676 }
677 
678 bool AMDGPUPassConfig::addInstSelector() {
679   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
680   return false;
681 }
682 
683 bool AMDGPUPassConfig::addGCPasses() {
684   // Do nothing. GC is not supported.
685   return false;
686 }
687 
688 //===----------------------------------------------------------------------===//
689 // R600 Pass Setup
690 //===----------------------------------------------------------------------===//
691 
692 bool R600PassConfig::addPreISel() {
693   AMDGPUPassConfig::addPreISel();
694 
695   if (EnableR600StructurizeCFG)
696     addPass(createStructurizeCFGPass());
697   return false;
698 }
699 
700 bool R600PassConfig::addInstSelector() {
701   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
702   return false;
703 }
704 
705 void R600PassConfig::addPreRegAlloc() {
706   addPass(createR600VectorRegMerger());
707 }
708 
709 void R600PassConfig::addPreSched2() {
710   addPass(createR600EmitClauseMarkers(), false);
711   if (EnableR600IfConvert)
712     addPass(&IfConverterID, false);
713   addPass(createR600ClauseMergePass(), false);
714 }
715 
716 void R600PassConfig::addPreEmitPass() {
717   addPass(createAMDGPUCFGStructurizerPass(), false);
718   addPass(createR600ExpandSpecialInstrsPass(), false);
719   addPass(&FinalizeMachineBundlesID, false);
720   addPass(createR600Packetizer(), false);
721   addPass(createR600ControlFlowFinalizer(), false);
722 }
723 
724 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
725   return new R600PassConfig(*this, PM);
726 }
727 
728 //===----------------------------------------------------------------------===//
729 // GCN Pass Setup
730 //===----------------------------------------------------------------------===//
731 
732 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
733   MachineSchedContext *C) const {
734   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
735   if (ST.enableSIScheduler())
736     return createSIMachineScheduler(C);
737   return createGCNMaxOccupancyMachineScheduler(C);
738 }
739 
740 bool GCNPassConfig::addPreISel() {
741   AMDGPUPassConfig::addPreISel();
742 
743   // FIXME: We need to run a pass to propagate the attributes when calls are
744   // supported.
745   addPass(createAMDGPUAnnotateKernelFeaturesPass());
746 
747   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
748   // regions formed by them.
749   addPass(&AMDGPUUnifyDivergentExitNodesID);
750   if (!LateCFGStructurize) {
751     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
752   }
753   addPass(createSinkingPass());
754   addPass(createAMDGPUAnnotateUniformValues());
755   if (!LateCFGStructurize) {
756     addPass(createSIAnnotateControlFlowPass());
757   }
758 
759   return false;
760 }
761 
762 void GCNPassConfig::addMachineSSAOptimization() {
763   TargetPassConfig::addMachineSSAOptimization();
764 
765   // We want to fold operands after PeepholeOptimizer has run (or as part of
766   // it), because it will eliminate extra copies making it easier to fold the
767   // real source operand. We want to eliminate dead instructions after, so that
768   // we see fewer uses of the copies. We then need to clean up the dead
769   // instructions leftover after the operands are folded as well.
770   //
771   // XXX - Can we get away without running DeadMachineInstructionElim again?
772   addPass(&SIFoldOperandsID);
773   addPass(&DeadMachineInstructionElimID);
774   addPass(&SILoadStoreOptimizerID);
775   if (EnableSDWAPeephole) {
776     addPass(&SIPeepholeSDWAID);
777     addPass(&EarlyMachineLICMID);
778     addPass(&MachineCSEID);
779     addPass(&SIFoldOperandsID);
780     addPass(&DeadMachineInstructionElimID);
781   }
782   addPass(createSIShrinkInstructionsPass());
783 }
784 
785 bool GCNPassConfig::addILPOpts() {
786   if (EnableEarlyIfConversion)
787     addPass(&EarlyIfConverterID);
788 
789   TargetPassConfig::addILPOpts();
790   return false;
791 }
792 
793 bool GCNPassConfig::addInstSelector() {
794   AMDGPUPassConfig::addInstSelector();
795   addPass(createSILowerI1CopiesPass());
796   addPass(&SIFixSGPRCopiesID);
797   return false;
798 }
799 
800 bool GCNPassConfig::addIRTranslator() {
801   addPass(new IRTranslator());
802   return false;
803 }
804 
805 bool GCNPassConfig::addLegalizeMachineIR() {
806   addPass(new Legalizer());
807   return false;
808 }
809 
810 bool GCNPassConfig::addRegBankSelect() {
811   addPass(new RegBankSelect());
812   return false;
813 }
814 
815 bool GCNPassConfig::addGlobalInstructionSelect() {
816   addPass(new InstructionSelect());
817   return false;
818 }
819 
820 void GCNPassConfig::addPreRegAlloc() {
821   if (LateCFGStructurize) {
822     addPass(createAMDGPUMachineCFGStructurizerPass());
823   }
824   addPass(createSIWholeQuadModePass());
825 }
826 
827 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
828   // FIXME: We have to disable the verifier here because of PHIElimination +
829   // TwoAddressInstructions disabling it.
830 
831   // This must be run immediately after phi elimination and before
832   // TwoAddressInstructions, otherwise the processing of the tied operand of
833   // SI_ELSE will introduce a copy of the tied operand source after the else.
834   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
835 
836   // This must be run after SILowerControlFlow, since it needs to use the
837   // machine-level CFG, but before register allocation.
838   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
839 
840   TargetPassConfig::addFastRegAlloc(RegAllocPass);
841 }
842 
843 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
844   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
845 
846   // This must be run immediately after phi elimination and before
847   // TwoAddressInstructions, otherwise the processing of the tied operand of
848   // SI_ELSE will introduce a copy of the tied operand source after the else.
849   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
850 
851   // This must be run after SILowerControlFlow, since it needs to use the
852   // machine-level CFG, but before register allocation.
853   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
854 
855   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
856 }
857 
858 void GCNPassConfig::addPostRegAlloc() {
859   addPass(&SIFixVGPRCopiesID);
860   addPass(&SIOptimizeExecMaskingID);
861   TargetPassConfig::addPostRegAlloc();
862 }
863 
864 void GCNPassConfig::addPreSched2() {
865 }
866 
867 void GCNPassConfig::addPreEmitPass() {
868   // The hazard recognizer that runs as part of the post-ra scheduler does not
869   // guarantee to be able handle all hazards correctly. This is because if there
870   // are multiple scheduling regions in a basic block, the regions are scheduled
871   // bottom up, so when we begin to schedule a region we don't know what
872   // instructions were emitted directly before it.
873   //
874   // Here we add a stand-alone hazard recognizer pass which can handle all
875   // cases.
876   addPass(&PostRAHazardRecognizerID);
877 
878   addPass(createSIMemoryLegalizerPass());
879   addPass(createSIInsertWaitcntsPass());
880   addPass(createSIShrinkInstructionsPass());
881   addPass(&SIInsertSkipsPassID);
882   addPass(createSIDebuggerInsertNopsPass());
883   addPass(&BranchRelaxationPassID);
884 }
885 
886 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
887   return new GCNPassConfig(*this, PM);
888 }
889