1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110   cl::desc("Enable AMDGPU Alias Analysis"),
111   cl::init(true));
112 
113 // Option to run late CFG structurizer
114 static cl::opt<bool, true> LateCFGStructurize(
115   "amdgpu-late-structurize",
116   cl::desc("Enable late CFG structurization"),
117   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
118   cl::Hidden);
119 
120 static cl::opt<bool> EnableAMDGPUFunctionCalls(
121   "amdgpu-function-calls",
122   cl::Hidden,
123   cl::desc("Enable AMDGPU function call support"),
124   cl::init(false));
125 
126 // Enable lib calls simplifications
127 static cl::opt<bool> EnableLibCallSimplify(
128   "amdgpu-simplify-libcall",
129   cl::desc("Enable amdgpu library simplifications"),
130   cl::init(true),
131   cl::Hidden);
132 
133 extern "C" void LLVMInitializeAMDGPUTarget() {
134   // Register the target
135   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
136   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
137 
138   PassRegistry *PR = PassRegistry::getPassRegistry();
139   initializeR600ClauseMergePassPass(*PR);
140   initializeR600ControlFlowFinalizerPass(*PR);
141   initializeR600PacketizerPass(*PR);
142   initializeR600ExpandSpecialInstrsPassPass(*PR);
143   initializeR600VectorRegMergerPass(*PR);
144   initializeGlobalISel(*PR);
145   initializeAMDGPUDAGToDAGISelPass(*PR);
146   initializeSILowerI1CopiesPass(*PR);
147   initializeSIFixSGPRCopiesPass(*PR);
148   initializeSIFixVGPRCopiesPass(*PR);
149   initializeSIFoldOperandsPass(*PR);
150   initializeSIPeepholeSDWAPass(*PR);
151   initializeSIShrinkInstructionsPass(*PR);
152   initializeSIOptimizeExecMaskingPreRAPass(*PR);
153   initializeSILoadStoreOptimizerPass(*PR);
154   initializeAMDGPUAlwaysInlinePass(*PR);
155   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
156   initializeAMDGPUAnnotateUniformValuesPass(*PR);
157   initializeAMDGPUArgumentUsageInfoPass(*PR);
158   initializeAMDGPULowerKernelAttributesPass(*PR);
159   initializeAMDGPULowerIntrinsicsPass(*PR);
160   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
161   initializeAMDGPUPromoteAllocaPass(*PR);
162   initializeAMDGPUCodeGenPreparePass(*PR);
163   initializeAMDGPURewriteOutArgumentsPass(*PR);
164   initializeAMDGPUUnifyMetadataPass(*PR);
165   initializeSIAnnotateControlFlowPass(*PR);
166   initializeSIInsertWaitcntsPass(*PR);
167   initializeSIWholeQuadModePass(*PR);
168   initializeSILowerControlFlowPass(*PR);
169   initializeSIInsertSkipsPass(*PR);
170   initializeSIMemoryLegalizerPass(*PR);
171   initializeSIDebuggerInsertNopsPass(*PR);
172   initializeSIOptimizeExecMaskingPass(*PR);
173   initializeSIFixWWMLivenessPass(*PR);
174   initializeSIFormMemoryClausesPass(*PR);
175   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
176   initializeAMDGPUAAWrapperPassPass(*PR);
177   initializeAMDGPUUseNativeCallsPass(*PR);
178   initializeAMDGPUSimplifyLibCallsPass(*PR);
179   initializeAMDGPUInlinerPass(*PR);
180 }
181 
182 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
183   return llvm::make_unique<AMDGPUTargetObjectFile>();
184 }
185 
186 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
187   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
188 }
189 
190 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
191   return new SIScheduleDAGMI(C);
192 }
193 
194 static ScheduleDAGInstrs *
195 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
196   ScheduleDAGMILive *DAG =
197     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
198   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
199   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
200   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
201   return DAG;
202 }
203 
204 static ScheduleDAGInstrs *
205 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
206   auto DAG = new GCNIterativeScheduler(C,
207     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
208   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
209   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
210   return DAG;
211 }
212 
213 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
214   return new GCNIterativeScheduler(C,
215     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
216 }
217 
218 static ScheduleDAGInstrs *
219 createIterativeILPMachineScheduler(MachineSchedContext *C) {
220   auto DAG = new GCNIterativeScheduler(C,
221     GCNIterativeScheduler::SCHEDULE_ILP);
222   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
223   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
224   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
225   return DAG;
226 }
227 
228 static MachineSchedRegistry
229 R600SchedRegistry("r600", "Run R600's custom scheduler",
230                    createR600MachineScheduler);
231 
232 static MachineSchedRegistry
233 SISchedRegistry("si", "Run SI's custom scheduler",
234                 createSIMachineScheduler);
235 
236 static MachineSchedRegistry
237 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
238                              "Run GCN scheduler to maximize occupancy",
239                              createGCNMaxOccupancyMachineScheduler);
240 
241 static MachineSchedRegistry
242 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
243   "Run GCN scheduler to maximize occupancy (experimental)",
244   createIterativeGCNMaxOccupancyMachineScheduler);
245 
246 static MachineSchedRegistry
247 GCNMinRegSchedRegistry("gcn-minreg",
248   "Run GCN iterative scheduler for minimal register usage (experimental)",
249   createMinRegScheduler);
250 
251 static MachineSchedRegistry
252 GCNILPSchedRegistry("gcn-ilp",
253   "Run GCN iterative scheduler for ILP scheduling (experimental)",
254   createIterativeILPMachineScheduler);
255 
256 static StringRef computeDataLayout(const Triple &TT) {
257   if (TT.getArch() == Triple::r600) {
258     // 32-bit pointers.
259       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
260              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
261   }
262 
263   // 32-bit private, local, and region pointers. 64-bit global, constant and
264   // flat.
265     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
266          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
267          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
268 }
269 
270 LLVM_READNONE
271 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
272   if (!GPU.empty())
273     return GPU;
274 
275   if (TT.getArch() == Triple::amdgcn)
276     return "generic";
277 
278   return "r600";
279 }
280 
281 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
282   // The AMDGPU toolchain only supports generating shared objects, so we
283   // must always use PIC.
284   return Reloc::PIC_;
285 }
286 
287 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
288   if (CM)
289     return *CM;
290   return CodeModel::Small;
291 }
292 
293 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
294                                          StringRef CPU, StringRef FS,
295                                          TargetOptions Options,
296                                          Optional<Reloc::Model> RM,
297                                          Optional<CodeModel::Model> CM,
298                                          CodeGenOpt::Level OptLevel)
299     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
300                         FS, Options, getEffectiveRelocModel(RM),
301                         getEffectiveCodeModel(CM), OptLevel),
302       TLOF(createTLOF(getTargetTriple())) {
303   AS = AMDGPU::getAMDGPUAS(TT);
304   initAsmInfo();
305 }
306 
307 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
308 
309 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
310 
311 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
312   Attribute GPUAttr = F.getFnAttribute("target-cpu");
313   return GPUAttr.hasAttribute(Attribute::None) ?
314     getTargetCPU() : GPUAttr.getValueAsString();
315 }
316 
317 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
318   Attribute FSAttr = F.getFnAttribute("target-features");
319 
320   return FSAttr.hasAttribute(Attribute::None) ?
321     getTargetFeatureString() :
322     FSAttr.getValueAsString();
323 }
324 
325 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
326   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
327       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
328         AAR.addAAResult(WrapperPass->getResult());
329       });
330 }
331 
332 /// Predicate for Internalize pass.
333 static bool mustPreserveGV(const GlobalValue &GV) {
334   if (const Function *F = dyn_cast<Function>(&GV))
335     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
336 
337   return !GV.use_empty();
338 }
339 
340 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
341   Builder.DivergentTarget = true;
342 
343   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
344   bool Internalize = InternalizeSymbols;
345   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
346   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
347   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
348 
349   if (EnableAMDGPUFunctionCalls) {
350     delete Builder.Inliner;
351     Builder.Inliner = createAMDGPUFunctionInliningPass();
352   }
353 
354   if (Internalize) {
355     // If we're generating code, we always have the whole program available. The
356     // relocations expected for externally visible functions aren't supported,
357     // so make sure every non-entry function is hidden.
358     Builder.addExtension(
359       PassManagerBuilder::EP_EnabledOnOptLevel0,
360       [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
361         PM.add(createInternalizePass(mustPreserveGV));
362       });
363   }
364 
365   Builder.addExtension(
366     PassManagerBuilder::EP_ModuleOptimizerEarly,
367     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
368                                          legacy::PassManagerBase &PM) {
369       if (AMDGPUAA) {
370         PM.add(createAMDGPUAAWrapperPass());
371         PM.add(createAMDGPUExternalAAWrapperPass());
372       }
373       PM.add(createAMDGPUUnifyMetadataPass());
374       if (Internalize) {
375         PM.add(createInternalizePass(mustPreserveGV));
376         PM.add(createGlobalDCEPass());
377       }
378       if (EarlyInline)
379         PM.add(createAMDGPUAlwaysInlinePass(false));
380   });
381 
382   const auto &Opt = Options;
383   Builder.addExtension(
384     PassManagerBuilder::EP_EarlyAsPossible,
385     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
386                                       legacy::PassManagerBase &PM) {
387       if (AMDGPUAA) {
388         PM.add(createAMDGPUAAWrapperPass());
389         PM.add(createAMDGPUExternalAAWrapperPass());
390       }
391       PM.add(llvm::createAMDGPUUseNativeCallsPass());
392       if (LibCallSimplify)
393         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
394   });
395 
396   Builder.addExtension(
397     PassManagerBuilder::EP_CGSCCOptimizerLate,
398     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
399       // Add infer address spaces pass to the opt pipeline after inlining
400       // but before SROA to increase SROA opportunities.
401       PM.add(createInferAddressSpacesPass());
402 
403       // This should run after inlining to have any chance of doing anything,
404       // and before other cleanup optimizations.
405       PM.add(createAMDGPULowerKernelAttributesPass());
406   });
407 }
408 
409 //===----------------------------------------------------------------------===//
410 // R600 Target Machine (R600 -> Cayman)
411 //===----------------------------------------------------------------------===//
412 
413 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
414                                      StringRef CPU, StringRef FS,
415                                      TargetOptions Options,
416                                      Optional<Reloc::Model> RM,
417                                      Optional<CodeModel::Model> CM,
418                                      CodeGenOpt::Level OL, bool JIT)
419     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
420   setRequiresStructuredCFG(true);
421 }
422 
423 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
424   const Function &F) const {
425   StringRef GPU = getGPUName(F);
426   StringRef FS = getFeatureString(F);
427 
428   SmallString<128> SubtargetKey(GPU);
429   SubtargetKey.append(FS);
430 
431   auto &I = SubtargetMap[SubtargetKey];
432   if (!I) {
433     // This needs to be done before we create a new subtarget since any
434     // creation will depend on the TM and the code generation flags on the
435     // function that reside in TargetOptions.
436     resetTargetOptions(F);
437     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
438   }
439 
440   return I.get();
441 }
442 
443 TargetTransformInfo
444 R600TargetMachine::getTargetTransformInfo(const Function &F) {
445   return TargetTransformInfo(R600TTIImpl(this, F));
446 }
447 
448 //===----------------------------------------------------------------------===//
449 // GCN Target Machine (SI+)
450 //===----------------------------------------------------------------------===//
451 
452 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
453                                    StringRef CPU, StringRef FS,
454                                    TargetOptions Options,
455                                    Optional<Reloc::Model> RM,
456                                    Optional<CodeModel::Model> CM,
457                                    CodeGenOpt::Level OL, bool JIT)
458     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
459 
460 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
461   StringRef GPU = getGPUName(F);
462   StringRef FS = getFeatureString(F);
463 
464   SmallString<128> SubtargetKey(GPU);
465   SubtargetKey.append(FS);
466 
467   auto &I = SubtargetMap[SubtargetKey];
468   if (!I) {
469     // This needs to be done before we create a new subtarget since any
470     // creation will depend on the TM and the code generation flags on the
471     // function that reside in TargetOptions.
472     resetTargetOptions(F);
473     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
474   }
475 
476   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
477 
478   return I.get();
479 }
480 
481 TargetTransformInfo
482 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
483   return TargetTransformInfo(GCNTTIImpl(this, F));
484 }
485 
486 //===----------------------------------------------------------------------===//
487 // AMDGPU Pass Setup
488 //===----------------------------------------------------------------------===//
489 
490 namespace {
491 
492 class AMDGPUPassConfig : public TargetPassConfig {
493 public:
494   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
495     : TargetPassConfig(TM, PM) {
496     // Exceptions and StackMaps are not supported, so these passes will never do
497     // anything.
498     disablePass(&StackMapLivenessID);
499     disablePass(&FuncletLayoutID);
500   }
501 
502   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
503     return getTM<AMDGPUTargetMachine>();
504   }
505 
506   ScheduleDAGInstrs *
507   createMachineScheduler(MachineSchedContext *C) const override {
508     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
509     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
510     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
511     return DAG;
512   }
513 
514   void addEarlyCSEOrGVNPass();
515   void addStraightLineScalarOptimizationPasses();
516   void addIRPasses() override;
517   void addCodeGenPrepare() override;
518   bool addPreISel() override;
519   bool addInstSelector() override;
520   bool addGCPasses() override;
521 };
522 
523 class R600PassConfig final : public AMDGPUPassConfig {
524 public:
525   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
526     : AMDGPUPassConfig(TM, PM) {}
527 
528   ScheduleDAGInstrs *createMachineScheduler(
529     MachineSchedContext *C) const override {
530     return createR600MachineScheduler(C);
531   }
532 
533   bool addPreISel() override;
534   bool addInstSelector() override;
535   void addPreRegAlloc() override;
536   void addPreSched2() override;
537   void addPreEmitPass() override;
538 };
539 
540 class GCNPassConfig final : public AMDGPUPassConfig {
541 public:
542   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
543     : AMDGPUPassConfig(TM, PM) {
544     // It is necessary to know the register usage of the entire call graph.  We
545     // allow calls without EnableAMDGPUFunctionCalls if they are marked
546     // noinline, so this is always required.
547     setRequiresCodeGenSCCOrder(true);
548   }
549 
550   GCNTargetMachine &getGCNTargetMachine() const {
551     return getTM<GCNTargetMachine>();
552   }
553 
554   ScheduleDAGInstrs *
555   createMachineScheduler(MachineSchedContext *C) const override;
556 
557   bool addPreISel() override;
558   void addMachineSSAOptimization() override;
559   bool addILPOpts() override;
560   bool addInstSelector() override;
561   bool addIRTranslator() override;
562   bool addLegalizeMachineIR() override;
563   bool addRegBankSelect() override;
564   bool addGlobalInstructionSelect() override;
565   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
566   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
567   void addPreRegAlloc() override;
568   void addPostRegAlloc() override;
569   void addPreSched2() override;
570   void addPreEmitPass() override;
571 };
572 
573 } // end anonymous namespace
574 
575 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
576   if (getOptLevel() == CodeGenOpt::Aggressive)
577     addPass(createGVNPass());
578   else
579     addPass(createEarlyCSEPass());
580 }
581 
582 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
583   addPass(createSeparateConstOffsetFromGEPPass());
584   addPass(createSpeculativeExecutionPass());
585   // ReassociateGEPs exposes more opportunites for SLSR. See
586   // the example in reassociate-geps-and-slsr.ll.
587   addPass(createStraightLineStrengthReducePass());
588   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
589   // EarlyCSE can reuse.
590   addEarlyCSEOrGVNPass();
591   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
592   addPass(createNaryReassociatePass());
593   // NaryReassociate on GEPs creates redundant common expressions, so run
594   // EarlyCSE after it.
595   addPass(createEarlyCSEPass());
596 }
597 
598 void AMDGPUPassConfig::addIRPasses() {
599   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
600 
601   // There is no reason to run these.
602   disablePass(&StackMapLivenessID);
603   disablePass(&FuncletLayoutID);
604   disablePass(&PatchableFunctionID);
605 
606   addPass(createAMDGPULowerIntrinsicsPass());
607 
608   if (TM.getTargetTriple().getArch() == Triple::r600 ||
609       !EnableAMDGPUFunctionCalls) {
610     // Function calls are not supported, so make sure we inline everything.
611     addPass(createAMDGPUAlwaysInlinePass());
612     addPass(createAlwaysInlinerLegacyPass());
613     // We need to add the barrier noop pass, otherwise adding the function
614     // inlining pass will cause all of the PassConfigs passes to be run
615     // one function at a time, which means if we have a nodule with two
616     // functions, then we will generate code for the first function
617     // without ever running any passes on the second.
618     addPass(createBarrierNoopPass());
619   }
620 
621   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
622     // TODO: May want to move later or split into an early and late one.
623 
624     addPass(createAMDGPUCodeGenPreparePass());
625   }
626 
627   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
628   if (TM.getTargetTriple().getArch() == Triple::r600)
629     addPass(createR600OpenCLImageTypeLoweringPass());
630 
631   // Replace OpenCL enqueued block function pointers with global variables.
632   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
633 
634   if (TM.getOptLevel() > CodeGenOpt::None) {
635     addPass(createInferAddressSpacesPass());
636     addPass(createAMDGPUPromoteAlloca());
637 
638     if (EnableSROA)
639       addPass(createSROAPass());
640 
641     addStraightLineScalarOptimizationPasses();
642 
643     if (EnableAMDGPUAliasAnalysis) {
644       addPass(createAMDGPUAAWrapperPass());
645       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
646                                              AAResults &AAR) {
647         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
648           AAR.addAAResult(WrapperPass->getResult());
649         }));
650     }
651   }
652 
653   TargetPassConfig::addIRPasses();
654 
655   // EarlyCSE is not always strong enough to clean up what LSR produces. For
656   // example, GVN can combine
657   //
658   //   %0 = add %a, %b
659   //   %1 = add %b, %a
660   //
661   // and
662   //
663   //   %0 = shl nsw %a, 2
664   //   %1 = shl %a, 2
665   //
666   // but EarlyCSE can do neither of them.
667   if (getOptLevel() != CodeGenOpt::None)
668     addEarlyCSEOrGVNPass();
669 }
670 
671 void AMDGPUPassConfig::addCodeGenPrepare() {
672   TargetPassConfig::addCodeGenPrepare();
673 
674   if (EnableLoadStoreVectorizer)
675     addPass(createLoadStoreVectorizerPass());
676 }
677 
678 bool AMDGPUPassConfig::addPreISel() {
679   addPass(createFlattenCFGPass());
680   return false;
681 }
682 
683 bool AMDGPUPassConfig::addInstSelector() {
684   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
685   return false;
686 }
687 
688 bool AMDGPUPassConfig::addGCPasses() {
689   // Do nothing. GC is not supported.
690   return false;
691 }
692 
693 //===----------------------------------------------------------------------===//
694 // R600 Pass Setup
695 //===----------------------------------------------------------------------===//
696 
697 bool R600PassConfig::addPreISel() {
698   AMDGPUPassConfig::addPreISel();
699 
700   if (EnableR600StructurizeCFG)
701     addPass(createStructurizeCFGPass());
702   return false;
703 }
704 
705 bool R600PassConfig::addInstSelector() {
706   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
707   return false;
708 }
709 
710 void R600PassConfig::addPreRegAlloc() {
711   addPass(createR600VectorRegMerger());
712 }
713 
714 void R600PassConfig::addPreSched2() {
715   addPass(createR600EmitClauseMarkers(), false);
716   if (EnableR600IfConvert)
717     addPass(&IfConverterID, false);
718   addPass(createR600ClauseMergePass(), false);
719 }
720 
721 void R600PassConfig::addPreEmitPass() {
722   addPass(createAMDGPUCFGStructurizerPass(), false);
723   addPass(createR600ExpandSpecialInstrsPass(), false);
724   addPass(&FinalizeMachineBundlesID, false);
725   addPass(createR600Packetizer(), false);
726   addPass(createR600ControlFlowFinalizer(), false);
727 }
728 
729 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
730   return new R600PassConfig(*this, PM);
731 }
732 
733 //===----------------------------------------------------------------------===//
734 // GCN Pass Setup
735 //===----------------------------------------------------------------------===//
736 
737 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
738   MachineSchedContext *C) const {
739   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
740   if (ST.enableSIScheduler())
741     return createSIMachineScheduler(C);
742   return createGCNMaxOccupancyMachineScheduler(C);
743 }
744 
745 bool GCNPassConfig::addPreISel() {
746   AMDGPUPassConfig::addPreISel();
747 
748   // FIXME: We need to run a pass to propagate the attributes when calls are
749   // supported.
750   addPass(createAMDGPUAnnotateKernelFeaturesPass());
751 
752   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
753   // regions formed by them.
754   addPass(&AMDGPUUnifyDivergentExitNodesID);
755   if (!LateCFGStructurize) {
756     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
757   }
758   addPass(createSinkingPass());
759   addPass(createAMDGPUAnnotateUniformValues());
760   if (!LateCFGStructurize) {
761     addPass(createSIAnnotateControlFlowPass());
762   }
763 
764   return false;
765 }
766 
767 void GCNPassConfig::addMachineSSAOptimization() {
768   TargetPassConfig::addMachineSSAOptimization();
769 
770   // We want to fold operands after PeepholeOptimizer has run (or as part of
771   // it), because it will eliminate extra copies making it easier to fold the
772   // real source operand. We want to eliminate dead instructions after, so that
773   // we see fewer uses of the copies. We then need to clean up the dead
774   // instructions leftover after the operands are folded as well.
775   //
776   // XXX - Can we get away without running DeadMachineInstructionElim again?
777   addPass(&SIFoldOperandsID);
778   addPass(&DeadMachineInstructionElimID);
779   addPass(&SILoadStoreOptimizerID);
780   if (EnableSDWAPeephole) {
781     addPass(&SIPeepholeSDWAID);
782     addPass(&EarlyMachineLICMID);
783     addPass(&MachineCSEID);
784     addPass(&SIFoldOperandsID);
785     addPass(&DeadMachineInstructionElimID);
786   }
787   addPass(createSIShrinkInstructionsPass());
788 }
789 
790 bool GCNPassConfig::addILPOpts() {
791   if (EnableEarlyIfConversion)
792     addPass(&EarlyIfConverterID);
793 
794   TargetPassConfig::addILPOpts();
795   return false;
796 }
797 
798 bool GCNPassConfig::addInstSelector() {
799   AMDGPUPassConfig::addInstSelector();
800   addPass(createSILowerI1CopiesPass());
801   addPass(&SIFixSGPRCopiesID);
802   return false;
803 }
804 
805 bool GCNPassConfig::addIRTranslator() {
806   addPass(new IRTranslator());
807   return false;
808 }
809 
810 bool GCNPassConfig::addLegalizeMachineIR() {
811   addPass(new Legalizer());
812   return false;
813 }
814 
815 bool GCNPassConfig::addRegBankSelect() {
816   addPass(new RegBankSelect());
817   return false;
818 }
819 
820 bool GCNPassConfig::addGlobalInstructionSelect() {
821   addPass(new InstructionSelect());
822   return false;
823 }
824 
825 void GCNPassConfig::addPreRegAlloc() {
826   if (LateCFGStructurize) {
827     addPass(createAMDGPUMachineCFGStructurizerPass());
828   }
829   addPass(createSIWholeQuadModePass());
830 }
831 
832 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
833   // FIXME: We have to disable the verifier here because of PHIElimination +
834   // TwoAddressInstructions disabling it.
835 
836   // This must be run immediately after phi elimination and before
837   // TwoAddressInstructions, otherwise the processing of the tied operand of
838   // SI_ELSE will introduce a copy of the tied operand source after the else.
839   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
840 
841   // This must be run after SILowerControlFlow, since it needs to use the
842   // machine-level CFG, but before register allocation.
843   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
844 
845   TargetPassConfig::addFastRegAlloc(RegAllocPass);
846 }
847 
848 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
849   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
850 
851   insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
852 
853   // This must be run immediately after phi elimination and before
854   // TwoAddressInstructions, otherwise the processing of the tied operand of
855   // SI_ELSE will introduce a copy of the tied operand source after the else.
856   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
857 
858   // This must be run after SILowerControlFlow, since it needs to use the
859   // machine-level CFG, but before register allocation.
860   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
861 
862   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
863 }
864 
865 void GCNPassConfig::addPostRegAlloc() {
866   addPass(&SIFixVGPRCopiesID);
867   addPass(&SIOptimizeExecMaskingID);
868   TargetPassConfig::addPostRegAlloc();
869 }
870 
871 void GCNPassConfig::addPreSched2() {
872 }
873 
874 void GCNPassConfig::addPreEmitPass() {
875   // The hazard recognizer that runs as part of the post-ra scheduler does not
876   // guarantee to be able handle all hazards correctly. This is because if there
877   // are multiple scheduling regions in a basic block, the regions are scheduled
878   // bottom up, so when we begin to schedule a region we don't know what
879   // instructions were emitted directly before it.
880   //
881   // Here we add a stand-alone hazard recognizer pass which can handle all
882   // cases.
883   addPass(&PostRAHazardRecognizerID);
884 
885   addPass(createSIMemoryLegalizerPass());
886   addPass(createSIInsertWaitcntsPass());
887   addPass(createSIShrinkInstructionsPass());
888   addPass(&SIInsertSkipsPassID);
889   addPass(createSIDebuggerInsertNopsPass());
890   addPass(&BranchRelaxationPassID);
891 }
892 
893 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
894   return new GCNPassConfig(*this, PM);
895 }
896