1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUInstructionSelector.h"
20 #include "AMDGPULegalizerInfo.h"
21 #include "AMDGPUMacroFusion.h"
22 #include "AMDGPUTargetObjectFile.h"
23 #include "AMDGPUTargetTransformInfo.h"
24 #include "GCNIterativeScheduler.h"
25 #include "GCNSchedStrategy.h"
26 #include "R600MachineScheduler.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIMachineScheduler.h"
29 #include "TargetInfo/AMDGPUTargetInfo.h"
30 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
31 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
32 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
33 #include "llvm/CodeGen/GlobalISel/Localizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MIRParser/MIParser.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/LegacyPassManager.h"
41 #include "llvm/InitializePasses.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/TargetRegistry.h"
46 #include "llvm/Target/TargetLoweringObjectFile.h"
47 #include "llvm/Transforms/IPO.h"
48 #include "llvm/Transforms/IPO/AlwaysInliner.h"
49 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
50 #include "llvm/Transforms/Scalar.h"
51 #include "llvm/Transforms/Scalar/GVN.h"
52 #include "llvm/Transforms/Utils.h"
53 #include "llvm/Transforms/Vectorize.h"
54 #include <memory>
55 
56 using namespace llvm;
57 
58 static cl::opt<bool> EnableR600StructurizeCFG(
59   "r600-ir-structurize",
60   cl::desc("Use StructurizeCFG IR pass"),
61   cl::init(true));
62 
63 static cl::opt<bool> EnableSROA(
64   "amdgpu-sroa",
65   cl::desc("Run SROA after promote alloca pass"),
66   cl::ReallyHidden,
67   cl::init(true));
68 
69 static cl::opt<bool>
70 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
71                         cl::desc("Run early if-conversion"),
72                         cl::init(false));
73 
74 static cl::opt<bool>
75 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
76             cl::desc("Run pre-RA exec mask optimizations"),
77             cl::init(true));
78 
79 static cl::opt<bool> EnableR600IfConvert(
80   "r600-if-convert",
81   cl::desc("Use if conversion pass"),
82   cl::ReallyHidden,
83   cl::init(true));
84 
85 // Option to disable vectorizer for tests.
86 static cl::opt<bool> EnableLoadStoreVectorizer(
87   "amdgpu-load-store-vectorizer",
88   cl::desc("Enable load store vectorizer"),
89   cl::init(true),
90   cl::Hidden);
91 
92 // Option to control global loads scalarization
93 static cl::opt<bool> ScalarizeGlobal(
94   "amdgpu-scalarize-global-loads",
95   cl::desc("Enable global load scalarization"),
96   cl::init(true),
97   cl::Hidden);
98 
99 // Option to run internalize pass.
100 static cl::opt<bool> InternalizeSymbols(
101   "amdgpu-internalize-symbols",
102   cl::desc("Enable elimination of non-kernel functions and unused globals"),
103   cl::init(false),
104   cl::Hidden);
105 
106 // Option to inline all early.
107 static cl::opt<bool> EarlyInlineAll(
108   "amdgpu-early-inline-all",
109   cl::desc("Inline all functions early"),
110   cl::init(false),
111   cl::Hidden);
112 
113 static cl::opt<bool> EnableSDWAPeephole(
114   "amdgpu-sdwa-peephole",
115   cl::desc("Enable SDWA peepholer"),
116   cl::init(true));
117 
118 static cl::opt<bool> EnableDPPCombine(
119   "amdgpu-dpp-combine",
120   cl::desc("Enable DPP combiner"),
121   cl::init(true));
122 
123 // Enable address space based alias analysis
124 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
125   cl::desc("Enable AMDGPU Alias Analysis"),
126   cl::init(true));
127 
128 // Option to run late CFG structurizer
129 static cl::opt<bool, true> LateCFGStructurize(
130   "amdgpu-late-structurize",
131   cl::desc("Enable late CFG structurization"),
132   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
133   cl::Hidden);
134 
135 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
136   "amdgpu-function-calls",
137   cl::desc("Enable AMDGPU function call support"),
138   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
139   cl::init(true),
140   cl::Hidden);
141 
142 // Enable lib calls simplifications
143 static cl::opt<bool> EnableLibCallSimplify(
144   "amdgpu-simplify-libcall",
145   cl::desc("Enable amdgpu library simplifications"),
146   cl::init(true),
147   cl::Hidden);
148 
149 static cl::opt<bool> EnableLowerKernelArguments(
150   "amdgpu-ir-lower-kernel-arguments",
151   cl::desc("Lower kernel argument loads in IR pass"),
152   cl::init(true),
153   cl::Hidden);
154 
155 static cl::opt<bool> EnableRegReassign(
156   "amdgpu-reassign-regs",
157   cl::desc("Enable register reassign optimizations on gfx10+"),
158   cl::init(true),
159   cl::Hidden);
160 
161 // Enable atomic optimization
162 static cl::opt<bool> EnableAtomicOptimizations(
163   "amdgpu-atomic-optimizations",
164   cl::desc("Enable atomic optimizations"),
165   cl::init(false),
166   cl::Hidden);
167 
168 // Enable Mode register optimization
169 static cl::opt<bool> EnableSIModeRegisterPass(
170   "amdgpu-mode-register",
171   cl::desc("Enable mode register pass"),
172   cl::init(true),
173   cl::Hidden);
174 
175 // Option is used in lit tests to prevent deadcoding of patterns inspected.
176 static cl::opt<bool>
177 EnableDCEInRA("amdgpu-dce-in-ra",
178     cl::init(true), cl::Hidden,
179     cl::desc("Enable machine DCE inside regalloc"));
180 
181 static cl::opt<bool> EnableScalarIRPasses(
182   "amdgpu-scalar-ir-passes",
183   cl::desc("Enable scalar IR passes"),
184   cl::init(true),
185   cl::Hidden);
186 
187 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
188   // Register the target
189   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
190   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
191 
192   PassRegistry *PR = PassRegistry::getPassRegistry();
193   initializeR600ClauseMergePassPass(*PR);
194   initializeR600ControlFlowFinalizerPass(*PR);
195   initializeR600PacketizerPass(*PR);
196   initializeR600ExpandSpecialInstrsPassPass(*PR);
197   initializeR600VectorRegMergerPass(*PR);
198   initializeGlobalISel(*PR);
199   initializeAMDGPUDAGToDAGISelPass(*PR);
200   initializeGCNDPPCombinePass(*PR);
201   initializeSILowerI1CopiesPass(*PR);
202   initializeSILowerSGPRSpillsPass(*PR);
203   initializeSIFixSGPRCopiesPass(*PR);
204   initializeSIFixVGPRCopiesPass(*PR);
205   initializeSIFixupVectorISelPass(*PR);
206   initializeSIFoldOperandsPass(*PR);
207   initializeSIPeepholeSDWAPass(*PR);
208   initializeSIShrinkInstructionsPass(*PR);
209   initializeSIOptimizeExecMaskingPreRAPass(*PR);
210   initializeSILoadStoreOptimizerPass(*PR);
211   initializeAMDGPUFixFunctionBitcastsPass(*PR);
212   initializeAMDGPUAlwaysInlinePass(*PR);
213   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
214   initializeAMDGPUAnnotateUniformValuesPass(*PR);
215   initializeAMDGPUArgumentUsageInfoPass(*PR);
216   initializeAMDGPUAtomicOptimizerPass(*PR);
217   initializeAMDGPULowerKernelArgumentsPass(*PR);
218   initializeAMDGPULowerKernelAttributesPass(*PR);
219   initializeAMDGPULowerIntrinsicsPass(*PR);
220   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
221   initializeAMDGPUPostLegalizerCombinerPass(*PR);
222   initializeAMDGPUPreLegalizerCombinerPass(*PR);
223   initializeAMDGPUPromoteAllocaPass(*PR);
224   initializeAMDGPUCodeGenPreparePass(*PR);
225   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
226   initializeAMDGPUPropagateAttributesLatePass(*PR);
227   initializeAMDGPURewriteOutArgumentsPass(*PR);
228   initializeAMDGPUUnifyMetadataPass(*PR);
229   initializeSIAnnotateControlFlowPass(*PR);
230   initializeSIInsertWaitcntsPass(*PR);
231   initializeSIModeRegisterPass(*PR);
232   initializeSIWholeQuadModePass(*PR);
233   initializeSILowerControlFlowPass(*PR);
234   initializeSIRemoveShortExecBranchesPass(*PR);
235   initializeSIInsertSkipsPass(*PR);
236   initializeSIMemoryLegalizerPass(*PR);
237   initializeSIOptimizeExecMaskingPass(*PR);
238   initializeSIPreAllocateWWMRegsPass(*PR);
239   initializeSIFormMemoryClausesPass(*PR);
240   initializeSIPostRABundlerPass(*PR);
241   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
242   initializeAMDGPUAAWrapperPassPass(*PR);
243   initializeAMDGPUExternalAAWrapperPass(*PR);
244   initializeAMDGPUUseNativeCallsPass(*PR);
245   initializeAMDGPUSimplifyLibCallsPass(*PR);
246   initializeAMDGPUInlinerPass(*PR);
247   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
248   initializeGCNRegBankReassignPass(*PR);
249   initializeGCNNSAReassignPass(*PR);
250   initializeSIAddIMGInitPass(*PR);
251 }
252 
253 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
254   return std::make_unique<AMDGPUTargetObjectFile>();
255 }
256 
257 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
258   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
259 }
260 
261 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
262   return new SIScheduleDAGMI(C);
263 }
264 
265 static ScheduleDAGInstrs *
266 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
267   ScheduleDAGMILive *DAG =
268     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
269   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
270   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
271   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
272   return DAG;
273 }
274 
275 static ScheduleDAGInstrs *
276 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
277   auto DAG = new GCNIterativeScheduler(C,
278     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
279   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
280   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
281   return DAG;
282 }
283 
284 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
285   return new GCNIterativeScheduler(C,
286     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
287 }
288 
289 static ScheduleDAGInstrs *
290 createIterativeILPMachineScheduler(MachineSchedContext *C) {
291   auto DAG = new GCNIterativeScheduler(C,
292     GCNIterativeScheduler::SCHEDULE_ILP);
293   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
294   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
295   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
296   return DAG;
297 }
298 
299 static MachineSchedRegistry
300 R600SchedRegistry("r600", "Run R600's custom scheduler",
301                    createR600MachineScheduler);
302 
303 static MachineSchedRegistry
304 SISchedRegistry("si", "Run SI's custom scheduler",
305                 createSIMachineScheduler);
306 
307 static MachineSchedRegistry
308 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
309                              "Run GCN scheduler to maximize occupancy",
310                              createGCNMaxOccupancyMachineScheduler);
311 
312 static MachineSchedRegistry
313 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
314   "Run GCN scheduler to maximize occupancy (experimental)",
315   createIterativeGCNMaxOccupancyMachineScheduler);
316 
317 static MachineSchedRegistry
318 GCNMinRegSchedRegistry("gcn-minreg",
319   "Run GCN iterative scheduler for minimal register usage (experimental)",
320   createMinRegScheduler);
321 
322 static MachineSchedRegistry
323 GCNILPSchedRegistry("gcn-ilp",
324   "Run GCN iterative scheduler for ILP scheduling (experimental)",
325   createIterativeILPMachineScheduler);
326 
327 static StringRef computeDataLayout(const Triple &TT) {
328   if (TT.getArch() == Triple::r600) {
329     // 32-bit pointers.
330       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
331              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
332   }
333 
334   // 32-bit private, local, and region pointers. 64-bit global, constant and
335   // flat, non-integral buffer fat pointers.
336     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
337          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
338          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
339          "-ni:7";
340 }
341 
342 LLVM_READNONE
343 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
344   if (!GPU.empty())
345     return GPU;
346 
347   // Need to default to a target with flat support for HSA.
348   if (TT.getArch() == Triple::amdgcn)
349     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
350 
351   return "r600";
352 }
353 
354 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
355   // The AMDGPU toolchain only supports generating shared objects, so we
356   // must always use PIC.
357   return Reloc::PIC_;
358 }
359 
360 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
361                                          StringRef CPU, StringRef FS,
362                                          TargetOptions Options,
363                                          Optional<Reloc::Model> RM,
364                                          Optional<CodeModel::Model> CM,
365                                          CodeGenOpt::Level OptLevel)
366     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
367                         FS, Options, getEffectiveRelocModel(RM),
368                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
369       TLOF(createTLOF(getTargetTriple())) {
370   initAsmInfo();
371 }
372 
373 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
374 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
375 
376 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
377 
378 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
379   Attribute GPUAttr = F.getFnAttribute("target-cpu");
380   return GPUAttr.hasAttribute(Attribute::None) ?
381     getTargetCPU() : GPUAttr.getValueAsString();
382 }
383 
384 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
385   Attribute FSAttr = F.getFnAttribute("target-features");
386 
387   return FSAttr.hasAttribute(Attribute::None) ?
388     getTargetFeatureString() :
389     FSAttr.getValueAsString();
390 }
391 
392 /// Predicate for Internalize pass.
393 static bool mustPreserveGV(const GlobalValue &GV) {
394   if (const Function *F = dyn_cast<Function>(&GV))
395     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
396 
397   return !GV.use_empty();
398 }
399 
400 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
401   Builder.DivergentTarget = true;
402 
403   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
404   bool Internalize = InternalizeSymbols;
405   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
406   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
407   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
408 
409   if (EnableFunctionCalls) {
410     delete Builder.Inliner;
411     Builder.Inliner = createAMDGPUFunctionInliningPass();
412   }
413 
414   Builder.addExtension(
415     PassManagerBuilder::EP_ModuleOptimizerEarly,
416     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
417                                                legacy::PassManagerBase &PM) {
418       if (AMDGPUAA) {
419         PM.add(createAMDGPUAAWrapperPass());
420         PM.add(createAMDGPUExternalAAWrapperPass());
421       }
422       PM.add(createAMDGPUUnifyMetadataPass());
423       PM.add(createAMDGPUPrintfRuntimeBinding());
424       PM.add(createAMDGPUPropagateAttributesLatePass(this));
425       if (Internalize) {
426         PM.add(createInternalizePass(mustPreserveGV));
427         PM.add(createGlobalDCEPass());
428       }
429       if (EarlyInline)
430         PM.add(createAMDGPUAlwaysInlinePass(false));
431   });
432 
433   const auto &Opt = Options;
434   Builder.addExtension(
435     PassManagerBuilder::EP_EarlyAsPossible,
436     [AMDGPUAA, LibCallSimplify, &Opt, this](const PassManagerBuilder &,
437                                             legacy::PassManagerBase &PM) {
438       if (AMDGPUAA) {
439         PM.add(createAMDGPUAAWrapperPass());
440         PM.add(createAMDGPUExternalAAWrapperPass());
441       }
442       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
443       PM.add(llvm::createAMDGPUUseNativeCallsPass());
444       if (LibCallSimplify)
445         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt, this));
446   });
447 
448   Builder.addExtension(
449     PassManagerBuilder::EP_CGSCCOptimizerLate,
450     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
451       // Add infer address spaces pass to the opt pipeline after inlining
452       // but before SROA to increase SROA opportunities.
453       PM.add(createInferAddressSpacesPass());
454 
455       // This should run after inlining to have any chance of doing anything,
456       // and before other cleanup optimizations.
457       PM.add(createAMDGPULowerKernelAttributesPass());
458   });
459 }
460 
461 //===----------------------------------------------------------------------===//
462 // R600 Target Machine (R600 -> Cayman)
463 //===----------------------------------------------------------------------===//
464 
465 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
466                                      StringRef CPU, StringRef FS,
467                                      TargetOptions Options,
468                                      Optional<Reloc::Model> RM,
469                                      Optional<CodeModel::Model> CM,
470                                      CodeGenOpt::Level OL, bool JIT)
471     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
472   setRequiresStructuredCFG(true);
473 
474   // Override the default since calls aren't supported for r600.
475   if (EnableFunctionCalls &&
476       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
477     EnableFunctionCalls = false;
478 }
479 
480 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
481   const Function &F) const {
482   StringRef GPU = getGPUName(F);
483   StringRef FS = getFeatureString(F);
484 
485   SmallString<128> SubtargetKey(GPU);
486   SubtargetKey.append(FS);
487 
488   auto &I = SubtargetMap[SubtargetKey];
489   if (!I) {
490     // This needs to be done before we create a new subtarget since any
491     // creation will depend on the TM and the code generation flags on the
492     // function that reside in TargetOptions.
493     resetTargetOptions(F);
494     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
495   }
496 
497   return I.get();
498 }
499 
500 TargetTransformInfo
501 R600TargetMachine::getTargetTransformInfo(const Function &F) {
502   return TargetTransformInfo(R600TTIImpl(this, F));
503 }
504 
505 //===----------------------------------------------------------------------===//
506 // GCN Target Machine (SI+)
507 //===----------------------------------------------------------------------===//
508 
509 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
510                                    StringRef CPU, StringRef FS,
511                                    TargetOptions Options,
512                                    Optional<Reloc::Model> RM,
513                                    Optional<CodeModel::Model> CM,
514                                    CodeGenOpt::Level OL, bool JIT)
515     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
516 
517 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
518   StringRef GPU = getGPUName(F);
519   StringRef FS = getFeatureString(F);
520 
521   SmallString<128> SubtargetKey(GPU);
522   SubtargetKey.append(FS);
523 
524   auto &I = SubtargetMap[SubtargetKey];
525   if (!I) {
526     // This needs to be done before we create a new subtarget since any
527     // creation will depend on the TM and the code generation flags on the
528     // function that reside in TargetOptions.
529     resetTargetOptions(F);
530     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
531   }
532 
533   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
534 
535   return I.get();
536 }
537 
538 TargetTransformInfo
539 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
540   return TargetTransformInfo(GCNTTIImpl(this, F));
541 }
542 
543 //===----------------------------------------------------------------------===//
544 // AMDGPU Pass Setup
545 //===----------------------------------------------------------------------===//
546 
547 namespace {
548 
549 class AMDGPUPassConfig : public TargetPassConfig {
550 public:
551   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
552     : TargetPassConfig(TM, PM) {
553     // Exceptions and StackMaps are not supported, so these passes will never do
554     // anything.
555     disablePass(&StackMapLivenessID);
556     disablePass(&FuncletLayoutID);
557   }
558 
559   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
560     return getTM<AMDGPUTargetMachine>();
561   }
562 
563   ScheduleDAGInstrs *
564   createMachineScheduler(MachineSchedContext *C) const override {
565     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
566     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
567     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
568     return DAG;
569   }
570 
571   void addEarlyCSEOrGVNPass();
572   void addStraightLineScalarOptimizationPasses();
573   void addIRPasses() override;
574   void addCodeGenPrepare() override;
575   bool addPreISel() override;
576   bool addInstSelector() override;
577   bool addGCPasses() override;
578 
579   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
580 };
581 
582 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
583   return getStandardCSEConfigForOpt(TM->getOptLevel());
584 }
585 
586 class R600PassConfig final : public AMDGPUPassConfig {
587 public:
588   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
589     : AMDGPUPassConfig(TM, PM) {}
590 
591   ScheduleDAGInstrs *createMachineScheduler(
592     MachineSchedContext *C) const override {
593     return createR600MachineScheduler(C);
594   }
595 
596   bool addPreISel() override;
597   bool addInstSelector() override;
598   void addPreRegAlloc() override;
599   void addPreSched2() override;
600   void addPreEmitPass() override;
601 };
602 
603 class GCNPassConfig final : public AMDGPUPassConfig {
604 public:
605   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
606     : AMDGPUPassConfig(TM, PM) {
607     // It is necessary to know the register usage of the entire call graph.  We
608     // allow calls without EnableAMDGPUFunctionCalls if they are marked
609     // noinline, so this is always required.
610     setRequiresCodeGenSCCOrder(true);
611   }
612 
613   GCNTargetMachine &getGCNTargetMachine() const {
614     return getTM<GCNTargetMachine>();
615   }
616 
617   ScheduleDAGInstrs *
618   createMachineScheduler(MachineSchedContext *C) const override;
619 
620   bool addPreISel() override;
621   void addMachineSSAOptimization() override;
622   bool addILPOpts() override;
623   bool addInstSelector() override;
624   bool addIRTranslator() override;
625   void addPreLegalizeMachineIR() override;
626   bool addLegalizeMachineIR() override;
627   void addPreRegBankSelect() override;
628   bool addRegBankSelect() override;
629   bool addGlobalInstructionSelect() override;
630   void addFastRegAlloc() override;
631   void addOptimizedRegAlloc() override;
632   void addPreRegAlloc() override;
633   bool addPreRewrite() override;
634   void addPostRegAlloc() override;
635   void addPreSched2() override;
636   void addPreEmitPass() override;
637 };
638 
639 } // end anonymous namespace
640 
641 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
642   if (getOptLevel() == CodeGenOpt::Aggressive)
643     addPass(createGVNPass());
644   else
645     addPass(createEarlyCSEPass());
646 }
647 
648 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
649   addPass(createLICMPass());
650   addPass(createSeparateConstOffsetFromGEPPass());
651   addPass(createSpeculativeExecutionPass());
652   // ReassociateGEPs exposes more opportunites for SLSR. See
653   // the example in reassociate-geps-and-slsr.ll.
654   addPass(createStraightLineStrengthReducePass());
655   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
656   // EarlyCSE can reuse.
657   addEarlyCSEOrGVNPass();
658   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
659   addPass(createNaryReassociatePass());
660   // NaryReassociate on GEPs creates redundant common expressions, so run
661   // EarlyCSE after it.
662   addPass(createEarlyCSEPass());
663 }
664 
665 void AMDGPUPassConfig::addIRPasses() {
666   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
667 
668   // There is no reason to run these.
669   disablePass(&StackMapLivenessID);
670   disablePass(&FuncletLayoutID);
671   disablePass(&PatchableFunctionID);
672 
673   addPass(createAMDGPUPrintfRuntimeBinding());
674 
675   // This must occur before inlining, as the inliner will not look through
676   // bitcast calls.
677   addPass(createAMDGPUFixFunctionBitcastsPass());
678 
679   // A call to propagate attributes pass in the backend in case opt was not run.
680   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
681 
682   addPass(createAtomicExpandPass());
683 
684 
685   addPass(createAMDGPULowerIntrinsicsPass());
686 
687   // Function calls are not supported, so make sure we inline everything.
688   addPass(createAMDGPUAlwaysInlinePass());
689   addPass(createAlwaysInlinerLegacyPass());
690   // We need to add the barrier noop pass, otherwise adding the function
691   // inlining pass will cause all of the PassConfigs passes to be run
692   // one function at a time, which means if we have a nodule with two
693   // functions, then we will generate code for the first function
694   // without ever running any passes on the second.
695   addPass(createBarrierNoopPass());
696 
697   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
698   if (TM.getTargetTriple().getArch() == Triple::r600)
699     addPass(createR600OpenCLImageTypeLoweringPass());
700 
701   // Replace OpenCL enqueued block function pointers with global variables.
702   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
703 
704   if (TM.getOptLevel() > CodeGenOpt::None) {
705     addPass(createInferAddressSpacesPass());
706     addPass(createAMDGPUPromoteAlloca());
707 
708     if (EnableSROA)
709       addPass(createSROAPass());
710 
711     if (EnableScalarIRPasses)
712       addStraightLineScalarOptimizationPasses();
713 
714     if (EnableAMDGPUAliasAnalysis) {
715       addPass(createAMDGPUAAWrapperPass());
716       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
717                                              AAResults &AAR) {
718         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
719           AAR.addAAResult(WrapperPass->getResult());
720         }));
721     }
722   }
723 
724   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
725     // TODO: May want to move later or split into an early and late one.
726     addPass(createAMDGPUCodeGenPreparePass());
727   }
728 
729   TargetPassConfig::addIRPasses();
730 
731   // EarlyCSE is not always strong enough to clean up what LSR produces. For
732   // example, GVN can combine
733   //
734   //   %0 = add %a, %b
735   //   %1 = add %b, %a
736   //
737   // and
738   //
739   //   %0 = shl nsw %a, 2
740   //   %1 = shl %a, 2
741   //
742   // but EarlyCSE can do neither of them.
743   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
744     addEarlyCSEOrGVNPass();
745 }
746 
747 void AMDGPUPassConfig::addCodeGenPrepare() {
748   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
749     addPass(createAMDGPUAnnotateKernelFeaturesPass());
750 
751   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
752       EnableLowerKernelArguments)
753     addPass(createAMDGPULowerKernelArgumentsPass());
754 
755   addPass(&AMDGPUPerfHintAnalysisID);
756 
757   TargetPassConfig::addCodeGenPrepare();
758 
759   if (EnableLoadStoreVectorizer)
760     addPass(createLoadStoreVectorizerPass());
761 }
762 
763 bool AMDGPUPassConfig::addPreISel() {
764   addPass(createLowerSwitchPass());
765   addPass(createFlattenCFGPass());
766   return false;
767 }
768 
769 bool AMDGPUPassConfig::addInstSelector() {
770   // Defer the verifier until FinalizeISel.
771   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
772   return false;
773 }
774 
775 bool AMDGPUPassConfig::addGCPasses() {
776   // Do nothing. GC is not supported.
777   return false;
778 }
779 
780 //===----------------------------------------------------------------------===//
781 // R600 Pass Setup
782 //===----------------------------------------------------------------------===//
783 
784 bool R600PassConfig::addPreISel() {
785   AMDGPUPassConfig::addPreISel();
786 
787   if (EnableR600StructurizeCFG)
788     addPass(createStructurizeCFGPass());
789   return false;
790 }
791 
792 bool R600PassConfig::addInstSelector() {
793   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
794   return false;
795 }
796 
797 void R600PassConfig::addPreRegAlloc() {
798   addPass(createR600VectorRegMerger());
799 }
800 
801 void R600PassConfig::addPreSched2() {
802   addPass(createR600EmitClauseMarkers(), false);
803   if (EnableR600IfConvert)
804     addPass(&IfConverterID, false);
805   addPass(createR600ClauseMergePass(), false);
806 }
807 
808 void R600PassConfig::addPreEmitPass() {
809   addPass(createAMDGPUCFGStructurizerPass(), false);
810   addPass(createR600ExpandSpecialInstrsPass(), false);
811   addPass(&FinalizeMachineBundlesID, false);
812   addPass(createR600Packetizer(), false);
813   addPass(createR600ControlFlowFinalizer(), false);
814 }
815 
816 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
817   return new R600PassConfig(*this, PM);
818 }
819 
820 //===----------------------------------------------------------------------===//
821 // GCN Pass Setup
822 //===----------------------------------------------------------------------===//
823 
824 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
825   MachineSchedContext *C) const {
826   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
827   if (ST.enableSIScheduler())
828     return createSIMachineScheduler(C);
829   return createGCNMaxOccupancyMachineScheduler(C);
830 }
831 
832 bool GCNPassConfig::addPreISel() {
833   AMDGPUPassConfig::addPreISel();
834 
835   if (EnableAtomicOptimizations) {
836     addPass(createAMDGPUAtomicOptimizerPass());
837   }
838 
839   // FIXME: We need to run a pass to propagate the attributes when calls are
840   // supported.
841 
842   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
843   // regions formed by them.
844   addPass(&AMDGPUUnifyDivergentExitNodesID);
845   if (!LateCFGStructurize) {
846     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
847   }
848   addPass(createSinkingPass());
849   addPass(createAMDGPUAnnotateUniformValues());
850   if (!LateCFGStructurize) {
851     addPass(createSIAnnotateControlFlowPass());
852   }
853   addPass(createLCSSAPass());
854 
855   return false;
856 }
857 
858 void GCNPassConfig::addMachineSSAOptimization() {
859   TargetPassConfig::addMachineSSAOptimization();
860 
861   // We want to fold operands after PeepholeOptimizer has run (or as part of
862   // it), because it will eliminate extra copies making it easier to fold the
863   // real source operand. We want to eliminate dead instructions after, so that
864   // we see fewer uses of the copies. We then need to clean up the dead
865   // instructions leftover after the operands are folded as well.
866   //
867   // XXX - Can we get away without running DeadMachineInstructionElim again?
868   addPass(&SIFoldOperandsID);
869   if (EnableDPPCombine)
870     addPass(&GCNDPPCombineID);
871   addPass(&DeadMachineInstructionElimID);
872   addPass(&SILoadStoreOptimizerID);
873   if (EnableSDWAPeephole) {
874     addPass(&SIPeepholeSDWAID);
875     addPass(&EarlyMachineLICMID);
876     addPass(&MachineCSEID);
877     addPass(&SIFoldOperandsID);
878     addPass(&DeadMachineInstructionElimID);
879   }
880   addPass(createSIShrinkInstructionsPass());
881 }
882 
883 bool GCNPassConfig::addILPOpts() {
884   if (EnableEarlyIfConversion)
885     addPass(&EarlyIfConverterID);
886 
887   TargetPassConfig::addILPOpts();
888   return false;
889 }
890 
891 bool GCNPassConfig::addInstSelector() {
892   AMDGPUPassConfig::addInstSelector();
893   addPass(&SIFixSGPRCopiesID);
894   addPass(createSILowerI1CopiesPass());
895   addPass(createSIFixupVectorISelPass());
896   addPass(createSIAddIMGInitPass());
897   return false;
898 }
899 
900 bool GCNPassConfig::addIRTranslator() {
901   addPass(new IRTranslator());
902   return false;
903 }
904 
905 void GCNPassConfig::addPreLegalizeMachineIR() {
906   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
907   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
908   addPass(new Localizer());
909 }
910 
911 bool GCNPassConfig::addLegalizeMachineIR() {
912   addPass(new Legalizer());
913   return false;
914 }
915 
916 void GCNPassConfig::addPreRegBankSelect() {
917   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
918   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
919 }
920 
921 bool GCNPassConfig::addRegBankSelect() {
922   addPass(new RegBankSelect());
923   return false;
924 }
925 
926 bool GCNPassConfig::addGlobalInstructionSelect() {
927   addPass(new InstructionSelect());
928   return false;
929 }
930 
931 void GCNPassConfig::addPreRegAlloc() {
932   if (LateCFGStructurize) {
933     addPass(createAMDGPUMachineCFGStructurizerPass());
934   }
935   addPass(createSIWholeQuadModePass());
936 }
937 
938 void GCNPassConfig::addFastRegAlloc() {
939   // FIXME: We have to disable the verifier here because of PHIElimination +
940   // TwoAddressInstructions disabling it.
941 
942   // This must be run immediately after phi elimination and before
943   // TwoAddressInstructions, otherwise the processing of the tied operand of
944   // SI_ELSE will introduce a copy of the tied operand source after the else.
945   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
946 
947   // This must be run just after RegisterCoalescing.
948   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
949 
950   TargetPassConfig::addFastRegAlloc();
951 }
952 
953 void GCNPassConfig::addOptimizedRegAlloc() {
954   if (OptExecMaskPreRA) {
955     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
956     insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
957   } else {
958     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
959   }
960 
961   // This must be run immediately after phi elimination and before
962   // TwoAddressInstructions, otherwise the processing of the tied operand of
963   // SI_ELSE will introduce a copy of the tied operand source after the else.
964   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
965 
966   // This must be run just after RegisterCoalescing.
967   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
968 
969   if (EnableDCEInRA)
970     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
971 
972   TargetPassConfig::addOptimizedRegAlloc();
973 }
974 
975 bool GCNPassConfig::addPreRewrite() {
976   if (EnableRegReassign) {
977     addPass(&GCNNSAReassignID);
978     addPass(&GCNRegBankReassignID);
979   }
980   return true;
981 }
982 
983 void GCNPassConfig::addPostRegAlloc() {
984   addPass(&SIFixVGPRCopiesID);
985   if (getOptLevel() > CodeGenOpt::None)
986     addPass(&SIOptimizeExecMaskingID);
987   TargetPassConfig::addPostRegAlloc();
988 
989   // Equivalent of PEI for SGPRs.
990   addPass(&SILowerSGPRSpillsID);
991 }
992 
993 void GCNPassConfig::addPreSched2() {
994   addPass(&SIPostRABundlerID);
995 }
996 
997 void GCNPassConfig::addPreEmitPass() {
998   addPass(createSIMemoryLegalizerPass());
999   addPass(createSIInsertWaitcntsPass());
1000   addPass(createSIShrinkInstructionsPass());
1001   addPass(createSIModeRegisterPass());
1002 
1003   // The hazard recognizer that runs as part of the post-ra scheduler does not
1004   // guarantee to be able handle all hazards correctly. This is because if there
1005   // are multiple scheduling regions in a basic block, the regions are scheduled
1006   // bottom up, so when we begin to schedule a region we don't know what
1007   // instructions were emitted directly before it.
1008   //
1009   // Here we add a stand-alone hazard recognizer pass which can handle all
1010   // cases.
1011   //
1012   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
1013   // be better for it to emit S_NOP <N> when possible.
1014   addPass(&PostRAHazardRecognizerID);
1015 
1016   addPass(&SIRemoveShortExecBranchesID);
1017   addPass(&SIInsertSkipsPassID);
1018   addPass(&BranchRelaxationPassID);
1019 }
1020 
1021 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1022   return new GCNPassConfig(*this, PM);
1023 }
1024 
1025 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1026   return new yaml::SIMachineFunctionInfo();
1027 }
1028 
1029 yaml::MachineFunctionInfo *
1030 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1031   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1032   return new yaml::SIMachineFunctionInfo(*MFI,
1033                                          *MF.getSubtarget().getRegisterInfo());
1034 }
1035 
1036 bool GCNTargetMachine::parseMachineFunctionInfo(
1037     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1038     SMDiagnostic &Error, SMRange &SourceRange) const {
1039   const yaml::SIMachineFunctionInfo &YamlMFI =
1040       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1041   MachineFunction &MF = PFS.MF;
1042   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1043 
1044   MFI->initializeBaseYamlFields(YamlMFI);
1045 
1046   auto parseRegister = [&](const yaml::StringValue &RegName, unsigned &RegVal) {
1047     if (parseNamedRegisterReference(PFS, RegVal, RegName.Value, Error)) {
1048       SourceRange = RegName.SourceRange;
1049       return true;
1050     }
1051 
1052     return false;
1053   };
1054 
1055   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1056     // Create a diagnostic for a the register string literal.
1057     const MemoryBuffer &Buffer =
1058         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1059     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1060                          RegName.Value.size(), SourceMgr::DK_Error,
1061                          "incorrect register class for field", RegName.Value,
1062                          None, None);
1063     SourceRange = RegName.SourceRange;
1064     return true;
1065   };
1066 
1067   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1068       parseRegister(YamlMFI.ScratchWaveOffsetReg, MFI->ScratchWaveOffsetReg) ||
1069       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1070       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1071     return true;
1072 
1073   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1074       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1075     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1076   }
1077 
1078   if (MFI->ScratchWaveOffsetReg != AMDGPU::SCRATCH_WAVE_OFFSET_REG &&
1079       !AMDGPU::SGPR_32RegClass.contains(MFI->ScratchWaveOffsetReg)) {
1080     return diagnoseRegisterClass(YamlMFI.ScratchWaveOffsetReg);
1081   }
1082 
1083   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1084       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1085     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1086   }
1087 
1088   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1089       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1090     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1091   }
1092 
1093   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1094                                    const TargetRegisterClass &RC,
1095                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1096                                    unsigned SystemSGPRs) {
1097     // Skip parsing if it's not present.
1098     if (!A)
1099       return false;
1100 
1101     if (A->IsRegister) {
1102       unsigned Reg;
1103       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1104         SourceRange = A->RegisterName.SourceRange;
1105         return true;
1106       }
1107       if (!RC.contains(Reg))
1108         return diagnoseRegisterClass(A->RegisterName);
1109       Arg = ArgDescriptor::createRegister(Reg);
1110     } else
1111       Arg = ArgDescriptor::createStack(A->StackOffset);
1112     // Check and apply the optional mask.
1113     if (A->Mask)
1114       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1115 
1116     MFI->NumUserSGPRs += UserSGPRs;
1117     MFI->NumSystemSGPRs += SystemSGPRs;
1118     return false;
1119   };
1120 
1121   if (YamlMFI.ArgInfo &&
1122       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1123                              AMDGPU::SGPR_128RegClass,
1124                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1125        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1126                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1127                              2, 0) ||
1128        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1129                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1130        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1131                              AMDGPU::SReg_64RegClass,
1132                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1133        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1134                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1135                              2, 0) ||
1136        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1137                              AMDGPU::SReg_64RegClass,
1138                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1139        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1140                              AMDGPU::SGPR_32RegClass,
1141                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1142        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1143                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1144                              0, 1) ||
1145        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1146                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1147                              0, 1) ||
1148        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1149                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1150                              0, 1) ||
1151        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1152                              AMDGPU::SGPR_32RegClass,
1153                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1154        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1155                              AMDGPU::SGPR_32RegClass,
1156                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1157        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1158                              AMDGPU::SReg_64RegClass,
1159                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1160        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1161                              AMDGPU::SReg_64RegClass,
1162                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1163        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1164                              AMDGPU::VGPR_32RegClass,
1165                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1166        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1167                              AMDGPU::VGPR_32RegClass,
1168                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1169        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1170                              AMDGPU::VGPR_32RegClass,
1171                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1172     return true;
1173 
1174   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1175   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1176   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1177   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1178   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1179   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1180 
1181   return false;
1182 }
1183