1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUExportClustering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
28 #include "R600MachineScheduler.h"
29 #include "SIMachineFunctionInfo.h"
30 #include "SIMachineScheduler.h"
31 #include "TargetInfo/AMDGPUTargetInfo.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
35 #include "llvm/CodeGen/GlobalISel/Localizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MIRParser/MIParser.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/LegacyPassManager.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/Pass.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Transforms/IPO.h"
50 #include "llvm/Transforms/IPO/AlwaysInliner.h"
51 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
52 #include "llvm/Transforms/Scalar.h"
53 #include "llvm/Transforms/Scalar/GVN.h"
54 #include "llvm/Transforms/Utils.h"
55 #include "llvm/Transforms/Vectorize.h"
56 #include <memory>
57 
58 using namespace llvm;
59 
60 static cl::opt<bool> EnableR600StructurizeCFG(
61   "r600-ir-structurize",
62   cl::desc("Use StructurizeCFG IR pass"),
63   cl::init(true));
64 
65 static cl::opt<bool> EnableSROA(
66   "amdgpu-sroa",
67   cl::desc("Run SROA after promote alloca pass"),
68   cl::ReallyHidden,
69   cl::init(true));
70 
71 static cl::opt<bool>
72 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
73                         cl::desc("Run early if-conversion"),
74                         cl::init(false));
75 
76 static cl::opt<bool>
77 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
78             cl::desc("Run pre-RA exec mask optimizations"),
79             cl::init(true));
80 
81 static cl::opt<bool> EnableR600IfConvert(
82   "r600-if-convert",
83   cl::desc("Use if conversion pass"),
84   cl::ReallyHidden,
85   cl::init(true));
86 
87 // Option to disable vectorizer for tests.
88 static cl::opt<bool> EnableLoadStoreVectorizer(
89   "amdgpu-load-store-vectorizer",
90   cl::desc("Enable load store vectorizer"),
91   cl::init(true),
92   cl::Hidden);
93 
94 // Option to control global loads scalarization
95 static cl::opt<bool> ScalarizeGlobal(
96   "amdgpu-scalarize-global-loads",
97   cl::desc("Enable global load scalarization"),
98   cl::init(true),
99   cl::Hidden);
100 
101 // Option to run internalize pass.
102 static cl::opt<bool> InternalizeSymbols(
103   "amdgpu-internalize-symbols",
104   cl::desc("Enable elimination of non-kernel functions and unused globals"),
105   cl::init(false),
106   cl::Hidden);
107 
108 // Option to inline all early.
109 static cl::opt<bool> EarlyInlineAll(
110   "amdgpu-early-inline-all",
111   cl::desc("Inline all functions early"),
112   cl::init(false),
113   cl::Hidden);
114 
115 static cl::opt<bool> EnableSDWAPeephole(
116   "amdgpu-sdwa-peephole",
117   cl::desc("Enable SDWA peepholer"),
118   cl::init(true));
119 
120 static cl::opt<bool> EnableDPPCombine(
121   "amdgpu-dpp-combine",
122   cl::desc("Enable DPP combiner"),
123   cl::init(true));
124 
125 // Enable address space based alias analysis
126 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
127   cl::desc("Enable AMDGPU Alias Analysis"),
128   cl::init(true));
129 
130 // Option to run late CFG structurizer
131 static cl::opt<bool, true> LateCFGStructurize(
132   "amdgpu-late-structurize",
133   cl::desc("Enable late CFG structurization"),
134   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
135   cl::Hidden);
136 
137 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
138   "amdgpu-function-calls",
139   cl::desc("Enable AMDGPU function call support"),
140   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
141   cl::init(true),
142   cl::Hidden);
143 
144 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
145   "amdgpu-fixed-function-abi",
146   cl::desc("Enable all implicit function arguments"),
147   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
148   cl::init(false),
149   cl::Hidden);
150 
151 // Enable lib calls simplifications
152 static cl::opt<bool> EnableLibCallSimplify(
153   "amdgpu-simplify-libcall",
154   cl::desc("Enable amdgpu library simplifications"),
155   cl::init(true),
156   cl::Hidden);
157 
158 static cl::opt<bool> EnableLowerKernelArguments(
159   "amdgpu-ir-lower-kernel-arguments",
160   cl::desc("Lower kernel argument loads in IR pass"),
161   cl::init(true),
162   cl::Hidden);
163 
164 static cl::opt<bool> EnableRegReassign(
165   "amdgpu-reassign-regs",
166   cl::desc("Enable register reassign optimizations on gfx10+"),
167   cl::init(true),
168   cl::Hidden);
169 
170 // Enable atomic optimization
171 static cl::opt<bool> EnableAtomicOptimizations(
172   "amdgpu-atomic-optimizations",
173   cl::desc("Enable atomic optimizations"),
174   cl::init(false),
175   cl::Hidden);
176 
177 // Enable Mode register optimization
178 static cl::opt<bool> EnableSIModeRegisterPass(
179   "amdgpu-mode-register",
180   cl::desc("Enable mode register pass"),
181   cl::init(true),
182   cl::Hidden);
183 
184 // Option is used in lit tests to prevent deadcoding of patterns inspected.
185 static cl::opt<bool>
186 EnableDCEInRA("amdgpu-dce-in-ra",
187     cl::init(true), cl::Hidden,
188     cl::desc("Enable machine DCE inside regalloc"));
189 
190 static cl::opt<bool> EnableScalarIRPasses(
191   "amdgpu-scalar-ir-passes",
192   cl::desc("Enable scalar IR passes"),
193   cl::init(true),
194   cl::Hidden);
195 
196 static cl::opt<bool> EnableStructurizerWorkarounds(
197     "amdgpu-enable-structurizer-workarounds",
198     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(false),
199     cl::Hidden);
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFixupVectorISelPass(*PR);
220   initializeSIFoldOperandsPass(*PR);
221   initializeSIPeepholeSDWAPass(*PR);
222   initializeSIShrinkInstructionsPass(*PR);
223   initializeSIOptimizeExecMaskingPreRAPass(*PR);
224   initializeSILoadStoreOptimizerPass(*PR);
225   initializeAMDGPUFixFunctionBitcastsPass(*PR);
226   initializeAMDGPUAlwaysInlinePass(*PR);
227   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
228   initializeAMDGPUAnnotateUniformValuesPass(*PR);
229   initializeAMDGPUArgumentUsageInfoPass(*PR);
230   initializeAMDGPUAtomicOptimizerPass(*PR);
231   initializeAMDGPULowerKernelArgumentsPass(*PR);
232   initializeAMDGPULowerKernelAttributesPass(*PR);
233   initializeAMDGPULowerIntrinsicsPass(*PR);
234   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
235   initializeAMDGPUPostLegalizerCombinerPass(*PR);
236   initializeAMDGPUPreLegalizerCombinerPass(*PR);
237   initializeAMDGPUPromoteAllocaPass(*PR);
238   initializeAMDGPUCodeGenPreparePass(*PR);
239   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
240   initializeAMDGPUPropagateAttributesLatePass(*PR);
241   initializeAMDGPURewriteOutArgumentsPass(*PR);
242   initializeAMDGPUUnifyMetadataPass(*PR);
243   initializeSIAnnotateControlFlowPass(*PR);
244   initializeSIInsertWaitcntsPass(*PR);
245   initializeSIModeRegisterPass(*PR);
246   initializeSIWholeQuadModePass(*PR);
247   initializeSILowerControlFlowPass(*PR);
248   initializeSIRemoveShortExecBranchesPass(*PR);
249   initializeSIPreEmitPeepholePass(*PR);
250   initializeSIInsertSkipsPass(*PR);
251   initializeSIMemoryLegalizerPass(*PR);
252   initializeSIOptimizeExecMaskingPass(*PR);
253   initializeSIPreAllocateWWMRegsPass(*PR);
254   initializeSIFormMemoryClausesPass(*PR);
255   initializeSIPostRABundlerPass(*PR);
256   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
257   initializeAMDGPUAAWrapperPassPass(*PR);
258   initializeAMDGPUExternalAAWrapperPass(*PR);
259   initializeAMDGPUUseNativeCallsPass(*PR);
260   initializeAMDGPUSimplifyLibCallsPass(*PR);
261   initializeAMDGPUInlinerPass(*PR);
262   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
263   initializeGCNRegBankReassignPass(*PR);
264   initializeGCNNSAReassignPass(*PR);
265   initializeSIAddIMGInitPass(*PR);
266 }
267 
268 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
269   return std::make_unique<AMDGPUTargetObjectFile>();
270 }
271 
272 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
273   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
274 }
275 
276 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
277   return new SIScheduleDAGMI(C);
278 }
279 
280 static ScheduleDAGInstrs *
281 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
282   ScheduleDAGMILive *DAG =
283     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
284   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
285   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
286   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
287   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
288   return DAG;
289 }
290 
291 static ScheduleDAGInstrs *
292 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
293   auto DAG = new GCNIterativeScheduler(C,
294     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
295   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
296   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
297   return DAG;
298 }
299 
300 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
301   return new GCNIterativeScheduler(C,
302     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
303 }
304 
305 static ScheduleDAGInstrs *
306 createIterativeILPMachineScheduler(MachineSchedContext *C) {
307   auto DAG = new GCNIterativeScheduler(C,
308     GCNIterativeScheduler::SCHEDULE_ILP);
309   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
310   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
311   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
312   return DAG;
313 }
314 
315 static MachineSchedRegistry
316 R600SchedRegistry("r600", "Run R600's custom scheduler",
317                    createR600MachineScheduler);
318 
319 static MachineSchedRegistry
320 SISchedRegistry("si", "Run SI's custom scheduler",
321                 createSIMachineScheduler);
322 
323 static MachineSchedRegistry
324 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
325                              "Run GCN scheduler to maximize occupancy",
326                              createGCNMaxOccupancyMachineScheduler);
327 
328 static MachineSchedRegistry
329 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
330   "Run GCN scheduler to maximize occupancy (experimental)",
331   createIterativeGCNMaxOccupancyMachineScheduler);
332 
333 static MachineSchedRegistry
334 GCNMinRegSchedRegistry("gcn-minreg",
335   "Run GCN iterative scheduler for minimal register usage (experimental)",
336   createMinRegScheduler);
337 
338 static MachineSchedRegistry
339 GCNILPSchedRegistry("gcn-ilp",
340   "Run GCN iterative scheduler for ILP scheduling (experimental)",
341   createIterativeILPMachineScheduler);
342 
343 static StringRef computeDataLayout(const Triple &TT) {
344   if (TT.getArch() == Triple::r600) {
345     // 32-bit pointers.
346       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
347              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
348   }
349 
350   // 32-bit private, local, and region pointers. 64-bit global, constant and
351   // flat, non-integral buffer fat pointers.
352     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
353          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
354          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
355          "-ni:7";
356 }
357 
358 LLVM_READNONE
359 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
360   if (!GPU.empty())
361     return GPU;
362 
363   // Need to default to a target with flat support for HSA.
364   if (TT.getArch() == Triple::amdgcn)
365     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
366 
367   return "r600";
368 }
369 
370 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
371   // The AMDGPU toolchain only supports generating shared objects, so we
372   // must always use PIC.
373   return Reloc::PIC_;
374 }
375 
376 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
377                                          StringRef CPU, StringRef FS,
378                                          TargetOptions Options,
379                                          Optional<Reloc::Model> RM,
380                                          Optional<CodeModel::Model> CM,
381                                          CodeGenOpt::Level OptLevel)
382     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
383                         FS, Options, getEffectiveRelocModel(RM),
384                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
385       TLOF(createTLOF(getTargetTriple())) {
386   initAsmInfo();
387   if (TT.getArch() == Triple::amdgcn) {
388     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
389       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
390     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
391       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
392   }
393 }
394 
395 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
396 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
397 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
398 
399 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
400 
401 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
402   Attribute GPUAttr = F.getFnAttribute("target-cpu");
403   return GPUAttr.hasAttribute(Attribute::None) ?
404     getTargetCPU() : GPUAttr.getValueAsString();
405 }
406 
407 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
408   Attribute FSAttr = F.getFnAttribute("target-features");
409 
410   return FSAttr.hasAttribute(Attribute::None) ?
411     getTargetFeatureString() :
412     FSAttr.getValueAsString();
413 }
414 
415 /// Predicate for Internalize pass.
416 static bool mustPreserveGV(const GlobalValue &GV) {
417   if (const Function *F = dyn_cast<Function>(&GV))
418     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
419 
420   return !GV.use_empty();
421 }
422 
423 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
424   Builder.DivergentTarget = true;
425 
426   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
427   bool Internalize = InternalizeSymbols;
428   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
429   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
430   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
431 
432   if (EnableFunctionCalls) {
433     delete Builder.Inliner;
434     Builder.Inliner = createAMDGPUFunctionInliningPass();
435   }
436 
437   Builder.addExtension(
438     PassManagerBuilder::EP_ModuleOptimizerEarly,
439     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
440                                                legacy::PassManagerBase &PM) {
441       if (AMDGPUAA) {
442         PM.add(createAMDGPUAAWrapperPass());
443         PM.add(createAMDGPUExternalAAWrapperPass());
444       }
445       PM.add(createAMDGPUUnifyMetadataPass());
446       PM.add(createAMDGPUPrintfRuntimeBinding());
447       if (Internalize)
448         PM.add(createInternalizePass(mustPreserveGV));
449       PM.add(createAMDGPUPropagateAttributesLatePass(this));
450       if (Internalize)
451         PM.add(createGlobalDCEPass());
452       if (EarlyInline)
453         PM.add(createAMDGPUAlwaysInlinePass(false));
454   });
455 
456   Builder.addExtension(
457     PassManagerBuilder::EP_EarlyAsPossible,
458     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
459                                       legacy::PassManagerBase &PM) {
460       if (AMDGPUAA) {
461         PM.add(createAMDGPUAAWrapperPass());
462         PM.add(createAMDGPUExternalAAWrapperPass());
463       }
464       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
465       PM.add(llvm::createAMDGPUUseNativeCallsPass());
466       if (LibCallSimplify)
467         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
468   });
469 
470   Builder.addExtension(
471     PassManagerBuilder::EP_CGSCCOptimizerLate,
472     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
473       // Add infer address spaces pass to the opt pipeline after inlining
474       // but before SROA to increase SROA opportunities.
475       PM.add(createInferAddressSpacesPass());
476 
477       // This should run after inlining to have any chance of doing anything,
478       // and before other cleanup optimizations.
479       PM.add(createAMDGPULowerKernelAttributesPass());
480   });
481 }
482 
483 //===----------------------------------------------------------------------===//
484 // R600 Target Machine (R600 -> Cayman)
485 //===----------------------------------------------------------------------===//
486 
487 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
488                                      StringRef CPU, StringRef FS,
489                                      TargetOptions Options,
490                                      Optional<Reloc::Model> RM,
491                                      Optional<CodeModel::Model> CM,
492                                      CodeGenOpt::Level OL, bool JIT)
493     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
494   setRequiresStructuredCFG(true);
495 
496   // Override the default since calls aren't supported for r600.
497   if (EnableFunctionCalls &&
498       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
499     EnableFunctionCalls = false;
500 }
501 
502 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
503   const Function &F) const {
504   StringRef GPU = getGPUName(F);
505   StringRef FS = getFeatureString(F);
506 
507   SmallString<128> SubtargetKey(GPU);
508   SubtargetKey.append(FS);
509 
510   auto &I = SubtargetMap[SubtargetKey];
511   if (!I) {
512     // This needs to be done before we create a new subtarget since any
513     // creation will depend on the TM and the code generation flags on the
514     // function that reside in TargetOptions.
515     resetTargetOptions(F);
516     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
517   }
518 
519   return I.get();
520 }
521 
522 TargetTransformInfo
523 R600TargetMachine::getTargetTransformInfo(const Function &F) {
524   return TargetTransformInfo(R600TTIImpl(this, F));
525 }
526 
527 //===----------------------------------------------------------------------===//
528 // GCN Target Machine (SI+)
529 //===----------------------------------------------------------------------===//
530 
531 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
532                                    StringRef CPU, StringRef FS,
533                                    TargetOptions Options,
534                                    Optional<Reloc::Model> RM,
535                                    Optional<CodeModel::Model> CM,
536                                    CodeGenOpt::Level OL, bool JIT)
537     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
538 
539 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
540   StringRef GPU = getGPUName(F);
541   StringRef FS = getFeatureString(F);
542 
543   SmallString<128> SubtargetKey(GPU);
544   SubtargetKey.append(FS);
545 
546   auto &I = SubtargetMap[SubtargetKey];
547   if (!I) {
548     // This needs to be done before we create a new subtarget since any
549     // creation will depend on the TM and the code generation flags on the
550     // function that reside in TargetOptions.
551     resetTargetOptions(F);
552     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
553   }
554 
555   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
556 
557   return I.get();
558 }
559 
560 TargetTransformInfo
561 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
562   return TargetTransformInfo(GCNTTIImpl(this, F));
563 }
564 
565 //===----------------------------------------------------------------------===//
566 // AMDGPU Pass Setup
567 //===----------------------------------------------------------------------===//
568 
569 namespace {
570 
571 class AMDGPUPassConfig : public TargetPassConfig {
572 public:
573   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
574     : TargetPassConfig(TM, PM) {
575     // Exceptions and StackMaps are not supported, so these passes will never do
576     // anything.
577     disablePass(&StackMapLivenessID);
578     disablePass(&FuncletLayoutID);
579   }
580 
581   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
582     return getTM<AMDGPUTargetMachine>();
583   }
584 
585   ScheduleDAGInstrs *
586   createMachineScheduler(MachineSchedContext *C) const override {
587     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
588     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
589     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
590     return DAG;
591   }
592 
593   void addEarlyCSEOrGVNPass();
594   void addStraightLineScalarOptimizationPasses();
595   void addIRPasses() override;
596   void addCodeGenPrepare() override;
597   bool addPreISel() override;
598   bool addInstSelector() override;
599   bool addGCPasses() override;
600 
601   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
602 };
603 
604 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
605   return getStandardCSEConfigForOpt(TM->getOptLevel());
606 }
607 
608 class R600PassConfig final : public AMDGPUPassConfig {
609 public:
610   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
611     : AMDGPUPassConfig(TM, PM) {}
612 
613   ScheduleDAGInstrs *createMachineScheduler(
614     MachineSchedContext *C) const override {
615     return createR600MachineScheduler(C);
616   }
617 
618   bool addPreISel() override;
619   bool addInstSelector() override;
620   void addPreRegAlloc() override;
621   void addPreSched2() override;
622   void addPreEmitPass() override;
623 };
624 
625 class GCNPassConfig final : public AMDGPUPassConfig {
626 public:
627   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
628     : AMDGPUPassConfig(TM, PM) {
629     // It is necessary to know the register usage of the entire call graph.  We
630     // allow calls without EnableAMDGPUFunctionCalls if they are marked
631     // noinline, so this is always required.
632     setRequiresCodeGenSCCOrder(true);
633   }
634 
635   GCNTargetMachine &getGCNTargetMachine() const {
636     return getTM<GCNTargetMachine>();
637   }
638 
639   ScheduleDAGInstrs *
640   createMachineScheduler(MachineSchedContext *C) const override;
641 
642   bool addPreISel() override;
643   void addMachineSSAOptimization() override;
644   bool addILPOpts() override;
645   bool addInstSelector() override;
646   bool addIRTranslator() override;
647   void addPreLegalizeMachineIR() override;
648   bool addLegalizeMachineIR() override;
649   void addPreRegBankSelect() override;
650   bool addRegBankSelect() override;
651   bool addGlobalInstructionSelect() override;
652   void addFastRegAlloc() override;
653   void addOptimizedRegAlloc() override;
654   void addPreRegAlloc() override;
655   bool addPreRewrite() override;
656   void addPostRegAlloc() override;
657   void addPreSched2() override;
658   void addPreEmitPass() override;
659 };
660 
661 } // end anonymous namespace
662 
663 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
664   if (getOptLevel() == CodeGenOpt::Aggressive)
665     addPass(createGVNPass());
666   else
667     addPass(createEarlyCSEPass());
668 }
669 
670 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
671   addPass(createLICMPass());
672   addPass(createSeparateConstOffsetFromGEPPass());
673   addPass(createSpeculativeExecutionPass());
674   // ReassociateGEPs exposes more opportunites for SLSR. See
675   // the example in reassociate-geps-and-slsr.ll.
676   addPass(createStraightLineStrengthReducePass());
677   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
678   // EarlyCSE can reuse.
679   addEarlyCSEOrGVNPass();
680   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
681   addPass(createNaryReassociatePass());
682   // NaryReassociate on GEPs creates redundant common expressions, so run
683   // EarlyCSE after it.
684   addPass(createEarlyCSEPass());
685 }
686 
687 void AMDGPUPassConfig::addIRPasses() {
688   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
689 
690   // There is no reason to run these.
691   disablePass(&StackMapLivenessID);
692   disablePass(&FuncletLayoutID);
693   disablePass(&PatchableFunctionID);
694 
695   addPass(createAMDGPUPrintfRuntimeBinding());
696 
697   // This must occur before inlining, as the inliner will not look through
698   // bitcast calls.
699   addPass(createAMDGPUFixFunctionBitcastsPass());
700 
701   // A call to propagate attributes pass in the backend in case opt was not run.
702   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
703 
704   addPass(createAtomicExpandPass());
705 
706 
707   addPass(createAMDGPULowerIntrinsicsPass());
708 
709   // Function calls are not supported, so make sure we inline everything.
710   addPass(createAMDGPUAlwaysInlinePass());
711   addPass(createAlwaysInlinerLegacyPass());
712   // We need to add the barrier noop pass, otherwise adding the function
713   // inlining pass will cause all of the PassConfigs passes to be run
714   // one function at a time, which means if we have a nodule with two
715   // functions, then we will generate code for the first function
716   // without ever running any passes on the second.
717   addPass(createBarrierNoopPass());
718 
719   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
720   if (TM.getTargetTriple().getArch() == Triple::r600)
721     addPass(createR600OpenCLImageTypeLoweringPass());
722 
723   // Replace OpenCL enqueued block function pointers with global variables.
724   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
725 
726   if (TM.getOptLevel() > CodeGenOpt::None) {
727     addPass(createInferAddressSpacesPass());
728     addPass(createAMDGPUPromoteAlloca());
729 
730     if (EnableSROA)
731       addPass(createSROAPass());
732 
733     if (EnableScalarIRPasses)
734       addStraightLineScalarOptimizationPasses();
735 
736     if (EnableAMDGPUAliasAnalysis) {
737       addPass(createAMDGPUAAWrapperPass());
738       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
739                                              AAResults &AAR) {
740         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
741           AAR.addAAResult(WrapperPass->getResult());
742         }));
743     }
744   }
745 
746   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
747     // TODO: May want to move later or split into an early and late one.
748     addPass(createAMDGPUCodeGenPreparePass());
749   }
750 
751   TargetPassConfig::addIRPasses();
752 
753   // EarlyCSE is not always strong enough to clean up what LSR produces. For
754   // example, GVN can combine
755   //
756   //   %0 = add %a, %b
757   //   %1 = add %b, %a
758   //
759   // and
760   //
761   //   %0 = shl nsw %a, 2
762   //   %1 = shl %a, 2
763   //
764   // but EarlyCSE can do neither of them.
765   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
766     addEarlyCSEOrGVNPass();
767 }
768 
769 void AMDGPUPassConfig::addCodeGenPrepare() {
770   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
771     addPass(createAMDGPUAnnotateKernelFeaturesPass());
772 
773   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
774       EnableLowerKernelArguments)
775     addPass(createAMDGPULowerKernelArgumentsPass());
776 
777   addPass(&AMDGPUPerfHintAnalysisID);
778 
779   TargetPassConfig::addCodeGenPrepare();
780 
781   if (EnableLoadStoreVectorizer)
782     addPass(createLoadStoreVectorizerPass());
783 }
784 
785 bool AMDGPUPassConfig::addPreISel() {
786   addPass(createLowerSwitchPass());
787   addPass(createFlattenCFGPass());
788   return false;
789 }
790 
791 bool AMDGPUPassConfig::addInstSelector() {
792   // Defer the verifier until FinalizeISel.
793   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
794   return false;
795 }
796 
797 bool AMDGPUPassConfig::addGCPasses() {
798   // Do nothing. GC is not supported.
799   return false;
800 }
801 
802 //===----------------------------------------------------------------------===//
803 // R600 Pass Setup
804 //===----------------------------------------------------------------------===//
805 
806 bool R600PassConfig::addPreISel() {
807   AMDGPUPassConfig::addPreISel();
808 
809   if (EnableR600StructurizeCFG)
810     addPass(createStructurizeCFGPass());
811   return false;
812 }
813 
814 bool R600PassConfig::addInstSelector() {
815   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
816   return false;
817 }
818 
819 void R600PassConfig::addPreRegAlloc() {
820   addPass(createR600VectorRegMerger());
821 }
822 
823 void R600PassConfig::addPreSched2() {
824   addPass(createR600EmitClauseMarkers(), false);
825   if (EnableR600IfConvert)
826     addPass(&IfConverterID, false);
827   addPass(createR600ClauseMergePass(), false);
828 }
829 
830 void R600PassConfig::addPreEmitPass() {
831   addPass(createAMDGPUCFGStructurizerPass(), false);
832   addPass(createR600ExpandSpecialInstrsPass(), false);
833   addPass(&FinalizeMachineBundlesID, false);
834   addPass(createR600Packetizer(), false);
835   addPass(createR600ControlFlowFinalizer(), false);
836 }
837 
838 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
839   return new R600PassConfig(*this, PM);
840 }
841 
842 //===----------------------------------------------------------------------===//
843 // GCN Pass Setup
844 //===----------------------------------------------------------------------===//
845 
846 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
847   MachineSchedContext *C) const {
848   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
849   if (ST.enableSIScheduler())
850     return createSIMachineScheduler(C);
851   return createGCNMaxOccupancyMachineScheduler(C);
852 }
853 
854 bool GCNPassConfig::addPreISel() {
855   AMDGPUPassConfig::addPreISel();
856 
857   if (EnableAtomicOptimizations) {
858     addPass(createAMDGPUAtomicOptimizerPass());
859   }
860 
861   // FIXME: We need to run a pass to propagate the attributes when calls are
862   // supported.
863 
864   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
865   // regions formed by them.
866   addPass(&AMDGPUUnifyDivergentExitNodesID);
867   if (!LateCFGStructurize) {
868     if (EnableStructurizerWorkarounds) {
869       addPass(createFixIrreduciblePass());
870       addPass(createUnifyLoopExitsPass());
871     }
872     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
873   }
874   addPass(createSinkingPass());
875   addPass(createAMDGPUAnnotateUniformValues());
876   if (!LateCFGStructurize) {
877     addPass(createSIAnnotateControlFlowPass());
878   }
879   addPass(createLCSSAPass());
880 
881   return false;
882 }
883 
884 void GCNPassConfig::addMachineSSAOptimization() {
885   TargetPassConfig::addMachineSSAOptimization();
886 
887   // We want to fold operands after PeepholeOptimizer has run (or as part of
888   // it), because it will eliminate extra copies making it easier to fold the
889   // real source operand. We want to eliminate dead instructions after, so that
890   // we see fewer uses of the copies. We then need to clean up the dead
891   // instructions leftover after the operands are folded as well.
892   //
893   // XXX - Can we get away without running DeadMachineInstructionElim again?
894   addPass(&SIFoldOperandsID);
895   if (EnableDPPCombine)
896     addPass(&GCNDPPCombineID);
897   addPass(&DeadMachineInstructionElimID);
898   addPass(&SILoadStoreOptimizerID);
899   if (EnableSDWAPeephole) {
900     addPass(&SIPeepholeSDWAID);
901     addPass(&EarlyMachineLICMID);
902     addPass(&MachineCSEID);
903     addPass(&SIFoldOperandsID);
904     addPass(&DeadMachineInstructionElimID);
905   }
906   addPass(createSIShrinkInstructionsPass());
907 }
908 
909 bool GCNPassConfig::addILPOpts() {
910   if (EnableEarlyIfConversion)
911     addPass(&EarlyIfConverterID);
912 
913   TargetPassConfig::addILPOpts();
914   return false;
915 }
916 
917 bool GCNPassConfig::addInstSelector() {
918   AMDGPUPassConfig::addInstSelector();
919   addPass(&SIFixSGPRCopiesID);
920   addPass(createSILowerI1CopiesPass());
921   // TODO: We have to add FinalizeISel
922   // to expand V_ADD/SUB_U64_PSEUDO before SIFixupVectorISel
923   // that expects V_ADD/SUB -> A_ADDC/SUBB pairs expanded.
924   // Will be removed as soon as SIFixupVectorISel is changed
925   // to work with V_ADD/SUB_U64_PSEUDO instead.
926   addPass(&FinalizeISelID);
927   addPass(createSIFixupVectorISelPass());
928   addPass(createSIAddIMGInitPass());
929   return false;
930 }
931 
932 bool GCNPassConfig::addIRTranslator() {
933   addPass(new IRTranslator());
934   return false;
935 }
936 
937 void GCNPassConfig::addPreLegalizeMachineIR() {
938   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
939   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
940   addPass(new Localizer());
941 }
942 
943 bool GCNPassConfig::addLegalizeMachineIR() {
944   addPass(new Legalizer());
945   return false;
946 }
947 
948 void GCNPassConfig::addPreRegBankSelect() {
949   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
950   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
951 }
952 
953 bool GCNPassConfig::addRegBankSelect() {
954   addPass(new RegBankSelect());
955   return false;
956 }
957 
958 bool GCNPassConfig::addGlobalInstructionSelect() {
959   addPass(new InstructionSelect());
960   return false;
961 }
962 
963 void GCNPassConfig::addPreRegAlloc() {
964   if (LateCFGStructurize) {
965     addPass(createAMDGPUMachineCFGStructurizerPass());
966   }
967   addPass(createSIWholeQuadModePass());
968 }
969 
970 void GCNPassConfig::addFastRegAlloc() {
971   // FIXME: We have to disable the verifier here because of PHIElimination +
972   // TwoAddressInstructions disabling it.
973 
974   // This must be run immediately after phi elimination and before
975   // TwoAddressInstructions, otherwise the processing of the tied operand of
976   // SI_ELSE will introduce a copy of the tied operand source after the else.
977   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
978 
979   // This must be run just after RegisterCoalescing.
980   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
981 
982   TargetPassConfig::addFastRegAlloc();
983 }
984 
985 void GCNPassConfig::addOptimizedRegAlloc() {
986   if (OptExecMaskPreRA) {
987     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
988     insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
989   } else {
990     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
991   }
992 
993   // This must be run immediately after phi elimination and before
994   // TwoAddressInstructions, otherwise the processing of the tied operand of
995   // SI_ELSE will introduce a copy of the tied operand source after the else.
996   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
997 
998   // This must be run just after RegisterCoalescing.
999   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
1000 
1001   if (EnableDCEInRA)
1002     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1003 
1004   TargetPassConfig::addOptimizedRegAlloc();
1005 }
1006 
1007 bool GCNPassConfig::addPreRewrite() {
1008   if (EnableRegReassign) {
1009     addPass(&GCNNSAReassignID);
1010     addPass(&GCNRegBankReassignID);
1011   }
1012   return true;
1013 }
1014 
1015 void GCNPassConfig::addPostRegAlloc() {
1016   addPass(&SIFixVGPRCopiesID);
1017   if (getOptLevel() > CodeGenOpt::None)
1018     addPass(&SIOptimizeExecMaskingID);
1019   TargetPassConfig::addPostRegAlloc();
1020 
1021   // Equivalent of PEI for SGPRs.
1022   addPass(&SILowerSGPRSpillsID);
1023 }
1024 
1025 void GCNPassConfig::addPreSched2() {
1026   addPass(&SIPostRABundlerID);
1027 }
1028 
1029 void GCNPassConfig::addPreEmitPass() {
1030   addPass(createSIMemoryLegalizerPass());
1031   addPass(createSIInsertWaitcntsPass());
1032   addPass(createSIShrinkInstructionsPass());
1033   addPass(createSIModeRegisterPass());
1034 
1035   // The hazard recognizer that runs as part of the post-ra scheduler does not
1036   // guarantee to be able handle all hazards correctly. This is because if there
1037   // are multiple scheduling regions in a basic block, the regions are scheduled
1038   // bottom up, so when we begin to schedule a region we don't know what
1039   // instructions were emitted directly before it.
1040   //
1041   // Here we add a stand-alone hazard recognizer pass which can handle all
1042   // cases.
1043   //
1044   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
1045   // be better for it to emit S_NOP <N> when possible.
1046   addPass(&PostRAHazardRecognizerID);
1047 
1048   addPass(&SIRemoveShortExecBranchesID);
1049   addPass(&SIPreEmitPeepholeID);
1050   addPass(&SIInsertSkipsPassID);
1051   addPass(&BranchRelaxationPassID);
1052 }
1053 
1054 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1055   return new GCNPassConfig(*this, PM);
1056 }
1057 
1058 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1059   return new yaml::SIMachineFunctionInfo();
1060 }
1061 
1062 yaml::MachineFunctionInfo *
1063 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1064   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1065   return new yaml::SIMachineFunctionInfo(*MFI,
1066                                          *MF.getSubtarget().getRegisterInfo());
1067 }
1068 
1069 bool GCNTargetMachine::parseMachineFunctionInfo(
1070     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1071     SMDiagnostic &Error, SMRange &SourceRange) const {
1072   const yaml::SIMachineFunctionInfo &YamlMFI =
1073       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1074   MachineFunction &MF = PFS.MF;
1075   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1076 
1077   MFI->initializeBaseYamlFields(YamlMFI);
1078 
1079   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1080     Register TempReg;
1081     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1082       SourceRange = RegName.SourceRange;
1083       return true;
1084     }
1085     RegVal = TempReg;
1086 
1087     return false;
1088   };
1089 
1090   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1091     // Create a diagnostic for a the register string literal.
1092     const MemoryBuffer &Buffer =
1093         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1094     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1095                          RegName.Value.size(), SourceMgr::DK_Error,
1096                          "incorrect register class for field", RegName.Value,
1097                          None, None);
1098     SourceRange = RegName.SourceRange;
1099     return true;
1100   };
1101 
1102   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1103       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1104       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1105     return true;
1106 
1107   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1108       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1109     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1110   }
1111 
1112   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1113       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1114     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1115   }
1116 
1117   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1118       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1119     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1120   }
1121 
1122   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1123                                    const TargetRegisterClass &RC,
1124                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1125                                    unsigned SystemSGPRs) {
1126     // Skip parsing if it's not present.
1127     if (!A)
1128       return false;
1129 
1130     if (A->IsRegister) {
1131       Register Reg;
1132       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1133         SourceRange = A->RegisterName.SourceRange;
1134         return true;
1135       }
1136       if (!RC.contains(Reg))
1137         return diagnoseRegisterClass(A->RegisterName);
1138       Arg = ArgDescriptor::createRegister(Reg);
1139     } else
1140       Arg = ArgDescriptor::createStack(A->StackOffset);
1141     // Check and apply the optional mask.
1142     if (A->Mask)
1143       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1144 
1145     MFI->NumUserSGPRs += UserSGPRs;
1146     MFI->NumSystemSGPRs += SystemSGPRs;
1147     return false;
1148   };
1149 
1150   if (YamlMFI.ArgInfo &&
1151       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1152                              AMDGPU::SGPR_128RegClass,
1153                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1154        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1155                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1156                              2, 0) ||
1157        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1158                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1159        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1160                              AMDGPU::SReg_64RegClass,
1161                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1162        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1163                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1164                              2, 0) ||
1165        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1166                              AMDGPU::SReg_64RegClass,
1167                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1168        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1169                              AMDGPU::SGPR_32RegClass,
1170                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1171        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1172                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1173                              0, 1) ||
1174        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1175                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1176                              0, 1) ||
1177        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1178                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1179                              0, 1) ||
1180        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1181                              AMDGPU::SGPR_32RegClass,
1182                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1183        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1184                              AMDGPU::SGPR_32RegClass,
1185                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1186        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1187                              AMDGPU::SReg_64RegClass,
1188                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1189        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1190                              AMDGPU::SReg_64RegClass,
1191                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1192        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1193                              AMDGPU::VGPR_32RegClass,
1194                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1195        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1196                              AMDGPU::VGPR_32RegClass,
1197                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1198        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1199                              AMDGPU::VGPR_32RegClass,
1200                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1201     return true;
1202 
1203   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1204   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1205   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1206   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1207   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1208   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1209 
1210   return false;
1211 }
1212