1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Utils.h"
49 #include "llvm/Transforms/Vectorize.h"
50 #include <memory>
51 
52 using namespace llvm;
53 
54 static cl::opt<bool> EnableR600StructurizeCFG(
55   "r600-ir-structurize",
56   cl::desc("Use StructurizeCFG IR pass"),
57   cl::init(true));
58 
59 static cl::opt<bool> EnableSROA(
60   "amdgpu-sroa",
61   cl::desc("Run SROA after promote alloca pass"),
62   cl::ReallyHidden,
63   cl::init(true));
64 
65 static cl::opt<bool>
66 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
67                         cl::desc("Run early if-conversion"),
68                         cl::init(false));
69 
70 static cl::opt<bool> EnableR600IfConvert(
71   "r600-if-convert",
72   cl::desc("Use if conversion pass"),
73   cl::ReallyHidden,
74   cl::init(true));
75 
76 // Option to disable vectorizer for tests.
77 static cl::opt<bool> EnableLoadStoreVectorizer(
78   "amdgpu-load-store-vectorizer",
79   cl::desc("Enable load store vectorizer"),
80   cl::init(true),
81   cl::Hidden);
82 
83 // Option to control global loads scalarization
84 static cl::opt<bool> ScalarizeGlobal(
85   "amdgpu-scalarize-global-loads",
86   cl::desc("Enable global load scalarization"),
87   cl::init(true),
88   cl::Hidden);
89 
90 // Option to run internalize pass.
91 static cl::opt<bool> InternalizeSymbols(
92   "amdgpu-internalize-symbols",
93   cl::desc("Enable elimination of non-kernel functions and unused globals"),
94   cl::init(false),
95   cl::Hidden);
96 
97 // Option to inline all early.
98 static cl::opt<bool> EarlyInlineAll(
99   "amdgpu-early-inline-all",
100   cl::desc("Inline all functions early"),
101   cl::init(false),
102   cl::Hidden);
103 
104 static cl::opt<bool> EnableSDWAPeephole(
105   "amdgpu-sdwa-peephole",
106   cl::desc("Enable SDWA peepholer"),
107   cl::init(true));
108 
109 // Enable address space based alias analysis
110 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
111   cl::desc("Enable AMDGPU Alias Analysis"),
112   cl::init(true));
113 
114 // Option to run late CFG structurizer
115 static cl::opt<bool, true> LateCFGStructurize(
116   "amdgpu-late-structurize",
117   cl::desc("Enable late CFG structurization"),
118   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
119   cl::Hidden);
120 
121 static cl::opt<bool, true> EnableAMDGPUFunctionCalls(
122   "amdgpu-function-calls",
123   cl::desc("Enable AMDGPU function call support"),
124   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
125   cl::init(false),
126   cl::Hidden);
127 
128 // Enable lib calls simplifications
129 static cl::opt<bool> EnableLibCallSimplify(
130   "amdgpu-simplify-libcall",
131   cl::desc("Enable amdgpu library simplifications"),
132   cl::init(true),
133   cl::Hidden);
134 
135 static cl::opt<bool> EnableLowerKernelArguments(
136   "amdgpu-ir-lower-kernel-arguments",
137   cl::desc("Lower kernel argument loads in IR pass"),
138   cl::init(true),
139   cl::Hidden);
140 
141 // Enable atomic optimization
142 static cl::opt<bool> EnableAtomicOptimizations(
143   "amdgpu-atomic-optimizations",
144   cl::desc("Enable atomic optimizations"),
145   cl::init(false),
146   cl::Hidden);
147 
148 extern "C" void LLVMInitializeAMDGPUTarget() {
149   // Register the target
150   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
151   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
152 
153   PassRegistry *PR = PassRegistry::getPassRegistry();
154   initializeR600ClauseMergePassPass(*PR);
155   initializeR600ControlFlowFinalizerPass(*PR);
156   initializeR600PacketizerPass(*PR);
157   initializeR600ExpandSpecialInstrsPassPass(*PR);
158   initializeR600VectorRegMergerPass(*PR);
159   initializeGlobalISel(*PR);
160   initializeAMDGPUDAGToDAGISelPass(*PR);
161   initializeSILowerI1CopiesPass(*PR);
162   initializeSIFixSGPRCopiesPass(*PR);
163   initializeSIFixVGPRCopiesPass(*PR);
164   initializeSIFoldOperandsPass(*PR);
165   initializeSIPeepholeSDWAPass(*PR);
166   initializeSIShrinkInstructionsPass(*PR);
167   initializeSIOptimizeExecMaskingPreRAPass(*PR);
168   initializeSILoadStoreOptimizerPass(*PR);
169   initializeAMDGPUFixFunctionBitcastsPass(*PR);
170   initializeAMDGPUAlwaysInlinePass(*PR);
171   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
172   initializeAMDGPUAnnotateUniformValuesPass(*PR);
173   initializeAMDGPUArgumentUsageInfoPass(*PR);
174   initializeAMDGPUAtomicOptimizerPass(*PR);
175   initializeAMDGPULowerKernelArgumentsPass(*PR);
176   initializeAMDGPULowerKernelAttributesPass(*PR);
177   initializeAMDGPULowerIntrinsicsPass(*PR);
178   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
179   initializeAMDGPUPromoteAllocaPass(*PR);
180   initializeAMDGPUCodeGenPreparePass(*PR);
181   initializeAMDGPURewriteOutArgumentsPass(*PR);
182   initializeAMDGPUUnifyMetadataPass(*PR);
183   initializeSIAnnotateControlFlowPass(*PR);
184   initializeSIInsertWaitcntsPass(*PR);
185   initializeSIWholeQuadModePass(*PR);
186   initializeSILowerControlFlowPass(*PR);
187   initializeSIInsertSkipsPass(*PR);
188   initializeSIMemoryLegalizerPass(*PR);
189   initializeSIDebuggerInsertNopsPass(*PR);
190   initializeSIOptimizeExecMaskingPass(*PR);
191   initializeSIFixWWMLivenessPass(*PR);
192   initializeSIFormMemoryClausesPass(*PR);
193   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
194   initializeAMDGPUAAWrapperPassPass(*PR);
195   initializeAMDGPUExternalAAWrapperPass(*PR);
196   initializeAMDGPUUseNativeCallsPass(*PR);
197   initializeAMDGPUSimplifyLibCallsPass(*PR);
198   initializeAMDGPUInlinerPass(*PR);
199 }
200 
201 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
202   return llvm::make_unique<AMDGPUTargetObjectFile>();
203 }
204 
205 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
206   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
207 }
208 
209 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
210   return new SIScheduleDAGMI(C);
211 }
212 
213 static ScheduleDAGInstrs *
214 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
215   ScheduleDAGMILive *DAG =
216     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
217   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
218   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
219   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
220   return DAG;
221 }
222 
223 static ScheduleDAGInstrs *
224 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
225   auto DAG = new GCNIterativeScheduler(C,
226     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
227   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
228   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
229   return DAG;
230 }
231 
232 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
233   return new GCNIterativeScheduler(C,
234     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
235 }
236 
237 static ScheduleDAGInstrs *
238 createIterativeILPMachineScheduler(MachineSchedContext *C) {
239   auto DAG = new GCNIterativeScheduler(C,
240     GCNIterativeScheduler::SCHEDULE_ILP);
241   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
242   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
243   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
244   return DAG;
245 }
246 
247 static MachineSchedRegistry
248 R600SchedRegistry("r600", "Run R600's custom scheduler",
249                    createR600MachineScheduler);
250 
251 static MachineSchedRegistry
252 SISchedRegistry("si", "Run SI's custom scheduler",
253                 createSIMachineScheduler);
254 
255 static MachineSchedRegistry
256 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
257                              "Run GCN scheduler to maximize occupancy",
258                              createGCNMaxOccupancyMachineScheduler);
259 
260 static MachineSchedRegistry
261 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
262   "Run GCN scheduler to maximize occupancy (experimental)",
263   createIterativeGCNMaxOccupancyMachineScheduler);
264 
265 static MachineSchedRegistry
266 GCNMinRegSchedRegistry("gcn-minreg",
267   "Run GCN iterative scheduler for minimal register usage (experimental)",
268   createMinRegScheduler);
269 
270 static MachineSchedRegistry
271 GCNILPSchedRegistry("gcn-ilp",
272   "Run GCN iterative scheduler for ILP scheduling (experimental)",
273   createIterativeILPMachineScheduler);
274 
275 static StringRef computeDataLayout(const Triple &TT) {
276   if (TT.getArch() == Triple::r600) {
277     // 32-bit pointers.
278       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
279              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
280   }
281 
282   // 32-bit private, local, and region pointers. 64-bit global, constant and
283   // flat.
284     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
285          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
286          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
287 }
288 
289 LLVM_READNONE
290 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
291   if (!GPU.empty())
292     return GPU;
293 
294   if (TT.getArch() == Triple::amdgcn)
295     return "generic";
296 
297   return "r600";
298 }
299 
300 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
301   // The AMDGPU toolchain only supports generating shared objects, so we
302   // must always use PIC.
303   return Reloc::PIC_;
304 }
305 
306 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
307   if (CM)
308     return *CM;
309   return CodeModel::Small;
310 }
311 
312 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
313                                          StringRef CPU, StringRef FS,
314                                          TargetOptions Options,
315                                          Optional<Reloc::Model> RM,
316                                          Optional<CodeModel::Model> CM,
317                                          CodeGenOpt::Level OptLevel)
318     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
319                         FS, Options, getEffectiveRelocModel(RM),
320                         getEffectiveCodeModel(CM), OptLevel),
321       TLOF(createTLOF(getTargetTriple())) {
322   initAsmInfo();
323 }
324 
325 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
326 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
327 
328 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
329 
330 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
331   Attribute GPUAttr = F.getFnAttribute("target-cpu");
332   return GPUAttr.hasAttribute(Attribute::None) ?
333     getTargetCPU() : GPUAttr.getValueAsString();
334 }
335 
336 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
337   Attribute FSAttr = F.getFnAttribute("target-features");
338 
339   return FSAttr.hasAttribute(Attribute::None) ?
340     getTargetFeatureString() :
341     FSAttr.getValueAsString();
342 }
343 
344 /// Predicate for Internalize pass.
345 static bool mustPreserveGV(const GlobalValue &GV) {
346   if (const Function *F = dyn_cast<Function>(&GV))
347     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
348 
349   return !GV.use_empty();
350 }
351 
352 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
353   Builder.DivergentTarget = true;
354 
355   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
356   bool Internalize = InternalizeSymbols;
357   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
358   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
359   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
360 
361   if (EnableAMDGPUFunctionCalls) {
362     delete Builder.Inliner;
363     Builder.Inliner = createAMDGPUFunctionInliningPass();
364   }
365 
366   Builder.addExtension(
367     PassManagerBuilder::EP_ModuleOptimizerEarly,
368     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
369                                          legacy::PassManagerBase &PM) {
370       if (AMDGPUAA) {
371         PM.add(createAMDGPUAAWrapperPass());
372         PM.add(createAMDGPUExternalAAWrapperPass());
373       }
374       PM.add(createAMDGPUUnifyMetadataPass());
375       if (Internalize) {
376         PM.add(createInternalizePass(mustPreserveGV));
377         PM.add(createGlobalDCEPass());
378       }
379       if (EarlyInline)
380         PM.add(createAMDGPUAlwaysInlinePass(false));
381   });
382 
383   const auto &Opt = Options;
384   Builder.addExtension(
385     PassManagerBuilder::EP_EarlyAsPossible,
386     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
387                                       legacy::PassManagerBase &PM) {
388       if (AMDGPUAA) {
389         PM.add(createAMDGPUAAWrapperPass());
390         PM.add(createAMDGPUExternalAAWrapperPass());
391       }
392       PM.add(llvm::createAMDGPUUseNativeCallsPass());
393       if (LibCallSimplify)
394         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
395   });
396 
397   Builder.addExtension(
398     PassManagerBuilder::EP_CGSCCOptimizerLate,
399     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
400       // Add infer address spaces pass to the opt pipeline after inlining
401       // but before SROA to increase SROA opportunities.
402       PM.add(createInferAddressSpacesPass());
403 
404       // This should run after inlining to have any chance of doing anything,
405       // and before other cleanup optimizations.
406       PM.add(createAMDGPULowerKernelAttributesPass());
407   });
408 }
409 
410 //===----------------------------------------------------------------------===//
411 // R600 Target Machine (R600 -> Cayman)
412 //===----------------------------------------------------------------------===//
413 
414 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
415                                      StringRef CPU, StringRef FS,
416                                      TargetOptions Options,
417                                      Optional<Reloc::Model> RM,
418                                      Optional<CodeModel::Model> CM,
419                                      CodeGenOpt::Level OL, bool JIT)
420     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
421   setRequiresStructuredCFG(true);
422 }
423 
424 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
425   const Function &F) const {
426   StringRef GPU = getGPUName(F);
427   StringRef FS = getFeatureString(F);
428 
429   SmallString<128> SubtargetKey(GPU);
430   SubtargetKey.append(FS);
431 
432   auto &I = SubtargetMap[SubtargetKey];
433   if (!I) {
434     // This needs to be done before we create a new subtarget since any
435     // creation will depend on the TM and the code generation flags on the
436     // function that reside in TargetOptions.
437     resetTargetOptions(F);
438     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
439   }
440 
441   return I.get();
442 }
443 
444 TargetTransformInfo
445 R600TargetMachine::getTargetTransformInfo(const Function &F) {
446   return TargetTransformInfo(R600TTIImpl(this, F));
447 }
448 
449 //===----------------------------------------------------------------------===//
450 // GCN Target Machine (SI+)
451 //===----------------------------------------------------------------------===//
452 
453 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
454                                    StringRef CPU, StringRef FS,
455                                    TargetOptions Options,
456                                    Optional<Reloc::Model> RM,
457                                    Optional<CodeModel::Model> CM,
458                                    CodeGenOpt::Level OL, bool JIT)
459     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
460 
461 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
462   StringRef GPU = getGPUName(F);
463   StringRef FS = getFeatureString(F);
464 
465   SmallString<128> SubtargetKey(GPU);
466   SubtargetKey.append(FS);
467 
468   auto &I = SubtargetMap[SubtargetKey];
469   if (!I) {
470     // This needs to be done before we create a new subtarget since any
471     // creation will depend on the TM and the code generation flags on the
472     // function that reside in TargetOptions.
473     resetTargetOptions(F);
474     I = llvm::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
475   }
476 
477   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
478 
479   return I.get();
480 }
481 
482 TargetTransformInfo
483 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
484   return TargetTransformInfo(GCNTTIImpl(this, F));
485 }
486 
487 //===----------------------------------------------------------------------===//
488 // AMDGPU Pass Setup
489 //===----------------------------------------------------------------------===//
490 
491 namespace {
492 
493 class AMDGPUPassConfig : public TargetPassConfig {
494 public:
495   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
496     : TargetPassConfig(TM, PM) {
497     // Exceptions and StackMaps are not supported, so these passes will never do
498     // anything.
499     disablePass(&StackMapLivenessID);
500     disablePass(&FuncletLayoutID);
501   }
502 
503   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
504     return getTM<AMDGPUTargetMachine>();
505   }
506 
507   ScheduleDAGInstrs *
508   createMachineScheduler(MachineSchedContext *C) const override {
509     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
510     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
511     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
512     return DAG;
513   }
514 
515   void addEarlyCSEOrGVNPass();
516   void addStraightLineScalarOptimizationPasses();
517   void addIRPasses() override;
518   void addCodeGenPrepare() override;
519   bool addPreISel() override;
520   bool addInstSelector() override;
521   bool addGCPasses() override;
522 };
523 
524 class R600PassConfig final : public AMDGPUPassConfig {
525 public:
526   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
527     : AMDGPUPassConfig(TM, PM) {}
528 
529   ScheduleDAGInstrs *createMachineScheduler(
530     MachineSchedContext *C) const override {
531     return createR600MachineScheduler(C);
532   }
533 
534   bool addPreISel() override;
535   bool addInstSelector() override;
536   void addPreRegAlloc() override;
537   void addPreSched2() override;
538   void addPreEmitPass() override;
539 };
540 
541 class GCNPassConfig final : public AMDGPUPassConfig {
542 public:
543   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
544     : AMDGPUPassConfig(TM, PM) {
545     // It is necessary to know the register usage of the entire call graph.  We
546     // allow calls without EnableAMDGPUFunctionCalls if they are marked
547     // noinline, so this is always required.
548     setRequiresCodeGenSCCOrder(true);
549   }
550 
551   GCNTargetMachine &getGCNTargetMachine() const {
552     return getTM<GCNTargetMachine>();
553   }
554 
555   ScheduleDAGInstrs *
556   createMachineScheduler(MachineSchedContext *C) const override;
557 
558   bool addPreISel() override;
559   void addMachineSSAOptimization() override;
560   bool addILPOpts() override;
561   bool addInstSelector() override;
562   bool addIRTranslator() override;
563   bool addLegalizeMachineIR() override;
564   bool addRegBankSelect() override;
565   bool addGlobalInstructionSelect() override;
566   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
567   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
568   void addPreRegAlloc() override;
569   void addPostRegAlloc() override;
570   void addPreSched2() override;
571   void addPreEmitPass() override;
572 };
573 
574 } // end anonymous namespace
575 
576 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
577   if (getOptLevel() == CodeGenOpt::Aggressive)
578     addPass(createGVNPass());
579   else
580     addPass(createEarlyCSEPass());
581 }
582 
583 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
584   addPass(createLICMPass());
585   addPass(createSeparateConstOffsetFromGEPPass());
586   addPass(createSpeculativeExecutionPass());
587   // ReassociateGEPs exposes more opportunites for SLSR. See
588   // the example in reassociate-geps-and-slsr.ll.
589   addPass(createStraightLineStrengthReducePass());
590   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
591   // EarlyCSE can reuse.
592   addEarlyCSEOrGVNPass();
593   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
594   addPass(createNaryReassociatePass());
595   // NaryReassociate on GEPs creates redundant common expressions, so run
596   // EarlyCSE after it.
597   addPass(createEarlyCSEPass());
598 }
599 
600 void AMDGPUPassConfig::addIRPasses() {
601   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
602 
603   // There is no reason to run these.
604   disablePass(&StackMapLivenessID);
605   disablePass(&FuncletLayoutID);
606   disablePass(&PatchableFunctionID);
607 
608   addPass(createAtomicExpandPass());
609 
610   // This must occur before inlining, as the inliner will not look through
611   // bitcast calls.
612   addPass(createAMDGPUFixFunctionBitcastsPass());
613 
614   addPass(createAMDGPULowerIntrinsicsPass());
615 
616   // Function calls are not supported, so make sure we inline everything.
617   addPass(createAMDGPUAlwaysInlinePass());
618   addPass(createAlwaysInlinerLegacyPass());
619   // We need to add the barrier noop pass, otherwise adding the function
620   // inlining pass will cause all of the PassConfigs passes to be run
621   // one function at a time, which means if we have a nodule with two
622   // functions, then we will generate code for the first function
623   // without ever running any passes on the second.
624   addPass(createBarrierNoopPass());
625 
626   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
627     // TODO: May want to move later or split into an early and late one.
628 
629     addPass(createAMDGPUCodeGenPreparePass());
630   }
631 
632   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
633   if (TM.getTargetTriple().getArch() == Triple::r600)
634     addPass(createR600OpenCLImageTypeLoweringPass());
635 
636   // Replace OpenCL enqueued block function pointers with global variables.
637   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
638 
639   if (TM.getOptLevel() > CodeGenOpt::None) {
640     addPass(createInferAddressSpacesPass());
641     addPass(createAMDGPUPromoteAlloca());
642 
643     if (EnableSROA)
644       addPass(createSROAPass());
645 
646     addStraightLineScalarOptimizationPasses();
647 
648     if (EnableAMDGPUAliasAnalysis) {
649       addPass(createAMDGPUAAWrapperPass());
650       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
651                                              AAResults &AAR) {
652         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
653           AAR.addAAResult(WrapperPass->getResult());
654         }));
655     }
656   }
657 
658   TargetPassConfig::addIRPasses();
659 
660   // EarlyCSE is not always strong enough to clean up what LSR produces. For
661   // example, GVN can combine
662   //
663   //   %0 = add %a, %b
664   //   %1 = add %b, %a
665   //
666   // and
667   //
668   //   %0 = shl nsw %a, 2
669   //   %1 = shl %a, 2
670   //
671   // but EarlyCSE can do neither of them.
672   if (getOptLevel() != CodeGenOpt::None)
673     addEarlyCSEOrGVNPass();
674 }
675 
676 void AMDGPUPassConfig::addCodeGenPrepare() {
677   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
678       EnableLowerKernelArguments)
679     addPass(createAMDGPULowerKernelArgumentsPass());
680 
681   TargetPassConfig::addCodeGenPrepare();
682 
683   if (EnableLoadStoreVectorizer)
684     addPass(createLoadStoreVectorizerPass());
685 }
686 
687 bool AMDGPUPassConfig::addPreISel() {
688   addPass(createLowerSwitchPass());
689   addPass(createFlattenCFGPass());
690   return false;
691 }
692 
693 bool AMDGPUPassConfig::addInstSelector() {
694   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
695   return false;
696 }
697 
698 bool AMDGPUPassConfig::addGCPasses() {
699   // Do nothing. GC is not supported.
700   return false;
701 }
702 
703 //===----------------------------------------------------------------------===//
704 // R600 Pass Setup
705 //===----------------------------------------------------------------------===//
706 
707 bool R600PassConfig::addPreISel() {
708   AMDGPUPassConfig::addPreISel();
709 
710   if (EnableR600StructurizeCFG)
711     addPass(createStructurizeCFGPass());
712   return false;
713 }
714 
715 bool R600PassConfig::addInstSelector() {
716   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
717   return false;
718 }
719 
720 void R600PassConfig::addPreRegAlloc() {
721   addPass(createR600VectorRegMerger());
722 }
723 
724 void R600PassConfig::addPreSched2() {
725   addPass(createR600EmitClauseMarkers(), false);
726   if (EnableR600IfConvert)
727     addPass(&IfConverterID, false);
728   addPass(createR600ClauseMergePass(), false);
729 }
730 
731 void R600PassConfig::addPreEmitPass() {
732   addPass(createAMDGPUCFGStructurizerPass(), false);
733   addPass(createR600ExpandSpecialInstrsPass(), false);
734   addPass(&FinalizeMachineBundlesID, false);
735   addPass(createR600Packetizer(), false);
736   addPass(createR600ControlFlowFinalizer(), false);
737 }
738 
739 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
740   return new R600PassConfig(*this, PM);
741 }
742 
743 //===----------------------------------------------------------------------===//
744 // GCN Pass Setup
745 //===----------------------------------------------------------------------===//
746 
747 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
748   MachineSchedContext *C) const {
749   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
750   if (ST.enableSIScheduler())
751     return createSIMachineScheduler(C);
752   return createGCNMaxOccupancyMachineScheduler(C);
753 }
754 
755 bool GCNPassConfig::addPreISel() {
756   AMDGPUPassConfig::addPreISel();
757 
758   if (EnableAtomicOptimizations) {
759     addPass(createAMDGPUAtomicOptimizerPass());
760   }
761 
762   // FIXME: We need to run a pass to propagate the attributes when calls are
763   // supported.
764   addPass(createAMDGPUAnnotateKernelFeaturesPass());
765 
766   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
767   // regions formed by them.
768   addPass(&AMDGPUUnifyDivergentExitNodesID);
769   if (!LateCFGStructurize) {
770     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
771   }
772   addPass(createSinkingPass());
773   addPass(createAMDGPUAnnotateUniformValues());
774   if (!LateCFGStructurize) {
775     addPass(createSIAnnotateControlFlowPass());
776   }
777 
778   return false;
779 }
780 
781 void GCNPassConfig::addMachineSSAOptimization() {
782   TargetPassConfig::addMachineSSAOptimization();
783 
784   // We want to fold operands after PeepholeOptimizer has run (or as part of
785   // it), because it will eliminate extra copies making it easier to fold the
786   // real source operand. We want to eliminate dead instructions after, so that
787   // we see fewer uses of the copies. We then need to clean up the dead
788   // instructions leftover after the operands are folded as well.
789   //
790   // XXX - Can we get away without running DeadMachineInstructionElim again?
791   addPass(&SIFoldOperandsID);
792   addPass(&DeadMachineInstructionElimID);
793   addPass(&SILoadStoreOptimizerID);
794   if (EnableSDWAPeephole) {
795     addPass(&SIPeepholeSDWAID);
796     addPass(&EarlyMachineLICMID);
797     addPass(&MachineCSEID);
798     addPass(&SIFoldOperandsID);
799     addPass(&DeadMachineInstructionElimID);
800   }
801   addPass(createSIShrinkInstructionsPass());
802 }
803 
804 bool GCNPassConfig::addILPOpts() {
805   if (EnableEarlyIfConversion)
806     addPass(&EarlyIfConverterID);
807 
808   TargetPassConfig::addILPOpts();
809   return false;
810 }
811 
812 bool GCNPassConfig::addInstSelector() {
813   AMDGPUPassConfig::addInstSelector();
814   addPass(&SIFixSGPRCopiesID);
815   addPass(createSILowerI1CopiesPass());
816   return false;
817 }
818 
819 bool GCNPassConfig::addIRTranslator() {
820   addPass(new IRTranslator());
821   return false;
822 }
823 
824 bool GCNPassConfig::addLegalizeMachineIR() {
825   addPass(new Legalizer());
826   return false;
827 }
828 
829 bool GCNPassConfig::addRegBankSelect() {
830   addPass(new RegBankSelect());
831   return false;
832 }
833 
834 bool GCNPassConfig::addGlobalInstructionSelect() {
835   addPass(new InstructionSelect());
836   return false;
837 }
838 
839 void GCNPassConfig::addPreRegAlloc() {
840   if (LateCFGStructurize) {
841     addPass(createAMDGPUMachineCFGStructurizerPass());
842   }
843   addPass(createSIWholeQuadModePass());
844 }
845 
846 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
847   // FIXME: We have to disable the verifier here because of PHIElimination +
848   // TwoAddressInstructions disabling it.
849 
850   // This must be run immediately after phi elimination and before
851   // TwoAddressInstructions, otherwise the processing of the tied operand of
852   // SI_ELSE will introduce a copy of the tied operand source after the else.
853   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
854 
855   // This must be run after SILowerControlFlow, since it needs to use the
856   // machine-level CFG, but before register allocation.
857   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
858 
859   TargetPassConfig::addFastRegAlloc(RegAllocPass);
860 }
861 
862 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
863   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
864 
865   insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
866 
867   // This must be run immediately after phi elimination and before
868   // TwoAddressInstructions, otherwise the processing of the tied operand of
869   // SI_ELSE will introduce a copy of the tied operand source after the else.
870   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
871 
872   // This must be run after SILowerControlFlow, since it needs to use the
873   // machine-level CFG, but before register allocation.
874   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
875 
876   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
877 }
878 
879 void GCNPassConfig::addPostRegAlloc() {
880   addPass(&SIFixVGPRCopiesID);
881   addPass(&SIOptimizeExecMaskingID);
882   TargetPassConfig::addPostRegAlloc();
883 }
884 
885 void GCNPassConfig::addPreSched2() {
886 }
887 
888 void GCNPassConfig::addPreEmitPass() {
889   addPass(createSIMemoryLegalizerPass());
890   addPass(createSIInsertWaitcntsPass());
891   addPass(createSIShrinkInstructionsPass());
892 
893   // The hazard recognizer that runs as part of the post-ra scheduler does not
894   // guarantee to be able handle all hazards correctly. This is because if there
895   // are multiple scheduling regions in a basic block, the regions are scheduled
896   // bottom up, so when we begin to schedule a region we don't know what
897   // instructions were emitted directly before it.
898   //
899   // Here we add a stand-alone hazard recognizer pass which can handle all
900   // cases.
901   //
902   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
903   // be better for it to emit S_NOP <N> when possible.
904   addPass(&PostRAHazardRecognizerID);
905 
906   addPass(&SIInsertSkipsPassID);
907   addPass(createSIDebuggerInsertNopsPass());
908   addPass(&BranchRelaxationPassID);
909 }
910 
911 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
912   return new GCNPassConfig(*this, PM);
913 }
914