1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110   cl::desc("Enable AMDGPU Alias Analysis"),
111   cl::init(true));
112 
113 // Option to enable new waitcnt insertion pass.
114 static cl::opt<bool> EnableSIInsertWaitcntsPass(
115   "enable-si-insert-waitcnts",
116   cl::desc("Use new waitcnt insertion pass"),
117   cl::init(true));
118 
119 // Option to run late CFG structurizer
120 static cl::opt<bool, true> LateCFGStructurize(
121   "amdgpu-late-structurize",
122   cl::desc("Enable late CFG structurization"),
123   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
124   cl::Hidden);
125 
126 static cl::opt<bool> EnableAMDGPUFunctionCalls(
127   "amdgpu-function-calls",
128   cl::Hidden,
129   cl::desc("Enable AMDGPU function call support"),
130   cl::init(false));
131 
132 // Enable lib calls simplifications
133 static cl::opt<bool> EnableLibCallSimplify(
134   "amdgpu-simplify-libcall",
135   cl::desc("Enable mdgpu library simplifications"),
136   cl::init(true),
137   cl::Hidden);
138 
139 extern "C" void LLVMInitializeAMDGPUTarget() {
140   // Register the target
141   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
142   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
143 
144   PassRegistry *PR = PassRegistry::getPassRegistry();
145   initializeR600ClauseMergePassPass(*PR);
146   initializeR600ControlFlowFinalizerPass(*PR);
147   initializeR600PacketizerPass(*PR);
148   initializeR600ExpandSpecialInstrsPassPass(*PR);
149   initializeR600VectorRegMergerPass(*PR);
150   initializeGlobalISel(*PR);
151   initializeAMDGPUDAGToDAGISelPass(*PR);
152   initializeSILowerI1CopiesPass(*PR);
153   initializeSIFixSGPRCopiesPass(*PR);
154   initializeSIFixVGPRCopiesPass(*PR);
155   initializeSIFoldOperandsPass(*PR);
156   initializeSIPeepholeSDWAPass(*PR);
157   initializeSIShrinkInstructionsPass(*PR);
158   initializeSIOptimizeExecMaskingPreRAPass(*PR);
159   initializeSILoadStoreOptimizerPass(*PR);
160   initializeAMDGPUAlwaysInlinePass(*PR);
161   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
162   initializeAMDGPUAnnotateUniformValuesPass(*PR);
163   initializeAMDGPUArgumentUsageInfoPass(*PR);
164   initializeAMDGPULowerIntrinsicsPass(*PR);
165   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
166   initializeAMDGPUPromoteAllocaPass(*PR);
167   initializeAMDGPUCodeGenPreparePass(*PR);
168   initializeAMDGPURewriteOutArgumentsPass(*PR);
169   initializeAMDGPUUnifyMetadataPass(*PR);
170   initializeSIAnnotateControlFlowPass(*PR);
171   initializeSIInsertWaitsPass(*PR);
172   initializeSIInsertWaitcntsPass(*PR);
173   initializeSIWholeQuadModePass(*PR);
174   initializeSILowerControlFlowPass(*PR);
175   initializeSIInsertSkipsPass(*PR);
176   initializeSIMemoryLegalizerPass(*PR);
177   initializeSIDebuggerInsertNopsPass(*PR);
178   initializeSIOptimizeExecMaskingPass(*PR);
179   initializeSIFixWWMLivenessPass(*PR);
180   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
181   initializeAMDGPUAAWrapperPassPass(*PR);
182   initializeAMDGPUUseNativeCallsPass(*PR);
183   initializeAMDGPUSimplifyLibCallsPass(*PR);
184   initializeAMDGPUInlinerPass(*PR);
185 }
186 
187 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
188   return llvm::make_unique<AMDGPUTargetObjectFile>();
189 }
190 
191 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
192   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
193 }
194 
195 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
196   return new SIScheduleDAGMI(C);
197 }
198 
199 static ScheduleDAGInstrs *
200 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
201   ScheduleDAGMILive *DAG =
202     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
203   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
204   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
205   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
206   return DAG;
207 }
208 
209 static ScheduleDAGInstrs *
210 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
211   auto DAG = new GCNIterativeScheduler(C,
212     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
213   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
214   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
215   return DAG;
216 }
217 
218 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
219   return new GCNIterativeScheduler(C,
220     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
221 }
222 
223 static ScheduleDAGInstrs *
224 createIterativeILPMachineScheduler(MachineSchedContext *C) {
225   auto DAG = new GCNIterativeScheduler(C,
226     GCNIterativeScheduler::SCHEDULE_ILP);
227   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
228   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
229   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
230   return DAG;
231 }
232 
233 static MachineSchedRegistry
234 R600SchedRegistry("r600", "Run R600's custom scheduler",
235                    createR600MachineScheduler);
236 
237 static MachineSchedRegistry
238 SISchedRegistry("si", "Run SI's custom scheduler",
239                 createSIMachineScheduler);
240 
241 static MachineSchedRegistry
242 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
243                              "Run GCN scheduler to maximize occupancy",
244                              createGCNMaxOccupancyMachineScheduler);
245 
246 static MachineSchedRegistry
247 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
248   "Run GCN scheduler to maximize occupancy (experimental)",
249   createIterativeGCNMaxOccupancyMachineScheduler);
250 
251 static MachineSchedRegistry
252 GCNMinRegSchedRegistry("gcn-minreg",
253   "Run GCN iterative scheduler for minimal register usage (experimental)",
254   createMinRegScheduler);
255 
256 static MachineSchedRegistry
257 GCNILPSchedRegistry("gcn-ilp",
258   "Run GCN iterative scheduler for ILP scheduling (experimental)",
259   createIterativeILPMachineScheduler);
260 
261 static StringRef computeDataLayout(const Triple &TT) {
262   if (TT.getArch() == Triple::r600) {
263     // 32-bit pointers.
264       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
265              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
266   }
267 
268   // 32-bit private, local, and region pointers. 64-bit global, constant and
269   // flat.
270     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
271          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
272          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
273 }
274 
275 LLVM_READNONE
276 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
277   if (!GPU.empty())
278     return GPU;
279 
280   if (TT.getArch() == Triple::amdgcn)
281     return "generic";
282 
283   return "r600";
284 }
285 
286 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
287   // The AMDGPU toolchain only supports generating shared objects, so we
288   // must always use PIC.
289   return Reloc::PIC_;
290 }
291 
292 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
293   if (CM)
294     return *CM;
295   return CodeModel::Small;
296 }
297 
298 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
299                                          StringRef CPU, StringRef FS,
300                                          TargetOptions Options,
301                                          Optional<Reloc::Model> RM,
302                                          Optional<CodeModel::Model> CM,
303                                          CodeGenOpt::Level OptLevel)
304     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
305                         FS, Options, getEffectiveRelocModel(RM),
306                         getEffectiveCodeModel(CM), OptLevel),
307       TLOF(createTLOF(getTargetTriple())) {
308   AS = AMDGPU::getAMDGPUAS(TT);
309   initAsmInfo();
310 }
311 
312 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
313 
314 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
315 
316 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
317   Attribute GPUAttr = F.getFnAttribute("target-cpu");
318   return GPUAttr.hasAttribute(Attribute::None) ?
319     getTargetCPU() : GPUAttr.getValueAsString();
320 }
321 
322 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
323   Attribute FSAttr = F.getFnAttribute("target-features");
324 
325   return FSAttr.hasAttribute(Attribute::None) ?
326     getTargetFeatureString() :
327     FSAttr.getValueAsString();
328 }
329 
330 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
331   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
332       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
333         AAR.addAAResult(WrapperPass->getResult());
334       });
335 }
336 
337 /// Predicate for Internalize pass.
338 static bool mustPreserveGV(const GlobalValue &GV) {
339   if (const Function *F = dyn_cast<Function>(&GV))
340     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
341 
342   return !GV.use_empty();
343 }
344 
345 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
346   Builder.DivergentTarget = true;
347 
348   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
349   bool Internalize = InternalizeSymbols;
350   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
351   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
352   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
353 
354   if (EnableAMDGPUFunctionCalls) {
355     delete Builder.Inliner;
356     Builder.Inliner = createAMDGPUFunctionInliningPass();
357   }
358 
359   if (Internalize) {
360     // If we're generating code, we always have the whole program available. The
361     // relocations expected for externally visible functions aren't supported,
362     // so make sure every non-entry function is hidden.
363     Builder.addExtension(
364       PassManagerBuilder::EP_EnabledOnOptLevel0,
365       [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
366         PM.add(createInternalizePass(mustPreserveGV));
367       });
368   }
369 
370   Builder.addExtension(
371     PassManagerBuilder::EP_ModuleOptimizerEarly,
372     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
373                                          legacy::PassManagerBase &PM) {
374       if (AMDGPUAA) {
375         PM.add(createAMDGPUAAWrapperPass());
376         PM.add(createAMDGPUExternalAAWrapperPass());
377       }
378       PM.add(createAMDGPUUnifyMetadataPass());
379       if (Internalize) {
380         PM.add(createInternalizePass(mustPreserveGV));
381         PM.add(createGlobalDCEPass());
382       }
383       if (EarlyInline)
384         PM.add(createAMDGPUAlwaysInlinePass(false));
385   });
386 
387   const auto &Opt = Options;
388   Builder.addExtension(
389     PassManagerBuilder::EP_EarlyAsPossible,
390     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
391                                       legacy::PassManagerBase &PM) {
392       if (AMDGPUAA) {
393         PM.add(createAMDGPUAAWrapperPass());
394         PM.add(createAMDGPUExternalAAWrapperPass());
395       }
396       PM.add(llvm::createAMDGPUUseNativeCallsPass());
397       if (LibCallSimplify)
398         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
399   });
400 
401   Builder.addExtension(
402     PassManagerBuilder::EP_CGSCCOptimizerLate,
403     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
404       // Add infer address spaces pass to the opt pipeline after inlining
405       // but before SROA to increase SROA opportunities.
406       PM.add(createInferAddressSpacesPass());
407   });
408 }
409 
410 //===----------------------------------------------------------------------===//
411 // R600 Target Machine (R600 -> Cayman)
412 //===----------------------------------------------------------------------===//
413 
414 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
415                                      StringRef CPU, StringRef FS,
416                                      TargetOptions Options,
417                                      Optional<Reloc::Model> RM,
418                                      Optional<CodeModel::Model> CM,
419                                      CodeGenOpt::Level OL, bool JIT)
420     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
421   setRequiresStructuredCFG(true);
422 }
423 
424 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
425   const Function &F) const {
426   StringRef GPU = getGPUName(F);
427   StringRef FS = getFeatureString(F);
428 
429   SmallString<128> SubtargetKey(GPU);
430   SubtargetKey.append(FS);
431 
432   auto &I = SubtargetMap[SubtargetKey];
433   if (!I) {
434     // This needs to be done before we create a new subtarget since any
435     // creation will depend on the TM and the code generation flags on the
436     // function that reside in TargetOptions.
437     resetTargetOptions(F);
438     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
439   }
440 
441   return I.get();
442 }
443 
444 //===----------------------------------------------------------------------===//
445 // GCN Target Machine (SI+)
446 //===----------------------------------------------------------------------===//
447 
448 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
449                                    StringRef CPU, StringRef FS,
450                                    TargetOptions Options,
451                                    Optional<Reloc::Model> RM,
452                                    Optional<CodeModel::Model> CM,
453                                    CodeGenOpt::Level OL, bool JIT)
454     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
455 
456 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
457   StringRef GPU = getGPUName(F);
458   StringRef FS = getFeatureString(F);
459 
460   SmallString<128> SubtargetKey(GPU);
461   SubtargetKey.append(FS);
462 
463   auto &I = SubtargetMap[SubtargetKey];
464   if (!I) {
465     // This needs to be done before we create a new subtarget since any
466     // creation will depend on the TM and the code generation flags on the
467     // function that reside in TargetOptions.
468     resetTargetOptions(F);
469     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
470   }
471 
472   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
473 
474   return I.get();
475 }
476 
477 //===----------------------------------------------------------------------===//
478 // AMDGPU Pass Setup
479 //===----------------------------------------------------------------------===//
480 
481 namespace {
482 
483 class AMDGPUPassConfig : public TargetPassConfig {
484 public:
485   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
486     : TargetPassConfig(TM, PM) {
487     // Exceptions and StackMaps are not supported, so these passes will never do
488     // anything.
489     disablePass(&StackMapLivenessID);
490     disablePass(&FuncletLayoutID);
491   }
492 
493   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
494     return getTM<AMDGPUTargetMachine>();
495   }
496 
497   ScheduleDAGInstrs *
498   createMachineScheduler(MachineSchedContext *C) const override {
499     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
500     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
501     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
502     return DAG;
503   }
504 
505   void addEarlyCSEOrGVNPass();
506   void addStraightLineScalarOptimizationPasses();
507   void addIRPasses() override;
508   void addCodeGenPrepare() override;
509   bool addPreISel() override;
510   bool addInstSelector() override;
511   bool addGCPasses() override;
512 };
513 
514 class R600PassConfig final : public AMDGPUPassConfig {
515 public:
516   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
517     : AMDGPUPassConfig(TM, PM) {}
518 
519   ScheduleDAGInstrs *createMachineScheduler(
520     MachineSchedContext *C) const override {
521     return createR600MachineScheduler(C);
522   }
523 
524   bool addPreISel() override;
525   bool addInstSelector() override;
526   void addPreRegAlloc() override;
527   void addPreSched2() override;
528   void addPreEmitPass() override;
529 };
530 
531 class GCNPassConfig final : public AMDGPUPassConfig {
532 public:
533   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
534     : AMDGPUPassConfig(TM, PM) {
535     // It is necessary to know the register usage of the entire call graph.  We
536     // allow calls without EnableAMDGPUFunctionCalls if they are marked
537     // noinline, so this is always required.
538     setRequiresCodeGenSCCOrder(true);
539   }
540 
541   GCNTargetMachine &getGCNTargetMachine() const {
542     return getTM<GCNTargetMachine>();
543   }
544 
545   ScheduleDAGInstrs *
546   createMachineScheduler(MachineSchedContext *C) const override;
547 
548   bool addPreISel() override;
549   void addMachineSSAOptimization() override;
550   bool addILPOpts() override;
551   bool addInstSelector() override;
552   bool addIRTranslator() override;
553   bool addLegalizeMachineIR() override;
554   bool addRegBankSelect() override;
555   bool addGlobalInstructionSelect() override;
556   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
557   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
558   void addPreRegAlloc() override;
559   void addPostRegAlloc() override;
560   void addPreSched2() override;
561   void addPreEmitPass() override;
562 };
563 
564 } // end anonymous namespace
565 
566 TargetTransformInfo
567 AMDGPUTargetMachine::getTargetTransformInfo(const Function &F) {
568   return TargetTransformInfo(AMDGPUTTIImpl(this, F));
569 }
570 
571 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
572   if (getOptLevel() == CodeGenOpt::Aggressive)
573     addPass(createGVNPass());
574   else
575     addPass(createEarlyCSEPass());
576 }
577 
578 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
579   addPass(createSeparateConstOffsetFromGEPPass());
580   addPass(createSpeculativeExecutionPass());
581   // ReassociateGEPs exposes more opportunites for SLSR. See
582   // the example in reassociate-geps-and-slsr.ll.
583   addPass(createStraightLineStrengthReducePass());
584   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
585   // EarlyCSE can reuse.
586   addEarlyCSEOrGVNPass();
587   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
588   addPass(createNaryReassociatePass());
589   // NaryReassociate on GEPs creates redundant common expressions, so run
590   // EarlyCSE after it.
591   addPass(createEarlyCSEPass());
592 }
593 
594 void AMDGPUPassConfig::addIRPasses() {
595   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
596 
597   // There is no reason to run these.
598   disablePass(&StackMapLivenessID);
599   disablePass(&FuncletLayoutID);
600   disablePass(&PatchableFunctionID);
601 
602   addPass(createAMDGPULowerIntrinsicsPass());
603 
604   if (TM.getTargetTriple().getArch() == Triple::r600 ||
605       !EnableAMDGPUFunctionCalls) {
606     // Function calls are not supported, so make sure we inline everything.
607     addPass(createAMDGPUAlwaysInlinePass());
608     addPass(createAlwaysInlinerLegacyPass());
609     // We need to add the barrier noop pass, otherwise adding the function
610     // inlining pass will cause all of the PassConfigs passes to be run
611     // one function at a time, which means if we have a nodule with two
612     // functions, then we will generate code for the first function
613     // without ever running any passes on the second.
614     addPass(createBarrierNoopPass());
615   }
616 
617   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
618     // TODO: May want to move later or split into an early and late one.
619 
620     addPass(createAMDGPUCodeGenPreparePass());
621   }
622 
623   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
624   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
625 
626   // Replace OpenCL enqueued block function pointers with global variables.
627   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
628 
629   if (TM.getOptLevel() > CodeGenOpt::None) {
630     addPass(createInferAddressSpacesPass());
631     addPass(createAMDGPUPromoteAlloca());
632 
633     if (EnableSROA)
634       addPass(createSROAPass());
635 
636     addStraightLineScalarOptimizationPasses();
637 
638     if (EnableAMDGPUAliasAnalysis) {
639       addPass(createAMDGPUAAWrapperPass());
640       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
641                                              AAResults &AAR) {
642         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
643           AAR.addAAResult(WrapperPass->getResult());
644         }));
645     }
646   }
647 
648   TargetPassConfig::addIRPasses();
649 
650   // EarlyCSE is not always strong enough to clean up what LSR produces. For
651   // example, GVN can combine
652   //
653   //   %0 = add %a, %b
654   //   %1 = add %b, %a
655   //
656   // and
657   //
658   //   %0 = shl nsw %a, 2
659   //   %1 = shl %a, 2
660   //
661   // but EarlyCSE can do neither of them.
662   if (getOptLevel() != CodeGenOpt::None)
663     addEarlyCSEOrGVNPass();
664 }
665 
666 void AMDGPUPassConfig::addCodeGenPrepare() {
667   TargetPassConfig::addCodeGenPrepare();
668 
669   if (EnableLoadStoreVectorizer)
670     addPass(createLoadStoreVectorizerPass());
671 }
672 
673 bool AMDGPUPassConfig::addPreISel() {
674   addPass(createFlattenCFGPass());
675   return false;
676 }
677 
678 bool AMDGPUPassConfig::addInstSelector() {
679   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
680   return false;
681 }
682 
683 bool AMDGPUPassConfig::addGCPasses() {
684   // Do nothing. GC is not supported.
685   return false;
686 }
687 
688 //===----------------------------------------------------------------------===//
689 // R600 Pass Setup
690 //===----------------------------------------------------------------------===//
691 
692 bool R600PassConfig::addPreISel() {
693   AMDGPUPassConfig::addPreISel();
694 
695   if (EnableR600StructurizeCFG)
696     addPass(createStructurizeCFGPass());
697   return false;
698 }
699 
700 bool R600PassConfig::addInstSelector() {
701   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
702   return false;
703 }
704 
705 void R600PassConfig::addPreRegAlloc() {
706   addPass(createR600VectorRegMerger());
707 }
708 
709 void R600PassConfig::addPreSched2() {
710   addPass(createR600EmitClauseMarkers(), false);
711   if (EnableR600IfConvert)
712     addPass(&IfConverterID, false);
713   addPass(createR600ClauseMergePass(), false);
714 }
715 
716 void R600PassConfig::addPreEmitPass() {
717   addPass(createAMDGPUCFGStructurizerPass(), false);
718   addPass(createR600ExpandSpecialInstrsPass(), false);
719   addPass(&FinalizeMachineBundlesID, false);
720   addPass(createR600Packetizer(), false);
721   addPass(createR600ControlFlowFinalizer(), false);
722 }
723 
724 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
725   return new R600PassConfig(*this, PM);
726 }
727 
728 //===----------------------------------------------------------------------===//
729 // GCN Pass Setup
730 //===----------------------------------------------------------------------===//
731 
732 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
733   MachineSchedContext *C) const {
734   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
735   if (ST.enableSIScheduler())
736     return createSIMachineScheduler(C);
737   return createGCNMaxOccupancyMachineScheduler(C);
738 }
739 
740 bool GCNPassConfig::addPreISel() {
741   AMDGPUPassConfig::addPreISel();
742 
743   // FIXME: We need to run a pass to propagate the attributes when calls are
744   // supported.
745   addPass(createAMDGPUAnnotateKernelFeaturesPass());
746 
747   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
748   // regions formed by them.
749   addPass(&AMDGPUUnifyDivergentExitNodesID);
750   if (!LateCFGStructurize) {
751     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
752   }
753   addPass(createSinkingPass());
754   addPass(createAMDGPUAnnotateUniformValues());
755   if (!LateCFGStructurize) {
756     addPass(createSIAnnotateControlFlowPass());
757   }
758 
759   return false;
760 }
761 
762 void GCNPassConfig::addMachineSSAOptimization() {
763   TargetPassConfig::addMachineSSAOptimization();
764 
765   // We want to fold operands after PeepholeOptimizer has run (or as part of
766   // it), because it will eliminate extra copies making it easier to fold the
767   // real source operand. We want to eliminate dead instructions after, so that
768   // we see fewer uses of the copies. We then need to clean up the dead
769   // instructions leftover after the operands are folded as well.
770   //
771   // XXX - Can we get away without running DeadMachineInstructionElim again?
772   addPass(&SIFoldOperandsID);
773   addPass(&DeadMachineInstructionElimID);
774   addPass(&SILoadStoreOptimizerID);
775   if (EnableSDWAPeephole) {
776     addPass(&SIPeepholeSDWAID);
777     addPass(&EarlyMachineLICMID);
778     addPass(&MachineCSEID);
779     addPass(&SIFoldOperandsID);
780     addPass(&DeadMachineInstructionElimID);
781   }
782   addPass(createSIShrinkInstructionsPass());
783 }
784 
785 bool GCNPassConfig::addILPOpts() {
786   if (EnableEarlyIfConversion)
787     addPass(&EarlyIfConverterID);
788 
789   TargetPassConfig::addILPOpts();
790   return false;
791 }
792 
793 bool GCNPassConfig::addInstSelector() {
794   AMDGPUPassConfig::addInstSelector();
795   addPass(createSILowerI1CopiesPass());
796   addPass(&SIFixSGPRCopiesID);
797   return false;
798 }
799 
800 bool GCNPassConfig::addIRTranslator() {
801   addPass(new IRTranslator());
802   return false;
803 }
804 
805 bool GCNPassConfig::addLegalizeMachineIR() {
806   addPass(new Legalizer());
807   return false;
808 }
809 
810 bool GCNPassConfig::addRegBankSelect() {
811   addPass(new RegBankSelect());
812   return false;
813 }
814 
815 bool GCNPassConfig::addGlobalInstructionSelect() {
816   addPass(new InstructionSelect());
817   return false;
818 }
819 
820 void GCNPassConfig::addPreRegAlloc() {
821   if (LateCFGStructurize) {
822     addPass(createAMDGPUMachineCFGStructurizerPass());
823   }
824   addPass(createSIWholeQuadModePass());
825 }
826 
827 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
828   // FIXME: We have to disable the verifier here because of PHIElimination +
829   // TwoAddressInstructions disabling it.
830 
831   // This must be run immediately after phi elimination and before
832   // TwoAddressInstructions, otherwise the processing of the tied operand of
833   // SI_ELSE will introduce a copy of the tied operand source after the else.
834   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
835 
836   // This must be run after SILowerControlFlow, since it needs to use the
837   // machine-level CFG, but before register allocation.
838   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
839 
840   TargetPassConfig::addFastRegAlloc(RegAllocPass);
841 }
842 
843 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
844   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
845 
846   // This must be run immediately after phi elimination and before
847   // TwoAddressInstructions, otherwise the processing of the tied operand of
848   // SI_ELSE will introduce a copy of the tied operand source after the else.
849   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
850 
851   // This must be run after SILowerControlFlow, since it needs to use the
852   // machine-level CFG, but before register allocation.
853   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
854 
855   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
856 }
857 
858 void GCNPassConfig::addPostRegAlloc() {
859   addPass(&SIFixVGPRCopiesID);
860   addPass(&SIOptimizeExecMaskingID);
861   TargetPassConfig::addPostRegAlloc();
862 }
863 
864 void GCNPassConfig::addPreSched2() {
865 }
866 
867 void GCNPassConfig::addPreEmitPass() {
868   // The hazard recognizer that runs as part of the post-ra scheduler does not
869   // guarantee to be able handle all hazards correctly. This is because if there
870   // are multiple scheduling regions in a basic block, the regions are scheduled
871   // bottom up, so when we begin to schedule a region we don't know what
872   // instructions were emitted directly before it.
873   //
874   // Here we add a stand-alone hazard recognizer pass which can handle all
875   // cases.
876   addPass(&PostRAHazardRecognizerID);
877 
878   addPass(createSIMemoryLegalizerPass());
879   if (EnableSIInsertWaitcntsPass)
880     addPass(createSIInsertWaitcntsPass());
881   else
882     addPass(createSIInsertWaitsPass());
883   addPass(createSIShrinkInstructionsPass());
884   addPass(&SIInsertSkipsPassID);
885   addPass(createSIDebuggerInsertNopsPass());
886   addPass(&BranchRelaxationPassID);
887 }
888 
889 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
890   return new GCNPassConfig(*this, PM);
891 }
892