1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #ifdef LLVM_BUILD_GLOBAL_ISEL
23 #include "AMDGPURegisterBankInfo.h"
24 #endif
25 #include "AMDGPUTargetObjectFile.h"
26 #include "AMDGPUTargetTransformInfo.h"
27 #include "GCNIterativeScheduler.h"
28 #include "GCNSchedStrategy.h"
29 #include "R600MachineScheduler.h"
30 #include "SIMachineScheduler.h"
31 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/TargetPassConfig.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Transforms/IPO.h"
39 #include "llvm/Transforms/IPO/AlwaysInliner.h"
40 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
41 #include "llvm/Transforms/Scalar.h"
42 #include "llvm/Transforms/Scalar/GVN.h"
43 #include "llvm/Transforms/Vectorize.h"
44 #include "llvm/IR/Attributes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/LegacyPassManager.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Target/TargetLoweringObjectFile.h"
51 #include <memory>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool> EnableR600IfConvert(
72   "r600-if-convert",
73   cl::desc("Use if conversion pass"),
74   cl::ReallyHidden,
75   cl::init(true));
76 
77 // Option to disable vectorizer for tests.
78 static cl::opt<bool> EnableLoadStoreVectorizer(
79   "amdgpu-load-store-vectorizer",
80   cl::desc("Enable load store vectorizer"),
81   cl::init(true),
82   cl::Hidden);
83 
84 // Option to to control global loads scalarization
85 static cl::opt<bool> ScalarizeGlobal(
86   "amdgpu-scalarize-global-loads",
87   cl::desc("Enable global load scalarization"),
88   cl::init(false),
89   cl::Hidden);
90 
91 // Option to run internalize pass.
92 static cl::opt<bool> InternalizeSymbols(
93   "amdgpu-internalize-symbols",
94   cl::desc("Enable elimination of non-kernel functions and unused globals"),
95   cl::init(false),
96   cl::Hidden);
97 
98 // Option to inline all early.
99 static cl::opt<bool> EarlyInlineAll(
100   "amdgpu-early-inline-all",
101   cl::desc("Inline all functions early"),
102   cl::init(false),
103   cl::Hidden);
104 
105 static cl::opt<bool> EnableSDWAPeephole(
106   "amdgpu-sdwa-peephole",
107   cl::desc("Enable SDWA peepholer"),
108   cl::init(true));
109 
110 // Enable address space based alias analysis
111 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
112   cl::desc("Enable AMDGPU Alias Analysis"),
113   cl::init(true));
114 
115 // Option to enable new waitcnt insertion pass.
116 static cl::opt<bool> EnableSIInsertWaitcntsPass(
117   "enable-si-insert-waitcnts",
118   cl::desc("Use new waitcnt insertion pass"),
119   cl::init(false));
120 
121 extern "C" void LLVMInitializeAMDGPUTarget() {
122   // Register the target
123   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
124   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
125 
126   PassRegistry *PR = PassRegistry::getPassRegistry();
127   initializeSILowerI1CopiesPass(*PR);
128   initializeSIFixSGPRCopiesPass(*PR);
129   initializeSIFixVGPRCopiesPass(*PR);
130   initializeSIFoldOperandsPass(*PR);
131   initializeSIPeepholeSDWAPass(*PR);
132   initializeSIShrinkInstructionsPass(*PR);
133   initializeSIFixControlFlowLiveIntervalsPass(*PR);
134   initializeSILoadStoreOptimizerPass(*PR);
135   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
136   initializeAMDGPUAnnotateUniformValuesPass(*PR);
137   initializeAMDGPULowerIntrinsicsPass(*PR);
138   initializeAMDGPUPromoteAllocaPass(*PR);
139   initializeAMDGPUCodeGenPreparePass(*PR);
140   initializeAMDGPUUnifyMetadataPass(*PR);
141   initializeSIAnnotateControlFlowPass(*PR);
142   initializeSIInsertWaitsPass(*PR);
143   initializeSIInsertWaitcntsPass(*PR);
144   initializeSIWholeQuadModePass(*PR);
145   initializeSILowerControlFlowPass(*PR);
146   initializeSIInsertSkipsPass(*PR);
147   initializeSIDebuggerInsertNopsPass(*PR);
148   initializeSIOptimizeExecMaskingPass(*PR);
149   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
150   initializeAMDGPUAAWrapperPassPass(*PR);
151 }
152 
153 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
154   return llvm::make_unique<AMDGPUTargetObjectFile>();
155 }
156 
157 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
158   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
159 }
160 
161 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
162   return new SIScheduleDAGMI(C);
163 }
164 
165 static ScheduleDAGInstrs *
166 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
167   ScheduleDAGMILive *DAG =
168     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
169   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
170   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
171   return DAG;
172 }
173 
174 static ScheduleDAGInstrs *
175 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
176   auto DAG = new GCNIterativeScheduler(C,
177     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
178   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
179   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
180   return DAG;
181 }
182 
183 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
184   return new GCNIterativeScheduler(C,
185     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
186 }
187 
188 static MachineSchedRegistry
189 R600SchedRegistry("r600", "Run R600's custom scheduler",
190                    createR600MachineScheduler);
191 
192 static MachineSchedRegistry
193 SISchedRegistry("si", "Run SI's custom scheduler",
194                 createSIMachineScheduler);
195 
196 static MachineSchedRegistry
197 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
198                              "Run GCN scheduler to maximize occupancy",
199                              createGCNMaxOccupancyMachineScheduler);
200 
201 static MachineSchedRegistry
202 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
203   "Run GCN scheduler to maximize occupancy (experimental)",
204   createIterativeGCNMaxOccupancyMachineScheduler);
205 
206 static MachineSchedRegistry
207 GCNMinRegSchedRegistry("gcn-minreg",
208   "Run GCN iterative scheduler for minimal register usage (experimental)",
209   createMinRegScheduler);
210 
211 static StringRef computeDataLayout(const Triple &TT) {
212   if (TT.getArch() == Triple::r600) {
213     // 32-bit pointers.
214     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
215             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
216   }
217 
218   // 32-bit private, local, and region pointers. 64-bit global, constant and
219   // flat.
220   if (TT.getEnvironmentName() == "amdgiz" ||
221       TT.getEnvironmentName() == "amdgizcl")
222     return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
223          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
224          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
225   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
226       "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
227       "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
228 }
229 
230 LLVM_READNONE
231 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
232   if (!GPU.empty())
233     return GPU;
234 
235   // HSA only supports CI+, so change the default GPU to a CI for HSA.
236   if (TT.getArch() == Triple::amdgcn)
237     return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
238 
239   return "r600";
240 }
241 
242 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
243   // The AMDGPU toolchain only supports generating shared objects, so we
244   // must always use PIC.
245   return Reloc::PIC_;
246 }
247 
248 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
249                                          StringRef CPU, StringRef FS,
250                                          TargetOptions Options,
251                                          Optional<Reloc::Model> RM,
252                                          CodeModel::Model CM,
253                                          CodeGenOpt::Level OptLevel)
254   : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
255                       FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
256     TLOF(createTLOF(getTargetTriple())) {
257   AS = AMDGPU::getAMDGPUAS(TT);
258   initAsmInfo();
259 }
260 
261 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
262 
263 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
264   Attribute GPUAttr = F.getFnAttribute("target-cpu");
265   return GPUAttr.hasAttribute(Attribute::None) ?
266     getTargetCPU() : GPUAttr.getValueAsString();
267 }
268 
269 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
270   Attribute FSAttr = F.getFnAttribute("target-features");
271 
272   return FSAttr.hasAttribute(Attribute::None) ?
273     getTargetFeatureString() :
274     FSAttr.getValueAsString();
275 }
276 
277 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
278   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
279       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
280         AAR.addAAResult(WrapperPass->getResult());
281       });
282 }
283 
284 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
285   Builder.DivergentTarget = true;
286 
287   bool Internalize = InternalizeSymbols &&
288                      (getOptLevel() > CodeGenOpt::None) &&
289                      (getTargetTriple().getArch() == Triple::amdgcn);
290   bool EarlyInline = EarlyInlineAll &&
291                      (getOptLevel() > CodeGenOpt::None);
292   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && getOptLevel() > CodeGenOpt::None;
293 
294   Builder.addExtension(
295     PassManagerBuilder::EP_ModuleOptimizerEarly,
296     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
297                                          legacy::PassManagerBase &PM) {
298       if (AMDGPUAA) {
299         PM.add(createAMDGPUAAWrapperPass());
300         PM.add(createAMDGPUExternalAAWrapperPass());
301       }
302       PM.add(createAMDGPUUnifyMetadataPass());
303       if (Internalize) {
304         PM.add(createInternalizePass([=](const GlobalValue &GV) -> bool {
305           if (const Function *F = dyn_cast<Function>(&GV)) {
306             if (F->isDeclaration())
307                 return true;
308             switch (F->getCallingConv()) {
309             default:
310               return false;
311             case CallingConv::AMDGPU_VS:
312             case CallingConv::AMDGPU_HS:
313             case CallingConv::AMDGPU_GS:
314             case CallingConv::AMDGPU_PS:
315             case CallingConv::AMDGPU_CS:
316             case CallingConv::AMDGPU_KERNEL:
317             case CallingConv::SPIR_KERNEL:
318               return true;
319             }
320           }
321           return !GV.use_empty();
322         }));
323         PM.add(createGlobalDCEPass());
324       }
325       if (EarlyInline)
326         PM.add(createAMDGPUAlwaysInlinePass(false));
327   });
328 
329   Builder.addExtension(
330     PassManagerBuilder::EP_EarlyAsPossible,
331     [AMDGPUAA](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
332       if (AMDGPUAA) {
333         PM.add(createAMDGPUAAWrapperPass());
334         PM.add(createAMDGPUExternalAAWrapperPass());
335       }
336   });
337 }
338 
339 //===----------------------------------------------------------------------===//
340 // R600 Target Machine (R600 -> Cayman)
341 //===----------------------------------------------------------------------===//
342 
343 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
344                                      StringRef CPU, StringRef FS,
345                                      TargetOptions Options,
346                                      Optional<Reloc::Model> RM,
347                                      CodeModel::Model CM, CodeGenOpt::Level OL)
348   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
349   setRequiresStructuredCFG(true);
350 }
351 
352 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
353   const Function &F) const {
354   StringRef GPU = getGPUName(F);
355   StringRef FS = getFeatureString(F);
356 
357   SmallString<128> SubtargetKey(GPU);
358   SubtargetKey.append(FS);
359 
360   auto &I = SubtargetMap[SubtargetKey];
361   if (!I) {
362     // This needs to be done before we create a new subtarget since any
363     // creation will depend on the TM and the code generation flags on the
364     // function that reside in TargetOptions.
365     resetTargetOptions(F);
366     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
367   }
368 
369   return I.get();
370 }
371 
372 //===----------------------------------------------------------------------===//
373 // GCN Target Machine (SI+)
374 //===----------------------------------------------------------------------===//
375 
376 #ifdef LLVM_BUILD_GLOBAL_ISEL
377 namespace {
378 
379 struct SIGISelActualAccessor : public GISelAccessor {
380   std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
381   std::unique_ptr<InstructionSelector> InstSelector;
382   std::unique_ptr<LegalizerInfo> Legalizer;
383   std::unique_ptr<RegisterBankInfo> RegBankInfo;
384   const AMDGPUCallLowering *getCallLowering() const override {
385     return CallLoweringInfo.get();
386   }
387   const InstructionSelector *getInstructionSelector() const override {
388     return InstSelector.get();
389   }
390   const LegalizerInfo *getLegalizerInfo() const override {
391     return Legalizer.get();
392   }
393   const RegisterBankInfo *getRegBankInfo() const override {
394     return RegBankInfo.get();
395   }
396 };
397 
398 } // end anonymous namespace
399 #endif
400 
401 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
402                                    StringRef CPU, StringRef FS,
403                                    TargetOptions Options,
404                                    Optional<Reloc::Model> RM,
405                                    CodeModel::Model CM, CodeGenOpt::Level OL)
406   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
407 
408 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
409   StringRef GPU = getGPUName(F);
410   StringRef FS = getFeatureString(F);
411 
412   SmallString<128> SubtargetKey(GPU);
413   SubtargetKey.append(FS);
414 
415   auto &I = SubtargetMap[SubtargetKey];
416   if (!I) {
417     // This needs to be done before we create a new subtarget since any
418     // creation will depend on the TM and the code generation flags on the
419     // function that reside in TargetOptions.
420     resetTargetOptions(F);
421     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
422 
423 #ifndef LLVM_BUILD_GLOBAL_ISEL
424     GISelAccessor *GISel = new GISelAccessor();
425 #else
426     SIGISelActualAccessor *GISel = new SIGISelActualAccessor();
427     GISel->CallLoweringInfo.reset(
428       new AMDGPUCallLowering(*I->getTargetLowering()));
429     GISel->Legalizer.reset(new AMDGPULegalizerInfo());
430 
431     GISel->RegBankInfo.reset(new AMDGPURegisterBankInfo(*I->getRegisterInfo()));
432     GISel->InstSelector.reset(new AMDGPUInstructionSelector(*I,
433 				*static_cast<AMDGPURegisterBankInfo*>(GISel->RegBankInfo.get())));
434 #endif
435 
436     I->setGISelAccessor(*GISel);
437   }
438 
439   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
440 
441   return I.get();
442 }
443 
444 //===----------------------------------------------------------------------===//
445 // AMDGPU Pass Setup
446 //===----------------------------------------------------------------------===//
447 
448 namespace {
449 
450 class AMDGPUPassConfig : public TargetPassConfig {
451 public:
452   AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
453     : TargetPassConfig(TM, PM) {
454     // Exceptions and StackMaps are not supported, so these passes will never do
455     // anything.
456     disablePass(&StackMapLivenessID);
457     disablePass(&FuncletLayoutID);
458   }
459 
460   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
461     return getTM<AMDGPUTargetMachine>();
462   }
463 
464   ScheduleDAGInstrs *
465   createMachineScheduler(MachineSchedContext *C) const override {
466     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
467     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
468     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
469     return DAG;
470   }
471 
472   void addEarlyCSEOrGVNPass();
473   void addStraightLineScalarOptimizationPasses();
474   void addIRPasses() override;
475   void addCodeGenPrepare() override;
476   bool addPreISel() override;
477   bool addInstSelector() override;
478   bool addGCPasses() override;
479 };
480 
481 class R600PassConfig final : public AMDGPUPassConfig {
482 public:
483   R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
484     : AMDGPUPassConfig(TM, PM) {}
485 
486   ScheduleDAGInstrs *createMachineScheduler(
487     MachineSchedContext *C) const override {
488     return createR600MachineScheduler(C);
489   }
490 
491   bool addPreISel() override;
492   void addPreRegAlloc() override;
493   void addPreSched2() override;
494   void addPreEmitPass() override;
495 };
496 
497 class GCNPassConfig final : public AMDGPUPassConfig {
498 public:
499   GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
500     : AMDGPUPassConfig(TM, PM) {}
501 
502   GCNTargetMachine &getGCNTargetMachine() const {
503     return getTM<GCNTargetMachine>();
504   }
505 
506   ScheduleDAGInstrs *
507   createMachineScheduler(MachineSchedContext *C) const override;
508 
509   bool addPreISel() override;
510   void addMachineSSAOptimization() override;
511   bool addILPOpts() override;
512   bool addInstSelector() override;
513 #ifdef LLVM_BUILD_GLOBAL_ISEL
514   bool addIRTranslator() override;
515   bool addLegalizeMachineIR() override;
516   bool addRegBankSelect() override;
517   bool addGlobalInstructionSelect() override;
518 #endif
519   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
520   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
521   void addPreRegAlloc() override;
522   void addPostRegAlloc() override;
523   void addPreSched2() override;
524   void addPreEmitPass() override;
525 };
526 
527 } // end anonymous namespace
528 
529 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
530   return TargetIRAnalysis([this](const Function &F) {
531     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
532   });
533 }
534 
535 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
536   if (getOptLevel() == CodeGenOpt::Aggressive)
537     addPass(createGVNPass());
538   else
539     addPass(createEarlyCSEPass());
540 }
541 
542 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
543   addPass(createSeparateConstOffsetFromGEPPass());
544   addPass(createSpeculativeExecutionPass());
545   // ReassociateGEPs exposes more opportunites for SLSR. See
546   // the example in reassociate-geps-and-slsr.ll.
547   addPass(createStraightLineStrengthReducePass());
548   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
549   // EarlyCSE can reuse.
550   addEarlyCSEOrGVNPass();
551   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
552   addPass(createNaryReassociatePass());
553   // NaryReassociate on GEPs creates redundant common expressions, so run
554   // EarlyCSE after it.
555   addPass(createEarlyCSEPass());
556 }
557 
558 void AMDGPUPassConfig::addIRPasses() {
559   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
560 
561   // There is no reason to run these.
562   disablePass(&StackMapLivenessID);
563   disablePass(&FuncletLayoutID);
564   disablePass(&PatchableFunctionID);
565 
566   addPass(createAMDGPULowerIntrinsicsPass(&TM));
567 
568   // Function calls are not supported, so make sure we inline everything.
569   addPass(createAMDGPUAlwaysInlinePass());
570   addPass(createAlwaysInlinerLegacyPass());
571   // We need to add the barrier noop pass, otherwise adding the function
572   // inlining pass will cause all of the PassConfigs passes to be run
573   // one function at a time, which means if we have a nodule with two
574   // functions, then we will generate code for the first function
575   // without ever running any passes on the second.
576   addPass(createBarrierNoopPass());
577 
578   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
579     // TODO: May want to move later or split into an early and late one.
580 
581     addPass(createAMDGPUCodeGenPreparePass(
582               static_cast<const GCNTargetMachine *>(&TM)));
583   }
584 
585   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
586   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
587 
588   if (TM.getOptLevel() > CodeGenOpt::None) {
589     addPass(createInferAddressSpacesPass());
590     addPass(createAMDGPUPromoteAlloca(&TM));
591 
592     if (EnableSROA)
593       addPass(createSROAPass());
594 
595     addStraightLineScalarOptimizationPasses();
596 
597     if (EnableAMDGPUAliasAnalysis) {
598       addPass(createAMDGPUAAWrapperPass());
599       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
600                                              AAResults &AAR) {
601         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
602           AAR.addAAResult(WrapperPass->getResult());
603         }));
604     }
605   }
606 
607   TargetPassConfig::addIRPasses();
608 
609   // EarlyCSE is not always strong enough to clean up what LSR produces. For
610   // example, GVN can combine
611   //
612   //   %0 = add %a, %b
613   //   %1 = add %b, %a
614   //
615   // and
616   //
617   //   %0 = shl nsw %a, 2
618   //   %1 = shl %a, 2
619   //
620   // but EarlyCSE can do neither of them.
621   if (getOptLevel() != CodeGenOpt::None)
622     addEarlyCSEOrGVNPass();
623 }
624 
625 void AMDGPUPassConfig::addCodeGenPrepare() {
626   TargetPassConfig::addCodeGenPrepare();
627 
628   if (EnableLoadStoreVectorizer)
629     addPass(createLoadStoreVectorizerPass());
630 }
631 
632 bool AMDGPUPassConfig::addPreISel() {
633   addPass(createFlattenCFGPass());
634   return false;
635 }
636 
637 bool AMDGPUPassConfig::addInstSelector() {
638   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));
639   return false;
640 }
641 
642 bool AMDGPUPassConfig::addGCPasses() {
643   // Do nothing. GC is not supported.
644   return false;
645 }
646 
647 //===----------------------------------------------------------------------===//
648 // R600 Pass Setup
649 //===----------------------------------------------------------------------===//
650 
651 bool R600PassConfig::addPreISel() {
652   AMDGPUPassConfig::addPreISel();
653 
654   if (EnableR600StructurizeCFG)
655     addPass(createStructurizeCFGPass());
656   return false;
657 }
658 
659 void R600PassConfig::addPreRegAlloc() {
660   addPass(createR600VectorRegMerger(*TM));
661 }
662 
663 void R600PassConfig::addPreSched2() {
664   addPass(createR600EmitClauseMarkers(), false);
665   if (EnableR600IfConvert)
666     addPass(&IfConverterID, false);
667   addPass(createR600ClauseMergePass(*TM), false);
668 }
669 
670 void R600PassConfig::addPreEmitPass() {
671   addPass(createAMDGPUCFGStructurizerPass(), false);
672   addPass(createR600ExpandSpecialInstrsPass(*TM), false);
673   addPass(&FinalizeMachineBundlesID, false);
674   addPass(createR600Packetizer(*TM), false);
675   addPass(createR600ControlFlowFinalizer(*TM), false);
676 }
677 
678 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
679   return new R600PassConfig(this, PM);
680 }
681 
682 //===----------------------------------------------------------------------===//
683 // GCN Pass Setup
684 //===----------------------------------------------------------------------===//
685 
686 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
687   MachineSchedContext *C) const {
688   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
689   if (ST.enableSIScheduler())
690     return createSIMachineScheduler(C);
691   return createGCNMaxOccupancyMachineScheduler(C);
692 }
693 
694 bool GCNPassConfig::addPreISel() {
695   AMDGPUPassConfig::addPreISel();
696 
697   // FIXME: We need to run a pass to propagate the attributes when calls are
698   // supported.
699   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
700   addPass(createAMDGPUAnnotateKernelFeaturesPass(&TM));
701 
702   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
703   // regions formed by them.
704   addPass(&AMDGPUUnifyDivergentExitNodesID);
705   addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
706   addPass(createSinkingPass());
707   addPass(createSITypeRewriter());
708   addPass(createAMDGPUAnnotateUniformValues());
709   addPass(createSIAnnotateControlFlowPass());
710 
711   return false;
712 }
713 
714 void GCNPassConfig::addMachineSSAOptimization() {
715   TargetPassConfig::addMachineSSAOptimization();
716 
717   // We want to fold operands after PeepholeOptimizer has run (or as part of
718   // it), because it will eliminate extra copies making it easier to fold the
719   // real source operand. We want to eliminate dead instructions after, so that
720   // we see fewer uses of the copies. We then need to clean up the dead
721   // instructions leftover after the operands are folded as well.
722   //
723   // XXX - Can we get away without running DeadMachineInstructionElim again?
724   addPass(&SIFoldOperandsID);
725   addPass(&DeadMachineInstructionElimID);
726   addPass(&SILoadStoreOptimizerID);
727   addPass(createSIShrinkInstructionsPass());
728   if (EnableSDWAPeephole) {
729     addPass(&SIPeepholeSDWAID);
730     addPass(&DeadMachineInstructionElimID);
731   }
732 }
733 
734 bool GCNPassConfig::addILPOpts() {
735   if (EnableEarlyIfConversion)
736     addPass(&EarlyIfConverterID);
737 
738   TargetPassConfig::addILPOpts();
739   return false;
740 }
741 
742 bool GCNPassConfig::addInstSelector() {
743   AMDGPUPassConfig::addInstSelector();
744   addPass(createSILowerI1CopiesPass());
745   addPass(&SIFixSGPRCopiesID);
746   return false;
747 }
748 
749 #ifdef LLVM_BUILD_GLOBAL_ISEL
750 bool GCNPassConfig::addIRTranslator() {
751   addPass(new IRTranslator());
752   return false;
753 }
754 
755 bool GCNPassConfig::addLegalizeMachineIR() {
756   addPass(new Legalizer());
757   return false;
758 }
759 
760 bool GCNPassConfig::addRegBankSelect() {
761   addPass(new RegBankSelect());
762   return false;
763 }
764 
765 bool GCNPassConfig::addGlobalInstructionSelect() {
766   addPass(new InstructionSelect());
767   return false;
768 }
769 
770 #endif
771 
772 void GCNPassConfig::addPreRegAlloc() {
773   addPass(createSIWholeQuadModePass());
774 }
775 
776 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
777   // FIXME: We have to disable the verifier here because of PHIElimination +
778   // TwoAddressInstructions disabling it.
779 
780   // This must be run immediately after phi elimination and before
781   // TwoAddressInstructions, otherwise the processing of the tied operand of
782   // SI_ELSE will introduce a copy of the tied operand source after the else.
783   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
784 
785   TargetPassConfig::addFastRegAlloc(RegAllocPass);
786 }
787 
788 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
789   // This needs to be run directly before register allocation because earlier
790   // passes might recompute live intervals.
791   insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
792 
793   // This must be run immediately after phi elimination and before
794   // TwoAddressInstructions, otherwise the processing of the tied operand of
795   // SI_ELSE will introduce a copy of the tied operand source after the else.
796   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
797 
798   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
799 }
800 
801 void GCNPassConfig::addPostRegAlloc() {
802   addPass(&SIFixVGPRCopiesID);
803   addPass(&SIOptimizeExecMaskingID);
804   TargetPassConfig::addPostRegAlloc();
805 }
806 
807 void GCNPassConfig::addPreSched2() {
808 }
809 
810 void GCNPassConfig::addPreEmitPass() {
811   // The hazard recognizer that runs as part of the post-ra scheduler does not
812   // guarantee to be able handle all hazards correctly. This is because if there
813   // are multiple scheduling regions in a basic block, the regions are scheduled
814   // bottom up, so when we begin to schedule a region we don't know what
815   // instructions were emitted directly before it.
816   //
817   // Here we add a stand-alone hazard recognizer pass which can handle all
818   // cases.
819   addPass(&PostRAHazardRecognizerID);
820 
821   if (EnableSIInsertWaitcntsPass)
822     addPass(createSIInsertWaitcntsPass());
823   else
824     addPass(createSIInsertWaitsPass());
825   addPass(createSIShrinkInstructionsPass());
826   addPass(&SIInsertSkipsPassID);
827   addPass(createSIDebuggerInsertNopsPass());
828   addPass(&BranchRelaxationPassID);
829 }
830 
831 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
832   return new GCNPassConfig(this, PM);
833 }
834 
835