1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUExportClustering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
28 #include "R600MachineScheduler.h"
29 #include "SIMachineFunctionInfo.h"
30 #include "SIMachineScheduler.h"
31 #include "TargetInfo/AMDGPUTargetInfo.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
35 #include "llvm/CodeGen/GlobalISel/Localizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MIRParser/MIParser.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/LegacyPassManager.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/Pass.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Transforms/IPO.h"
50 #include "llvm/Transforms/IPO/AlwaysInliner.h"
51 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
52 #include "llvm/Transforms/Scalar.h"
53 #include "llvm/Transforms/Scalar/GVN.h"
54 #include "llvm/Transforms/Utils.h"
55 #include "llvm/Transforms/Vectorize.h"
56 #include <memory>
57 
58 using namespace llvm;
59 
60 static cl::opt<bool> EnableR600StructurizeCFG(
61   "r600-ir-structurize",
62   cl::desc("Use StructurizeCFG IR pass"),
63   cl::init(true));
64 
65 static cl::opt<bool> EnableSROA(
66   "amdgpu-sroa",
67   cl::desc("Run SROA after promote alloca pass"),
68   cl::ReallyHidden,
69   cl::init(true));
70 
71 static cl::opt<bool>
72 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
73                         cl::desc("Run early if-conversion"),
74                         cl::init(false));
75 
76 static cl::opt<bool>
77 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
78             cl::desc("Run pre-RA exec mask optimizations"),
79             cl::init(true));
80 
81 static cl::opt<bool> EnableR600IfConvert(
82   "r600-if-convert",
83   cl::desc("Use if conversion pass"),
84   cl::ReallyHidden,
85   cl::init(true));
86 
87 // Option to disable vectorizer for tests.
88 static cl::opt<bool> EnableLoadStoreVectorizer(
89   "amdgpu-load-store-vectorizer",
90   cl::desc("Enable load store vectorizer"),
91   cl::init(true),
92   cl::Hidden);
93 
94 // Option to control global loads scalarization
95 static cl::opt<bool> ScalarizeGlobal(
96   "amdgpu-scalarize-global-loads",
97   cl::desc("Enable global load scalarization"),
98   cl::init(true),
99   cl::Hidden);
100 
101 // Option to run internalize pass.
102 static cl::opt<bool> InternalizeSymbols(
103   "amdgpu-internalize-symbols",
104   cl::desc("Enable elimination of non-kernel functions and unused globals"),
105   cl::init(false),
106   cl::Hidden);
107 
108 // Option to inline all early.
109 static cl::opt<bool> EarlyInlineAll(
110   "amdgpu-early-inline-all",
111   cl::desc("Inline all functions early"),
112   cl::init(false),
113   cl::Hidden);
114 
115 static cl::opt<bool> EnableSDWAPeephole(
116   "amdgpu-sdwa-peephole",
117   cl::desc("Enable SDWA peepholer"),
118   cl::init(true));
119 
120 static cl::opt<bool> EnableDPPCombine(
121   "amdgpu-dpp-combine",
122   cl::desc("Enable DPP combiner"),
123   cl::init(true));
124 
125 // Enable address space based alias analysis
126 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
127   cl::desc("Enable AMDGPU Alias Analysis"),
128   cl::init(true));
129 
130 // Option to run late CFG structurizer
131 static cl::opt<bool, true> LateCFGStructurize(
132   "amdgpu-late-structurize",
133   cl::desc("Enable late CFG structurization"),
134   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
135   cl::Hidden);
136 
137 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
138   "amdgpu-function-calls",
139   cl::desc("Enable AMDGPU function call support"),
140   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
141   cl::init(true),
142   cl::Hidden);
143 
144 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
145   "amdgpu-fixed-function-abi",
146   cl::desc("Enable all implicit function arguments"),
147   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
148   cl::init(false),
149   cl::Hidden);
150 
151 // Enable lib calls simplifications
152 static cl::opt<bool> EnableLibCallSimplify(
153   "amdgpu-simplify-libcall",
154   cl::desc("Enable amdgpu library simplifications"),
155   cl::init(true),
156   cl::Hidden);
157 
158 static cl::opt<bool> EnableLowerKernelArguments(
159   "amdgpu-ir-lower-kernel-arguments",
160   cl::desc("Lower kernel argument loads in IR pass"),
161   cl::init(true),
162   cl::Hidden);
163 
164 static cl::opt<bool> EnableRegReassign(
165   "amdgpu-reassign-regs",
166   cl::desc("Enable register reassign optimizations on gfx10+"),
167   cl::init(true),
168   cl::Hidden);
169 
170 // Enable atomic optimization
171 static cl::opt<bool> EnableAtomicOptimizations(
172   "amdgpu-atomic-optimizations",
173   cl::desc("Enable atomic optimizations"),
174   cl::init(false),
175   cl::Hidden);
176 
177 // Enable Mode register optimization
178 static cl::opt<bool> EnableSIModeRegisterPass(
179   "amdgpu-mode-register",
180   cl::desc("Enable mode register pass"),
181   cl::init(true),
182   cl::Hidden);
183 
184 // Option is used in lit tests to prevent deadcoding of patterns inspected.
185 static cl::opt<bool>
186 EnableDCEInRA("amdgpu-dce-in-ra",
187     cl::init(true), cl::Hidden,
188     cl::desc("Enable machine DCE inside regalloc"));
189 
190 static cl::opt<bool> EnableScalarIRPasses(
191   "amdgpu-scalar-ir-passes",
192   cl::desc("Enable scalar IR passes"),
193   cl::init(true),
194   cl::Hidden);
195 
196 static cl::opt<bool> EnableStructurizerWorkarounds(
197     "amdgpu-enable-structurizer-workarounds",
198     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
199     cl::Hidden);
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFoldOperandsPass(*PR);
220   initializeSIPeepholeSDWAPass(*PR);
221   initializeSIShrinkInstructionsPass(*PR);
222   initializeSIOptimizeExecMaskingPreRAPass(*PR);
223   initializeSILoadStoreOptimizerPass(*PR);
224   initializeAMDGPUFixFunctionBitcastsPass(*PR);
225   initializeAMDGPUAlwaysInlinePass(*PR);
226   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
227   initializeAMDGPUAnnotateUniformValuesPass(*PR);
228   initializeAMDGPUArgumentUsageInfoPass(*PR);
229   initializeAMDGPUAtomicOptimizerPass(*PR);
230   initializeAMDGPULowerKernelArgumentsPass(*PR);
231   initializeAMDGPULowerKernelAttributesPass(*PR);
232   initializeAMDGPULowerIntrinsicsPass(*PR);
233   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
234   initializeAMDGPUPostLegalizerCombinerPass(*PR);
235   initializeAMDGPUPreLegalizerCombinerPass(*PR);
236   initializeAMDGPUPromoteAllocaPass(*PR);
237   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
238   initializeAMDGPUCodeGenPreparePass(*PR);
239   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
240   initializeAMDGPUPropagateAttributesLatePass(*PR);
241   initializeAMDGPURewriteOutArgumentsPass(*PR);
242   initializeAMDGPUUnifyMetadataPass(*PR);
243   initializeSIAnnotateControlFlowPass(*PR);
244   initializeSIInsertHardClausesPass(*PR);
245   initializeSIInsertWaitcntsPass(*PR);
246   initializeSIModeRegisterPass(*PR);
247   initializeSIWholeQuadModePass(*PR);
248   initializeSILowerControlFlowPass(*PR);
249   initializeSIRemoveShortExecBranchesPass(*PR);
250   initializeSIPreEmitPeepholePass(*PR);
251   initializeSIInsertSkipsPass(*PR);
252   initializeSIMemoryLegalizerPass(*PR);
253   initializeSIOptimizeExecMaskingPass(*PR);
254   initializeSIPreAllocateWWMRegsPass(*PR);
255   initializeSIFormMemoryClausesPass(*PR);
256   initializeSIPostRABundlerPass(*PR);
257   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
258   initializeAMDGPUAAWrapperPassPass(*PR);
259   initializeAMDGPUExternalAAWrapperPass(*PR);
260   initializeAMDGPUUseNativeCallsPass(*PR);
261   initializeAMDGPUSimplifyLibCallsPass(*PR);
262   initializeAMDGPUInlinerPass(*PR);
263   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
264   initializeGCNRegBankReassignPass(*PR);
265   initializeGCNNSAReassignPass(*PR);
266   initializeSIAddIMGInitPass(*PR);
267 }
268 
269 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
270   return std::make_unique<AMDGPUTargetObjectFile>();
271 }
272 
273 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
274   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
275 }
276 
277 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
278   return new SIScheduleDAGMI(C);
279 }
280 
281 static ScheduleDAGInstrs *
282 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
283   ScheduleDAGMILive *DAG =
284     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
285   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
286   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
287   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
288   return DAG;
289 }
290 
291 static ScheduleDAGInstrs *
292 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
293   auto DAG = new GCNIterativeScheduler(C,
294     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
295   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
296   return DAG;
297 }
298 
299 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
300   return new GCNIterativeScheduler(C,
301     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
302 }
303 
304 static ScheduleDAGInstrs *
305 createIterativeILPMachineScheduler(MachineSchedContext *C) {
306   auto DAG = new GCNIterativeScheduler(C,
307     GCNIterativeScheduler::SCHEDULE_ILP);
308   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
309   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
310   return DAG;
311 }
312 
313 static MachineSchedRegistry
314 R600SchedRegistry("r600", "Run R600's custom scheduler",
315                    createR600MachineScheduler);
316 
317 static MachineSchedRegistry
318 SISchedRegistry("si", "Run SI's custom scheduler",
319                 createSIMachineScheduler);
320 
321 static MachineSchedRegistry
322 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
323                              "Run GCN scheduler to maximize occupancy",
324                              createGCNMaxOccupancyMachineScheduler);
325 
326 static MachineSchedRegistry
327 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
328   "Run GCN scheduler to maximize occupancy (experimental)",
329   createIterativeGCNMaxOccupancyMachineScheduler);
330 
331 static MachineSchedRegistry
332 GCNMinRegSchedRegistry("gcn-minreg",
333   "Run GCN iterative scheduler for minimal register usage (experimental)",
334   createMinRegScheduler);
335 
336 static MachineSchedRegistry
337 GCNILPSchedRegistry("gcn-ilp",
338   "Run GCN iterative scheduler for ILP scheduling (experimental)",
339   createIterativeILPMachineScheduler);
340 
341 static StringRef computeDataLayout(const Triple &TT) {
342   if (TT.getArch() == Triple::r600) {
343     // 32-bit pointers.
344       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
345              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
346   }
347 
348   // 32-bit private, local, and region pointers. 64-bit global, constant and
349   // flat, non-integral buffer fat pointers.
350     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
351          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
352          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
353          "-ni:7";
354 }
355 
356 LLVM_READNONE
357 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
358   if (!GPU.empty())
359     return GPU;
360 
361   // Need to default to a target with flat support for HSA.
362   if (TT.getArch() == Triple::amdgcn)
363     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
364 
365   return "r600";
366 }
367 
368 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
369   // The AMDGPU toolchain only supports generating shared objects, so we
370   // must always use PIC.
371   return Reloc::PIC_;
372 }
373 
374 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
375                                          StringRef CPU, StringRef FS,
376                                          TargetOptions Options,
377                                          Optional<Reloc::Model> RM,
378                                          Optional<CodeModel::Model> CM,
379                                          CodeGenOpt::Level OptLevel)
380     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
381                         FS, Options, getEffectiveRelocModel(RM),
382                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
383       TLOF(createTLOF(getTargetTriple())) {
384   initAsmInfo();
385   if (TT.getArch() == Triple::amdgcn) {
386     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
387       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
388     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
389       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
390   }
391 }
392 
393 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
394 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
395 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
396 
397 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
398 
399 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
400   Attribute GPUAttr = F.getFnAttribute("target-cpu");
401   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
402 }
403 
404 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
405   Attribute FSAttr = F.getFnAttribute("target-features");
406 
407   return FSAttr.isValid() ? FSAttr.getValueAsString()
408                           : getTargetFeatureString();
409 }
410 
411 /// Predicate for Internalize pass.
412 static bool mustPreserveGV(const GlobalValue &GV) {
413   if (const Function *F = dyn_cast<Function>(&GV))
414     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
415 
416   return !GV.use_empty();
417 }
418 
419 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
420   Builder.DivergentTarget = true;
421 
422   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
423   bool Internalize = InternalizeSymbols;
424   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
425   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
426   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
427 
428   if (EnableFunctionCalls) {
429     delete Builder.Inliner;
430     Builder.Inliner = createAMDGPUFunctionInliningPass();
431   }
432 
433   Builder.addExtension(
434     PassManagerBuilder::EP_ModuleOptimizerEarly,
435     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
436                                                legacy::PassManagerBase &PM) {
437       if (AMDGPUAA) {
438         PM.add(createAMDGPUAAWrapperPass());
439         PM.add(createAMDGPUExternalAAWrapperPass());
440       }
441       PM.add(createAMDGPUUnifyMetadataPass());
442       PM.add(createAMDGPUPrintfRuntimeBinding());
443       if (Internalize)
444         PM.add(createInternalizePass(mustPreserveGV));
445       PM.add(createAMDGPUPropagateAttributesLatePass(this));
446       if (Internalize)
447         PM.add(createGlobalDCEPass());
448       if (EarlyInline)
449         PM.add(createAMDGPUAlwaysInlinePass(false));
450   });
451 
452   Builder.addExtension(
453     PassManagerBuilder::EP_EarlyAsPossible,
454     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
455                                       legacy::PassManagerBase &PM) {
456       if (AMDGPUAA) {
457         PM.add(createAMDGPUAAWrapperPass());
458         PM.add(createAMDGPUExternalAAWrapperPass());
459       }
460       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
461       PM.add(llvm::createAMDGPUUseNativeCallsPass());
462       if (LibCallSimplify)
463         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
464   });
465 
466   Builder.addExtension(
467     PassManagerBuilder::EP_CGSCCOptimizerLate,
468     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
469       // Add infer address spaces pass to the opt pipeline after inlining
470       // but before SROA to increase SROA opportunities.
471       PM.add(createInferAddressSpacesPass());
472 
473       // This should run after inlining to have any chance of doing anything,
474       // and before other cleanup optimizations.
475       PM.add(createAMDGPULowerKernelAttributesPass());
476 
477       // Promote alloca to vector before SROA and loop unroll. If we manage
478       // to eliminate allocas before unroll we may choose to unroll less.
479       if (EnableOpt)
480         PM.add(createAMDGPUPromoteAllocaToVector());
481   });
482 }
483 
484 //===----------------------------------------------------------------------===//
485 // R600 Target Machine (R600 -> Cayman)
486 //===----------------------------------------------------------------------===//
487 
488 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
489                                      StringRef CPU, StringRef FS,
490                                      TargetOptions Options,
491                                      Optional<Reloc::Model> RM,
492                                      Optional<CodeModel::Model> CM,
493                                      CodeGenOpt::Level OL, bool JIT)
494     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
495   setRequiresStructuredCFG(true);
496 
497   // Override the default since calls aren't supported for r600.
498   if (EnableFunctionCalls &&
499       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
500     EnableFunctionCalls = false;
501 }
502 
503 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
504   const Function &F) const {
505   StringRef GPU = getGPUName(F);
506   StringRef FS = getFeatureString(F);
507 
508   SmallString<128> SubtargetKey(GPU);
509   SubtargetKey.append(FS);
510 
511   auto &I = SubtargetMap[SubtargetKey];
512   if (!I) {
513     // This needs to be done before we create a new subtarget since any
514     // creation will depend on the TM and the code generation flags on the
515     // function that reside in TargetOptions.
516     resetTargetOptions(F);
517     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
518   }
519 
520   return I.get();
521 }
522 
523 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
524                                               unsigned DestAS) const {
525   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
526          AMDGPU::isFlatGlobalAddrSpace(DestAS);
527 }
528 
529 TargetTransformInfo
530 R600TargetMachine::getTargetTransformInfo(const Function &F) {
531   return TargetTransformInfo(R600TTIImpl(this, F));
532 }
533 
534 //===----------------------------------------------------------------------===//
535 // GCN Target Machine (SI+)
536 //===----------------------------------------------------------------------===//
537 
538 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
539                                    StringRef CPU, StringRef FS,
540                                    TargetOptions Options,
541                                    Optional<Reloc::Model> RM,
542                                    Optional<CodeModel::Model> CM,
543                                    CodeGenOpt::Level OL, bool JIT)
544     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
545 
546 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
547   StringRef GPU = getGPUName(F);
548   StringRef FS = getFeatureString(F);
549 
550   SmallString<128> SubtargetKey(GPU);
551   SubtargetKey.append(FS);
552 
553   auto &I = SubtargetMap[SubtargetKey];
554   if (!I) {
555     // This needs to be done before we create a new subtarget since any
556     // creation will depend on the TM and the code generation flags on the
557     // function that reside in TargetOptions.
558     resetTargetOptions(F);
559     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
560   }
561 
562   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
563 
564   return I.get();
565 }
566 
567 TargetTransformInfo
568 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
569   return TargetTransformInfo(GCNTTIImpl(this, F));
570 }
571 
572 //===----------------------------------------------------------------------===//
573 // AMDGPU Pass Setup
574 //===----------------------------------------------------------------------===//
575 
576 namespace {
577 
578 class AMDGPUPassConfig : public TargetPassConfig {
579 public:
580   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
581     : TargetPassConfig(TM, PM) {
582     // Exceptions and StackMaps are not supported, so these passes will never do
583     // anything.
584     disablePass(&StackMapLivenessID);
585     disablePass(&FuncletLayoutID);
586   }
587 
588   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
589     return getTM<AMDGPUTargetMachine>();
590   }
591 
592   ScheduleDAGInstrs *
593   createMachineScheduler(MachineSchedContext *C) const override {
594     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
595     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
596     return DAG;
597   }
598 
599   void addEarlyCSEOrGVNPass();
600   void addStraightLineScalarOptimizationPasses();
601   void addIRPasses() override;
602   void addCodeGenPrepare() override;
603   bool addPreISel() override;
604   bool addInstSelector() override;
605   bool addGCPasses() override;
606 
607   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
608 };
609 
610 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
611   return getStandardCSEConfigForOpt(TM->getOptLevel());
612 }
613 
614 class R600PassConfig final : public AMDGPUPassConfig {
615 public:
616   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
617     : AMDGPUPassConfig(TM, PM) {}
618 
619   ScheduleDAGInstrs *createMachineScheduler(
620     MachineSchedContext *C) const override {
621     return createR600MachineScheduler(C);
622   }
623 
624   bool addPreISel() override;
625   bool addInstSelector() override;
626   void addPreRegAlloc() override;
627   void addPreSched2() override;
628   void addPreEmitPass() override;
629 };
630 
631 class GCNPassConfig final : public AMDGPUPassConfig {
632 public:
633   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
634     : AMDGPUPassConfig(TM, PM) {
635     // It is necessary to know the register usage of the entire call graph.  We
636     // allow calls without EnableAMDGPUFunctionCalls if they are marked
637     // noinline, so this is always required.
638     setRequiresCodeGenSCCOrder(true);
639   }
640 
641   GCNTargetMachine &getGCNTargetMachine() const {
642     return getTM<GCNTargetMachine>();
643   }
644 
645   ScheduleDAGInstrs *
646   createMachineScheduler(MachineSchedContext *C) const override;
647 
648   bool addPreISel() override;
649   void addMachineSSAOptimization() override;
650   bool addILPOpts() override;
651   bool addInstSelector() override;
652   bool addIRTranslator() override;
653   void addPreLegalizeMachineIR() override;
654   bool addLegalizeMachineIR() override;
655   void addPreRegBankSelect() override;
656   bool addRegBankSelect() override;
657   bool addGlobalInstructionSelect() override;
658   void addFastRegAlloc() override;
659   void addOptimizedRegAlloc() override;
660   void addPreRegAlloc() override;
661   bool addPreRewrite() override;
662   void addPostRegAlloc() override;
663   void addPreSched2() override;
664   void addPreEmitPass() override;
665 };
666 
667 } // end anonymous namespace
668 
669 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
670   if (getOptLevel() == CodeGenOpt::Aggressive)
671     addPass(createGVNPass());
672   else
673     addPass(createEarlyCSEPass());
674 }
675 
676 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
677   addPass(createLICMPass());
678   addPass(createSeparateConstOffsetFromGEPPass());
679   addPass(createSpeculativeExecutionPass());
680   // ReassociateGEPs exposes more opportunites for SLSR. See
681   // the example in reassociate-geps-and-slsr.ll.
682   addPass(createStraightLineStrengthReducePass());
683   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
684   // EarlyCSE can reuse.
685   addEarlyCSEOrGVNPass();
686   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
687   addPass(createNaryReassociatePass());
688   // NaryReassociate on GEPs creates redundant common expressions, so run
689   // EarlyCSE after it.
690   addPass(createEarlyCSEPass());
691 }
692 
693 void AMDGPUPassConfig::addIRPasses() {
694   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
695 
696   // There is no reason to run these.
697   disablePass(&StackMapLivenessID);
698   disablePass(&FuncletLayoutID);
699   disablePass(&PatchableFunctionID);
700 
701   addPass(createAMDGPUPrintfRuntimeBinding());
702 
703   // This must occur before inlining, as the inliner will not look through
704   // bitcast calls.
705   addPass(createAMDGPUFixFunctionBitcastsPass());
706 
707   // A call to propagate attributes pass in the backend in case opt was not run.
708   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
709 
710   addPass(createAtomicExpandPass());
711 
712 
713   addPass(createAMDGPULowerIntrinsicsPass());
714 
715   // Function calls are not supported, so make sure we inline everything.
716   addPass(createAMDGPUAlwaysInlinePass());
717   addPass(createAlwaysInlinerLegacyPass());
718   // We need to add the barrier noop pass, otherwise adding the function
719   // inlining pass will cause all of the PassConfigs passes to be run
720   // one function at a time, which means if we have a nodule with two
721   // functions, then we will generate code for the first function
722   // without ever running any passes on the second.
723   addPass(createBarrierNoopPass());
724 
725   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
726   if (TM.getTargetTriple().getArch() == Triple::r600)
727     addPass(createR600OpenCLImageTypeLoweringPass());
728 
729   // Replace OpenCL enqueued block function pointers with global variables.
730   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
731 
732   if (TM.getOptLevel() > CodeGenOpt::None) {
733     addPass(createInferAddressSpacesPass());
734     addPass(createAMDGPUPromoteAlloca());
735 
736     if (EnableSROA)
737       addPass(createSROAPass());
738 
739     if (EnableScalarIRPasses)
740       addStraightLineScalarOptimizationPasses();
741 
742     if (EnableAMDGPUAliasAnalysis) {
743       addPass(createAMDGPUAAWrapperPass());
744       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
745                                              AAResults &AAR) {
746         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
747           AAR.addAAResult(WrapperPass->getResult());
748         }));
749     }
750   }
751 
752   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
753     // TODO: May want to move later or split into an early and late one.
754     addPass(createAMDGPUCodeGenPreparePass());
755   }
756 
757   TargetPassConfig::addIRPasses();
758 
759   // EarlyCSE is not always strong enough to clean up what LSR produces. For
760   // example, GVN can combine
761   //
762   //   %0 = add %a, %b
763   //   %1 = add %b, %a
764   //
765   // and
766   //
767   //   %0 = shl nsw %a, 2
768   //   %1 = shl %a, 2
769   //
770   // but EarlyCSE can do neither of them.
771   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
772     addEarlyCSEOrGVNPass();
773 }
774 
775 void AMDGPUPassConfig::addCodeGenPrepare() {
776   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
777     addPass(createAMDGPUAnnotateKernelFeaturesPass());
778 
779   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
780       EnableLowerKernelArguments)
781     addPass(createAMDGPULowerKernelArgumentsPass());
782 
783   addPass(&AMDGPUPerfHintAnalysisID);
784 
785   TargetPassConfig::addCodeGenPrepare();
786 
787   if (EnableLoadStoreVectorizer)
788     addPass(createLoadStoreVectorizerPass());
789 
790   // LowerSwitch pass may introduce unreachable blocks that can
791   // cause unexpected behavior for subsequent passes. Placing it
792   // here seems better that these blocks would get cleaned up by
793   // UnreachableBlockElim inserted next in the pass flow.
794   addPass(createLowerSwitchPass());
795 }
796 
797 bool AMDGPUPassConfig::addPreISel() {
798   addPass(createFlattenCFGPass());
799   return false;
800 }
801 
802 bool AMDGPUPassConfig::addInstSelector() {
803   // Defer the verifier until FinalizeISel.
804   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
805   return false;
806 }
807 
808 bool AMDGPUPassConfig::addGCPasses() {
809   // Do nothing. GC is not supported.
810   return false;
811 }
812 
813 //===----------------------------------------------------------------------===//
814 // R600 Pass Setup
815 //===----------------------------------------------------------------------===//
816 
817 bool R600PassConfig::addPreISel() {
818   AMDGPUPassConfig::addPreISel();
819 
820   if (EnableR600StructurizeCFG)
821     addPass(createStructurizeCFGPass());
822   return false;
823 }
824 
825 bool R600PassConfig::addInstSelector() {
826   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
827   return false;
828 }
829 
830 void R600PassConfig::addPreRegAlloc() {
831   addPass(createR600VectorRegMerger());
832 }
833 
834 void R600PassConfig::addPreSched2() {
835   addPass(createR600EmitClauseMarkers(), false);
836   if (EnableR600IfConvert)
837     addPass(&IfConverterID, false);
838   addPass(createR600ClauseMergePass(), false);
839 }
840 
841 void R600PassConfig::addPreEmitPass() {
842   addPass(createAMDGPUCFGStructurizerPass(), false);
843   addPass(createR600ExpandSpecialInstrsPass(), false);
844   addPass(&FinalizeMachineBundlesID, false);
845   addPass(createR600Packetizer(), false);
846   addPass(createR600ControlFlowFinalizer(), false);
847 }
848 
849 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
850   return new R600PassConfig(*this, PM);
851 }
852 
853 //===----------------------------------------------------------------------===//
854 // GCN Pass Setup
855 //===----------------------------------------------------------------------===//
856 
857 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
858   MachineSchedContext *C) const {
859   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
860   if (ST.enableSIScheduler())
861     return createSIMachineScheduler(C);
862   return createGCNMaxOccupancyMachineScheduler(C);
863 }
864 
865 bool GCNPassConfig::addPreISel() {
866   AMDGPUPassConfig::addPreISel();
867 
868   if (EnableAtomicOptimizations) {
869     addPass(createAMDGPUAtomicOptimizerPass());
870   }
871 
872   // FIXME: We need to run a pass to propagate the attributes when calls are
873   // supported.
874 
875   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
876   // regions formed by them.
877   addPass(&AMDGPUUnifyDivergentExitNodesID);
878   if (!LateCFGStructurize) {
879     if (EnableStructurizerWorkarounds) {
880       addPass(createFixIrreduciblePass());
881       addPass(createUnifyLoopExitsPass());
882     }
883     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
884   }
885   addPass(createSinkingPass());
886   addPass(createAMDGPUAnnotateUniformValues());
887   if (!LateCFGStructurize) {
888     addPass(createSIAnnotateControlFlowPass());
889   }
890   addPass(createLCSSAPass());
891 
892   return false;
893 }
894 
895 void GCNPassConfig::addMachineSSAOptimization() {
896   TargetPassConfig::addMachineSSAOptimization();
897 
898   // We want to fold operands after PeepholeOptimizer has run (or as part of
899   // it), because it will eliminate extra copies making it easier to fold the
900   // real source operand. We want to eliminate dead instructions after, so that
901   // we see fewer uses of the copies. We then need to clean up the dead
902   // instructions leftover after the operands are folded as well.
903   //
904   // XXX - Can we get away without running DeadMachineInstructionElim again?
905   addPass(&SIFoldOperandsID);
906   if (EnableDPPCombine)
907     addPass(&GCNDPPCombineID);
908   addPass(&DeadMachineInstructionElimID);
909   addPass(&SILoadStoreOptimizerID);
910   if (EnableSDWAPeephole) {
911     addPass(&SIPeepholeSDWAID);
912     addPass(&EarlyMachineLICMID);
913     addPass(&MachineCSEID);
914     addPass(&SIFoldOperandsID);
915     addPass(&DeadMachineInstructionElimID);
916   }
917   addPass(createSIShrinkInstructionsPass());
918 }
919 
920 bool GCNPassConfig::addILPOpts() {
921   if (EnableEarlyIfConversion)
922     addPass(&EarlyIfConverterID);
923 
924   TargetPassConfig::addILPOpts();
925   return false;
926 }
927 
928 bool GCNPassConfig::addInstSelector() {
929   AMDGPUPassConfig::addInstSelector();
930   addPass(&SIFixSGPRCopiesID);
931   addPass(createSILowerI1CopiesPass());
932   addPass(createSIAddIMGInitPass());
933   return false;
934 }
935 
936 bool GCNPassConfig::addIRTranslator() {
937   addPass(new IRTranslator(getOptLevel()));
938   return false;
939 }
940 
941 void GCNPassConfig::addPreLegalizeMachineIR() {
942   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
943   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
944   addPass(new Localizer());
945 }
946 
947 bool GCNPassConfig::addLegalizeMachineIR() {
948   addPass(new Legalizer());
949   return false;
950 }
951 
952 void GCNPassConfig::addPreRegBankSelect() {
953   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
954   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
955 }
956 
957 bool GCNPassConfig::addRegBankSelect() {
958   addPass(new RegBankSelect());
959   return false;
960 }
961 
962 bool GCNPassConfig::addGlobalInstructionSelect() {
963   addPass(new InstructionSelect());
964   return false;
965 }
966 
967 void GCNPassConfig::addPreRegAlloc() {
968   if (LateCFGStructurize) {
969     addPass(createAMDGPUMachineCFGStructurizerPass());
970   }
971   addPass(createSIWholeQuadModePass());
972 }
973 
974 void GCNPassConfig::addFastRegAlloc() {
975   // FIXME: We have to disable the verifier here because of PHIElimination +
976   // TwoAddressInstructions disabling it.
977 
978   // This must be run immediately after phi elimination and before
979   // TwoAddressInstructions, otherwise the processing of the tied operand of
980   // SI_ELSE will introduce a copy of the tied operand source after the else.
981   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
982 
983   // This must be run just after RegisterCoalescing.
984   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
985 
986   TargetPassConfig::addFastRegAlloc();
987 }
988 
989 void GCNPassConfig::addOptimizedRegAlloc() {
990   if (OptExecMaskPreRA)
991     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
992   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
993 
994   // This must be run immediately after phi elimination and before
995   // TwoAddressInstructions, otherwise the processing of the tied operand of
996   // SI_ELSE will introduce a copy of the tied operand source after the else.
997   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
998 
999   // This must be run just after RegisterCoalescing.
1000   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
1001 
1002   if (EnableDCEInRA)
1003     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1004 
1005   TargetPassConfig::addOptimizedRegAlloc();
1006 }
1007 
1008 bool GCNPassConfig::addPreRewrite() {
1009   if (EnableRegReassign) {
1010     addPass(&GCNNSAReassignID);
1011     addPass(&GCNRegBankReassignID);
1012   }
1013   return true;
1014 }
1015 
1016 void GCNPassConfig::addPostRegAlloc() {
1017   addPass(&SIFixVGPRCopiesID);
1018   if (getOptLevel() > CodeGenOpt::None)
1019     addPass(&SIOptimizeExecMaskingID);
1020   TargetPassConfig::addPostRegAlloc();
1021 
1022   // Equivalent of PEI for SGPRs.
1023   addPass(&SILowerSGPRSpillsID);
1024 }
1025 
1026 void GCNPassConfig::addPreSched2() {
1027   addPass(&SIPostRABundlerID);
1028 }
1029 
1030 void GCNPassConfig::addPreEmitPass() {
1031   addPass(createSIMemoryLegalizerPass());
1032   addPass(createSIInsertWaitcntsPass());
1033   addPass(createSIShrinkInstructionsPass());
1034   addPass(createSIModeRegisterPass());
1035 
1036   // The hazard recognizer that runs as part of the post-ra scheduler does not
1037   // guarantee to be able handle all hazards correctly. This is because if there
1038   // are multiple scheduling regions in a basic block, the regions are scheduled
1039   // bottom up, so when we begin to schedule a region we don't know what
1040   // instructions were emitted directly before it.
1041   //
1042   // Here we add a stand-alone hazard recognizer pass which can handle all
1043   // cases.
1044   //
1045   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
1046   // be better for it to emit S_NOP <N> when possible.
1047   addPass(&PostRAHazardRecognizerID);
1048   if (getOptLevel() > CodeGenOpt::None)
1049     addPass(&SIInsertHardClausesID);
1050 
1051   addPass(&SIRemoveShortExecBranchesID);
1052   addPass(&SIInsertSkipsPassID);
1053   addPass(&SIPreEmitPeepholeID);
1054   addPass(&BranchRelaxationPassID);
1055 }
1056 
1057 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1058   return new GCNPassConfig(*this, PM);
1059 }
1060 
1061 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1062   return new yaml::SIMachineFunctionInfo();
1063 }
1064 
1065 yaml::MachineFunctionInfo *
1066 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1067   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1068   return new yaml::SIMachineFunctionInfo(*MFI,
1069                                          *MF.getSubtarget().getRegisterInfo());
1070 }
1071 
1072 bool GCNTargetMachine::parseMachineFunctionInfo(
1073     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1074     SMDiagnostic &Error, SMRange &SourceRange) const {
1075   const yaml::SIMachineFunctionInfo &YamlMFI =
1076       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1077   MachineFunction &MF = PFS.MF;
1078   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1079 
1080   MFI->initializeBaseYamlFields(YamlMFI);
1081 
1082   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1083     Register TempReg;
1084     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1085       SourceRange = RegName.SourceRange;
1086       return true;
1087     }
1088     RegVal = TempReg;
1089 
1090     return false;
1091   };
1092 
1093   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1094     // Create a diagnostic for a the register string literal.
1095     const MemoryBuffer &Buffer =
1096         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1097     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1098                          RegName.Value.size(), SourceMgr::DK_Error,
1099                          "incorrect register class for field", RegName.Value,
1100                          None, None);
1101     SourceRange = RegName.SourceRange;
1102     return true;
1103   };
1104 
1105   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1106       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1107       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1108     return true;
1109 
1110   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1111       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1112     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1113   }
1114 
1115   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1116       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1117     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1118   }
1119 
1120   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1121       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1122     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1123   }
1124 
1125   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1126                                    const TargetRegisterClass &RC,
1127                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1128                                    unsigned SystemSGPRs) {
1129     // Skip parsing if it's not present.
1130     if (!A)
1131       return false;
1132 
1133     if (A->IsRegister) {
1134       Register Reg;
1135       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1136         SourceRange = A->RegisterName.SourceRange;
1137         return true;
1138       }
1139       if (!RC.contains(Reg))
1140         return diagnoseRegisterClass(A->RegisterName);
1141       Arg = ArgDescriptor::createRegister(Reg);
1142     } else
1143       Arg = ArgDescriptor::createStack(A->StackOffset);
1144     // Check and apply the optional mask.
1145     if (A->Mask)
1146       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1147 
1148     MFI->NumUserSGPRs += UserSGPRs;
1149     MFI->NumSystemSGPRs += SystemSGPRs;
1150     return false;
1151   };
1152 
1153   if (YamlMFI.ArgInfo &&
1154       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1155                              AMDGPU::SGPR_128RegClass,
1156                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1157        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1158                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1159                              2, 0) ||
1160        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1161                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1162        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1163                              AMDGPU::SReg_64RegClass,
1164                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1165        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1166                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1167                              2, 0) ||
1168        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1169                              AMDGPU::SReg_64RegClass,
1170                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1171        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1172                              AMDGPU::SGPR_32RegClass,
1173                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1174        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1175                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1176                              0, 1) ||
1177        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1178                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1179                              0, 1) ||
1180        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1181                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1182                              0, 1) ||
1183        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1184                              AMDGPU::SGPR_32RegClass,
1185                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1186        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1187                              AMDGPU::SGPR_32RegClass,
1188                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1189        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1190                              AMDGPU::SReg_64RegClass,
1191                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1192        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1193                              AMDGPU::SReg_64RegClass,
1194                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1195        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1196                              AMDGPU::VGPR_32RegClass,
1197                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1198        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1199                              AMDGPU::VGPR_32RegClass,
1200                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1201        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1202                              AMDGPU::VGPR_32RegClass,
1203                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1204     return true;
1205 
1206   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1207   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1208   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1209   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1210   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1211   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1212 
1213   return false;
1214 }
1215