1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600MachineScheduler.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIMachineScheduler.h"
27 #include "TargetInfo/AMDGPUTargetInfo.h"
28 #include "llvm/Analysis/CGSCCPassManager.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/Localizer.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MIRParser/MIParser.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/LegacyPassManager.h"
37 #include "llvm/IR/PassManager.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/Passes/PassBuilder.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Transforms/IPO.h"
42 #include "llvm/Transforms/IPO/AlwaysInliner.h"
43 #include "llvm/Transforms/IPO/GlobalDCE.h"
44 #include "llvm/Transforms/IPO/Internalize.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
49 #include "llvm/Transforms/Utils.h"
50 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
51 #include "llvm/Transforms/Vectorize.h"
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73             cl::desc("Run pre-RA exec mask optimizations"),
74             cl::init(true));
75 
76 static cl::opt<bool> EnableR600IfConvert(
77   "r600-if-convert",
78   cl::desc("Use if conversion pass"),
79   cl::ReallyHidden,
80   cl::init(true));
81 
82 // Option to disable vectorizer for tests.
83 static cl::opt<bool> EnableLoadStoreVectorizer(
84   "amdgpu-load-store-vectorizer",
85   cl::desc("Enable load store vectorizer"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to control global loads scalarization
90 static cl::opt<bool> ScalarizeGlobal(
91   "amdgpu-scalarize-global-loads",
92   cl::desc("Enable global load scalarization"),
93   cl::init(true),
94   cl::Hidden);
95 
96 // Option to run internalize pass.
97 static cl::opt<bool> InternalizeSymbols(
98   "amdgpu-internalize-symbols",
99   cl::desc("Enable elimination of non-kernel functions and unused globals"),
100   cl::init(false),
101   cl::Hidden);
102 
103 // Option to inline all early.
104 static cl::opt<bool> EarlyInlineAll(
105   "amdgpu-early-inline-all",
106   cl::desc("Inline all functions early"),
107   cl::init(false),
108   cl::Hidden);
109 
110 static cl::opt<bool> EnableSDWAPeephole(
111   "amdgpu-sdwa-peephole",
112   cl::desc("Enable SDWA peepholer"),
113   cl::init(true));
114 
115 static cl::opt<bool> EnableDPPCombine(
116   "amdgpu-dpp-combine",
117   cl::desc("Enable DPP combiner"),
118   cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122   cl::desc("Enable AMDGPU Alias Analysis"),
123   cl::init(true));
124 
125 // Option to run late CFG structurizer
126 static cl::opt<bool, true> LateCFGStructurize(
127   "amdgpu-late-structurize",
128   cl::desc("Enable late CFG structurization"),
129   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
130   cl::Hidden);
131 
132 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
133   "amdgpu-function-calls",
134   cl::desc("Enable AMDGPU function call support"),
135   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
136   cl::init(true),
137   cl::Hidden);
138 
139 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
140   "amdgpu-fixed-function-abi",
141   cl::desc("Enable all implicit function arguments"),
142   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
143   cl::init(false),
144   cl::Hidden);
145 
146 // Enable lib calls simplifications
147 static cl::opt<bool> EnableLibCallSimplify(
148   "amdgpu-simplify-libcall",
149   cl::desc("Enable amdgpu library simplifications"),
150   cl::init(true),
151   cl::Hidden);
152 
153 static cl::opt<bool> EnableLowerKernelArguments(
154   "amdgpu-ir-lower-kernel-arguments",
155   cl::desc("Lower kernel argument loads in IR pass"),
156   cl::init(true),
157   cl::Hidden);
158 
159 static cl::opt<bool> EnableRegReassign(
160   "amdgpu-reassign-regs",
161   cl::desc("Enable register reassign optimizations on gfx10+"),
162   cl::init(true),
163   cl::Hidden);
164 
165 // Enable atomic optimization
166 static cl::opt<bool> EnableAtomicOptimizations(
167   "amdgpu-atomic-optimizations",
168   cl::desc("Enable atomic optimizations"),
169   cl::init(false),
170   cl::Hidden);
171 
172 // Enable Mode register optimization
173 static cl::opt<bool> EnableSIModeRegisterPass(
174   "amdgpu-mode-register",
175   cl::desc("Enable mode register pass"),
176   cl::init(true),
177   cl::Hidden);
178 
179 // Option is used in lit tests to prevent deadcoding of patterns inspected.
180 static cl::opt<bool>
181 EnableDCEInRA("amdgpu-dce-in-ra",
182     cl::init(true), cl::Hidden,
183     cl::desc("Enable machine DCE inside regalloc"));
184 
185 static cl::opt<bool> EnableScalarIRPasses(
186   "amdgpu-scalar-ir-passes",
187   cl::desc("Enable scalar IR passes"),
188   cl::init(true),
189   cl::Hidden);
190 
191 static cl::opt<bool> EnableStructurizerWorkarounds(
192     "amdgpu-enable-structurizer-workarounds",
193     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
194     cl::Hidden);
195 
196 static cl::opt<bool>
197     DisableLowerModuleLDS("amdgpu-disable-lower-module-lds", cl::Hidden,
198                           cl::desc("Disable lower module lds pass"),
199                           cl::init(false));
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFoldOperandsPass(*PR);
220   initializeSIPeepholeSDWAPass(*PR);
221   initializeSIShrinkInstructionsPass(*PR);
222   initializeSIOptimizeExecMaskingPreRAPass(*PR);
223   initializeSILoadStoreOptimizerPass(*PR);
224   initializeAMDGPUFixFunctionBitcastsPass(*PR);
225   initializeAMDGPUAlwaysInlinePass(*PR);
226   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
227   initializeAMDGPUAnnotateUniformValuesPass(*PR);
228   initializeAMDGPUArgumentUsageInfoPass(*PR);
229   initializeAMDGPUAtomicOptimizerPass(*PR);
230   initializeAMDGPULowerKernelArgumentsPass(*PR);
231   initializeAMDGPULowerKernelAttributesPass(*PR);
232   initializeAMDGPULowerIntrinsicsPass(*PR);
233   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
234   initializeAMDGPUPostLegalizerCombinerPass(*PR);
235   initializeAMDGPUPreLegalizerCombinerPass(*PR);
236   initializeAMDGPURegBankCombinerPass(*PR);
237   initializeAMDGPUPromoteAllocaPass(*PR);
238   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
239   initializeAMDGPUCodeGenPreparePass(*PR);
240   initializeAMDGPULateCodeGenPreparePass(*PR);
241   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
242   initializeAMDGPUPropagateAttributesLatePass(*PR);
243   initializeAMDGPULowerModuleLDSPass(*PR);
244   initializeAMDGPURewriteOutArgumentsPass(*PR);
245   initializeAMDGPUUnifyMetadataPass(*PR);
246   initializeSIAnnotateControlFlowPass(*PR);
247   initializeSIInsertHardClausesPass(*PR);
248   initializeSIInsertWaitcntsPass(*PR);
249   initializeSIModeRegisterPass(*PR);
250   initializeSIWholeQuadModePass(*PR);
251   initializeSILowerControlFlowPass(*PR);
252   initializeSIPreEmitPeepholePass(*PR);
253   initializeSILateBranchLoweringPass(*PR);
254   initializeSIMemoryLegalizerPass(*PR);
255   initializeSIOptimizeExecMaskingPass(*PR);
256   initializeSIPreAllocateWWMRegsPass(*PR);
257   initializeSIFormMemoryClausesPass(*PR);
258   initializeSIPostRABundlerPass(*PR);
259   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
260   initializeAMDGPUAAWrapperPassPass(*PR);
261   initializeAMDGPUExternalAAWrapperPass(*PR);
262   initializeAMDGPUUseNativeCallsPass(*PR);
263   initializeAMDGPUSimplifyLibCallsPass(*PR);
264   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
265   initializeGCNRegBankReassignPass(*PR);
266   initializeGCNNSAReassignPass(*PR);
267   initializeSIAddIMGInitPass(*PR);
268 }
269 
270 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
271   return std::make_unique<AMDGPUTargetObjectFile>();
272 }
273 
274 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
275   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
276 }
277 
278 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
279   return new SIScheduleDAGMI(C);
280 }
281 
282 static ScheduleDAGInstrs *
283 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
284   ScheduleDAGMILive *DAG =
285     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
286   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
287   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
288   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
289   return DAG;
290 }
291 
292 static ScheduleDAGInstrs *
293 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
294   auto DAG = new GCNIterativeScheduler(C,
295     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
296   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
297   return DAG;
298 }
299 
300 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
301   return new GCNIterativeScheduler(C,
302     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
303 }
304 
305 static ScheduleDAGInstrs *
306 createIterativeILPMachineScheduler(MachineSchedContext *C) {
307   auto DAG = new GCNIterativeScheduler(C,
308     GCNIterativeScheduler::SCHEDULE_ILP);
309   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
310   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
311   return DAG;
312 }
313 
314 static MachineSchedRegistry
315 R600SchedRegistry("r600", "Run R600's custom scheduler",
316                    createR600MachineScheduler);
317 
318 static MachineSchedRegistry
319 SISchedRegistry("si", "Run SI's custom scheduler",
320                 createSIMachineScheduler);
321 
322 static MachineSchedRegistry
323 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
324                              "Run GCN scheduler to maximize occupancy",
325                              createGCNMaxOccupancyMachineScheduler);
326 
327 static MachineSchedRegistry
328 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
329   "Run GCN scheduler to maximize occupancy (experimental)",
330   createIterativeGCNMaxOccupancyMachineScheduler);
331 
332 static MachineSchedRegistry
333 GCNMinRegSchedRegistry("gcn-minreg",
334   "Run GCN iterative scheduler for minimal register usage (experimental)",
335   createMinRegScheduler);
336 
337 static MachineSchedRegistry
338 GCNILPSchedRegistry("gcn-ilp",
339   "Run GCN iterative scheduler for ILP scheduling (experimental)",
340   createIterativeILPMachineScheduler);
341 
342 static StringRef computeDataLayout(const Triple &TT) {
343   if (TT.getArch() == Triple::r600) {
344     // 32-bit pointers.
345     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
346            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
347   }
348 
349   // 32-bit private, local, and region pointers. 64-bit global, constant and
350   // flat, non-integral buffer fat pointers.
351   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
352          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
353          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
354          "-ni:7";
355 }
356 
357 LLVM_READNONE
358 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
359   if (!GPU.empty())
360     return GPU;
361 
362   // Need to default to a target with flat support for HSA.
363   if (TT.getArch() == Triple::amdgcn)
364     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
365 
366   return "r600";
367 }
368 
369 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
370   // The AMDGPU toolchain only supports generating shared objects, so we
371   // must always use PIC.
372   return Reloc::PIC_;
373 }
374 
375 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
376                                          StringRef CPU, StringRef FS,
377                                          TargetOptions Options,
378                                          Optional<Reloc::Model> RM,
379                                          Optional<CodeModel::Model> CM,
380                                          CodeGenOpt::Level OptLevel)
381     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
382                         FS, Options, getEffectiveRelocModel(RM),
383                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
384       TLOF(createTLOF(getTargetTriple())) {
385   initAsmInfo();
386   if (TT.getArch() == Triple::amdgcn) {
387     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
388       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
389     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
390       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
391   }
392   // Set -fixed-function-abi to true if not provided..
393   if (TT.getOS() == Triple::AMDHSA &&
394       EnableAMDGPUFixedFunctionABIOpt.getNumOccurrences() == 0)
395     EnableFixedFunctionABI = true;
396 }
397 
398 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
399 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
400 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
401 
402 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
403 
404 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
405   Attribute GPUAttr = F.getFnAttribute("target-cpu");
406   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
407 }
408 
409 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
410   Attribute FSAttr = F.getFnAttribute("target-features");
411 
412   return FSAttr.isValid() ? FSAttr.getValueAsString()
413                           : getTargetFeatureString();
414 }
415 
416 /// Predicate for Internalize pass.
417 static bool mustPreserveGV(const GlobalValue &GV) {
418   if (const Function *F = dyn_cast<Function>(&GV))
419     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
420 
421   return !GV.use_empty();
422 }
423 
424 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
425   Builder.DivergentTarget = true;
426 
427   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
428   bool Internalize = InternalizeSymbols;
429   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
430   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
431   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
432 
433   if (EnableFunctionCalls) {
434     delete Builder.Inliner;
435     Builder.Inliner = createFunctionInliningPass();
436   }
437 
438   Builder.addExtension(
439     PassManagerBuilder::EP_ModuleOptimizerEarly,
440     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
441                                                legacy::PassManagerBase &PM) {
442       if (AMDGPUAA) {
443         PM.add(createAMDGPUAAWrapperPass());
444         PM.add(createAMDGPUExternalAAWrapperPass());
445       }
446       PM.add(createAMDGPUUnifyMetadataPass());
447       PM.add(createAMDGPUPrintfRuntimeBinding());
448       if (Internalize)
449         PM.add(createInternalizePass(mustPreserveGV));
450       PM.add(createAMDGPUPropagateAttributesLatePass(this));
451       if (Internalize)
452         PM.add(createGlobalDCEPass());
453       if (EarlyInline)
454         PM.add(createAMDGPUAlwaysInlinePass(false));
455   });
456 
457   Builder.addExtension(
458     PassManagerBuilder::EP_EarlyAsPossible,
459     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
460                                       legacy::PassManagerBase &PM) {
461       if (AMDGPUAA) {
462         PM.add(createAMDGPUAAWrapperPass());
463         PM.add(createAMDGPUExternalAAWrapperPass());
464       }
465       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
466       PM.add(llvm::createAMDGPUUseNativeCallsPass());
467       if (LibCallSimplify)
468         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
469   });
470 
471   Builder.addExtension(
472     PassManagerBuilder::EP_CGSCCOptimizerLate,
473     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
474       // Add infer address spaces pass to the opt pipeline after inlining
475       // but before SROA to increase SROA opportunities.
476       PM.add(createInferAddressSpacesPass());
477 
478       // This should run after inlining to have any chance of doing anything,
479       // and before other cleanup optimizations.
480       PM.add(createAMDGPULowerKernelAttributesPass());
481 
482       // Promote alloca to vector before SROA and loop unroll. If we manage
483       // to eliminate allocas before unroll we may choose to unroll less.
484       if (EnableOpt)
485         PM.add(createAMDGPUPromoteAllocaToVector());
486   });
487 }
488 
489 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
490   AAM.registerFunctionAnalysis<AMDGPUAA>();
491 }
492 
493 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
494                                                        bool DebugPassManager) {
495   PB.registerPipelineParsingCallback(
496       [this](StringRef PassName, ModulePassManager &PM,
497              ArrayRef<PassBuilder::PipelineElement>) {
498         if (PassName == "amdgpu-propagate-attributes-late") {
499           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
500           return true;
501         }
502         if (PassName == "amdgpu-unify-metadata") {
503           PM.addPass(AMDGPUUnifyMetadataPass());
504           return true;
505         }
506         if (PassName == "amdgpu-printf-runtime-binding") {
507           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
508           return true;
509         }
510         if (PassName == "amdgpu-always-inline") {
511           PM.addPass(AMDGPUAlwaysInlinePass());
512           return true;
513         }
514         if (PassName == "amdgpu-lower-module-lds") {
515           PM.addPass(AMDGPULowerModuleLDSPass());
516           return true;
517         }
518         return false;
519       });
520   PB.registerPipelineParsingCallback(
521       [this](StringRef PassName, FunctionPassManager &PM,
522              ArrayRef<PassBuilder::PipelineElement>) {
523         if (PassName == "amdgpu-simplifylib") {
524           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
525           return true;
526         }
527         if (PassName == "amdgpu-usenative") {
528           PM.addPass(AMDGPUUseNativeCallsPass());
529           return true;
530         }
531         if (PassName == "amdgpu-promote-alloca") {
532           PM.addPass(AMDGPUPromoteAllocaPass(*this));
533           return true;
534         }
535         if (PassName == "amdgpu-promote-alloca-to-vector") {
536           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
537           return true;
538         }
539         if (PassName == "amdgpu-lower-kernel-attributes") {
540           PM.addPass(AMDGPULowerKernelAttributesPass());
541           return true;
542         }
543         if (PassName == "amdgpu-propagate-attributes-early") {
544           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
545           return true;
546         }
547         return false;
548       });
549 
550   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
551     FAM.registerPass([&] { return AMDGPUAA(); });
552   });
553 
554   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
555     if (AAName == "amdgpu-aa") {
556       AAM.registerFunctionAnalysis<AMDGPUAA>();
557       return true;
558     }
559     return false;
560   });
561 
562   PB.registerPipelineStartEPCallback([this, DebugPassManager](
563                                          ModulePassManager &PM,
564                                          PassBuilder::OptimizationLevel Level) {
565     FunctionPassManager FPM(DebugPassManager);
566     FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
567     FPM.addPass(AMDGPUUseNativeCallsPass());
568     if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
569       FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
570     PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
571   });
572 
573   PB.registerPipelineEarlySimplificationEPCallback(
574       [this](ModulePassManager &PM, PassBuilder::OptimizationLevel Level) {
575         if (Level == PassBuilder::OptimizationLevel::O0)
576           return;
577 
578         PM.addPass(AMDGPUUnifyMetadataPass());
579         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
580 
581         if (InternalizeSymbols) {
582           PM.addPass(InternalizePass(mustPreserveGV));
583         }
584         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
585         if (InternalizeSymbols) {
586           PM.addPass(GlobalDCEPass());
587         }
588         if (EarlyInlineAll && !EnableFunctionCalls)
589           PM.addPass(AMDGPUAlwaysInlinePass());
590       });
591 
592   PB.registerCGSCCOptimizerLateEPCallback(
593       [this, DebugPassManager](CGSCCPassManager &PM,
594                                PassBuilder::OptimizationLevel Level) {
595         if (Level == PassBuilder::OptimizationLevel::O0)
596           return;
597 
598         FunctionPassManager FPM(DebugPassManager);
599 
600         // Add infer address spaces pass to the opt pipeline after inlining
601         // but before SROA to increase SROA opportunities.
602         FPM.addPass(InferAddressSpacesPass());
603 
604         // This should run after inlining to have any chance of doing
605         // anything, and before other cleanup optimizations.
606         FPM.addPass(AMDGPULowerKernelAttributesPass());
607 
608         if (Level != PassBuilder::OptimizationLevel::O0) {
609           // Promote alloca to vector before SROA and loop unroll. If we
610           // manage to eliminate allocas before unroll we may choose to unroll
611           // less.
612           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
613         }
614 
615         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
616       });
617 }
618 
619 //===----------------------------------------------------------------------===//
620 // R600 Target Machine (R600 -> Cayman)
621 //===----------------------------------------------------------------------===//
622 
623 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
624                                      StringRef CPU, StringRef FS,
625                                      TargetOptions Options,
626                                      Optional<Reloc::Model> RM,
627                                      Optional<CodeModel::Model> CM,
628                                      CodeGenOpt::Level OL, bool JIT)
629     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
630   setRequiresStructuredCFG(true);
631 
632   // Override the default since calls aren't supported for r600.
633   if (EnableFunctionCalls &&
634       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
635     EnableFunctionCalls = false;
636 }
637 
638 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
639   const Function &F) const {
640   StringRef GPU = getGPUName(F);
641   StringRef FS = getFeatureString(F);
642 
643   SmallString<128> SubtargetKey(GPU);
644   SubtargetKey.append(FS);
645 
646   auto &I = SubtargetMap[SubtargetKey];
647   if (!I) {
648     // This needs to be done before we create a new subtarget since any
649     // creation will depend on the TM and the code generation flags on the
650     // function that reside in TargetOptions.
651     resetTargetOptions(F);
652     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
653   }
654 
655   return I.get();
656 }
657 
658 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
659   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
660           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
661           AddrSpace == AMDGPUAS::REGION_ADDRESS)
662              ? -1
663              : 0;
664 }
665 
666 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
667                                               unsigned DestAS) const {
668   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
669          AMDGPU::isFlatGlobalAddrSpace(DestAS);
670 }
671 
672 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
673   const auto *LD = dyn_cast<LoadInst>(V);
674   if (!LD)
675     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
676 
677   // It must be a generic pointer loaded.
678   assert(V->getType()->isPointerTy() &&
679          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
680 
681   const auto *Ptr = LD->getPointerOperand();
682   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
683     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
684   // For a generic pointer loaded from the constant memory, it could be assumed
685   // as a global pointer since the constant memory is only populated on the
686   // host side. As implied by the offload programming model, only global
687   // pointers could be referenced on the host side.
688   return AMDGPUAS::GLOBAL_ADDRESS;
689 }
690 
691 TargetTransformInfo
692 R600TargetMachine::getTargetTransformInfo(const Function &F) {
693   return TargetTransformInfo(R600TTIImpl(this, F));
694 }
695 
696 //===----------------------------------------------------------------------===//
697 // GCN Target Machine (SI+)
698 //===----------------------------------------------------------------------===//
699 
700 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
701                                    StringRef CPU, StringRef FS,
702                                    TargetOptions Options,
703                                    Optional<Reloc::Model> RM,
704                                    Optional<CodeModel::Model> CM,
705                                    CodeGenOpt::Level OL, bool JIT)
706     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
707 
708 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
709   StringRef GPU = getGPUName(F);
710   StringRef FS = getFeatureString(F);
711 
712   SmallString<128> SubtargetKey(GPU);
713   SubtargetKey.append(FS);
714 
715   auto &I = SubtargetMap[SubtargetKey];
716   if (!I) {
717     // This needs to be done before we create a new subtarget since any
718     // creation will depend on the TM and the code generation flags on the
719     // function that reside in TargetOptions.
720     resetTargetOptions(F);
721     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
722   }
723 
724   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
725 
726   return I.get();
727 }
728 
729 TargetTransformInfo
730 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
731   return TargetTransformInfo(GCNTTIImpl(this, F));
732 }
733 
734 //===----------------------------------------------------------------------===//
735 // AMDGPU Pass Setup
736 //===----------------------------------------------------------------------===//
737 
738 namespace {
739 
740 class AMDGPUPassConfig : public TargetPassConfig {
741 public:
742   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
743     : TargetPassConfig(TM, PM) {
744     // Exceptions and StackMaps are not supported, so these passes will never do
745     // anything.
746     disablePass(&StackMapLivenessID);
747     disablePass(&FuncletLayoutID);
748   }
749 
750   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
751     return getTM<AMDGPUTargetMachine>();
752   }
753 
754   ScheduleDAGInstrs *
755   createMachineScheduler(MachineSchedContext *C) const override {
756     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
757     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
758     return DAG;
759   }
760 
761   void addEarlyCSEOrGVNPass();
762   void addStraightLineScalarOptimizationPasses();
763   void addIRPasses() override;
764   void addCodeGenPrepare() override;
765   bool addPreISel() override;
766   bool addInstSelector() override;
767   bool addGCPasses() override;
768 
769   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
770 };
771 
772 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
773   return getStandardCSEConfigForOpt(TM->getOptLevel());
774 }
775 
776 class R600PassConfig final : public AMDGPUPassConfig {
777 public:
778   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
779     : AMDGPUPassConfig(TM, PM) {}
780 
781   ScheduleDAGInstrs *createMachineScheduler(
782     MachineSchedContext *C) const override {
783     return createR600MachineScheduler(C);
784   }
785 
786   bool addPreISel() override;
787   bool addInstSelector() override;
788   void addPreRegAlloc() override;
789   void addPreSched2() override;
790   void addPreEmitPass() override;
791 };
792 
793 class GCNPassConfig final : public AMDGPUPassConfig {
794 public:
795   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
796     : AMDGPUPassConfig(TM, PM) {
797     // It is necessary to know the register usage of the entire call graph.  We
798     // allow calls without EnableAMDGPUFunctionCalls if they are marked
799     // noinline, so this is always required.
800     setRequiresCodeGenSCCOrder(true);
801   }
802 
803   GCNTargetMachine &getGCNTargetMachine() const {
804     return getTM<GCNTargetMachine>();
805   }
806 
807   ScheduleDAGInstrs *
808   createMachineScheduler(MachineSchedContext *C) const override;
809 
810   bool addPreISel() override;
811   void addMachineSSAOptimization() override;
812   bool addILPOpts() override;
813   bool addInstSelector() override;
814   bool addIRTranslator() override;
815   void addPreLegalizeMachineIR() override;
816   bool addLegalizeMachineIR() override;
817   void addPreRegBankSelect() override;
818   bool addRegBankSelect() override;
819   void addPreGlobalInstructionSelect() override;
820   bool addGlobalInstructionSelect() override;
821   void addFastRegAlloc() override;
822   void addOptimizedRegAlloc() override;
823   void addPreRegAlloc() override;
824   bool addPreRewrite() override;
825   void addPostRegAlloc() override;
826   void addPreSched2() override;
827   void addPreEmitPass() override;
828 };
829 
830 } // end anonymous namespace
831 
832 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
833   if (getOptLevel() == CodeGenOpt::Aggressive)
834     addPass(createGVNPass());
835   else
836     addPass(createEarlyCSEPass());
837 }
838 
839 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
840   addPass(createLICMPass());
841   addPass(createSeparateConstOffsetFromGEPPass());
842   addPass(createSpeculativeExecutionPass());
843   // ReassociateGEPs exposes more opportunites for SLSR. See
844   // the example in reassociate-geps-and-slsr.ll.
845   addPass(createStraightLineStrengthReducePass());
846   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
847   // EarlyCSE can reuse.
848   addEarlyCSEOrGVNPass();
849   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
850   addPass(createNaryReassociatePass());
851   // NaryReassociate on GEPs creates redundant common expressions, so run
852   // EarlyCSE after it.
853   addPass(createEarlyCSEPass());
854 }
855 
856 void AMDGPUPassConfig::addIRPasses() {
857   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
858 
859   // There is no reason to run these.
860   disablePass(&StackMapLivenessID);
861   disablePass(&FuncletLayoutID);
862   disablePass(&PatchableFunctionID);
863 
864   addPass(createAMDGPUPrintfRuntimeBinding());
865 
866   // This must occur before inlining, as the inliner will not look through
867   // bitcast calls.
868   addPass(createAMDGPUFixFunctionBitcastsPass());
869 
870   // A call to propagate attributes pass in the backend in case opt was not run.
871   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
872 
873   addPass(createAtomicExpandPass());
874 
875 
876   addPass(createAMDGPULowerIntrinsicsPass());
877 
878   // Function calls are not supported, so make sure we inline everything.
879   addPass(createAMDGPUAlwaysInlinePass());
880   addPass(createAlwaysInlinerLegacyPass());
881   // We need to add the barrier noop pass, otherwise adding the function
882   // inlining pass will cause all of the PassConfigs passes to be run
883   // one function at a time, which means if we have a nodule with two
884   // functions, then we will generate code for the first function
885   // without ever running any passes on the second.
886   addPass(createBarrierNoopPass());
887 
888   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
889   if (TM.getTargetTriple().getArch() == Triple::r600)
890     addPass(createR600OpenCLImageTypeLoweringPass());
891 
892   // Replace OpenCL enqueued block function pointers with global variables.
893   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
894 
895   // Can increase LDS used by kernel so runs before PromoteAlloca
896   if (!DisableLowerModuleLDS)
897     addPass(createAMDGPULowerModuleLDSPass());
898 
899   if (TM.getOptLevel() > CodeGenOpt::None) {
900     addPass(createInferAddressSpacesPass());
901     addPass(createAMDGPUPromoteAlloca());
902 
903     if (EnableSROA)
904       addPass(createSROAPass());
905 
906     if (EnableScalarIRPasses)
907       addStraightLineScalarOptimizationPasses();
908 
909     if (EnableAMDGPUAliasAnalysis) {
910       addPass(createAMDGPUAAWrapperPass());
911       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
912                                              AAResults &AAR) {
913         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
914           AAR.addAAResult(WrapperPass->getResult());
915         }));
916     }
917   }
918 
919   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
920     // TODO: May want to move later or split into an early and late one.
921     addPass(createAMDGPUCodeGenPreparePass());
922   }
923 
924   TargetPassConfig::addIRPasses();
925 
926   // EarlyCSE is not always strong enough to clean up what LSR produces. For
927   // example, GVN can combine
928   //
929   //   %0 = add %a, %b
930   //   %1 = add %b, %a
931   //
932   // and
933   //
934   //   %0 = shl nsw %a, 2
935   //   %1 = shl %a, 2
936   //
937   // but EarlyCSE can do neither of them.
938   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
939     addEarlyCSEOrGVNPass();
940 }
941 
942 void AMDGPUPassConfig::addCodeGenPrepare() {
943   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
944     addPass(createAMDGPUAnnotateKernelFeaturesPass());
945 
946   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
947       EnableLowerKernelArguments)
948     addPass(createAMDGPULowerKernelArgumentsPass());
949 
950   addPass(&AMDGPUPerfHintAnalysisID);
951 
952   TargetPassConfig::addCodeGenPrepare();
953 
954   if (EnableLoadStoreVectorizer)
955     addPass(createLoadStoreVectorizerPass());
956 
957   // LowerSwitch pass may introduce unreachable blocks that can
958   // cause unexpected behavior for subsequent passes. Placing it
959   // here seems better that these blocks would get cleaned up by
960   // UnreachableBlockElim inserted next in the pass flow.
961   addPass(createLowerSwitchPass());
962 }
963 
964 bool AMDGPUPassConfig::addPreISel() {
965   addPass(createFlattenCFGPass());
966   return false;
967 }
968 
969 bool AMDGPUPassConfig::addInstSelector() {
970   // Defer the verifier until FinalizeISel.
971   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
972   return false;
973 }
974 
975 bool AMDGPUPassConfig::addGCPasses() {
976   // Do nothing. GC is not supported.
977   return false;
978 }
979 
980 //===----------------------------------------------------------------------===//
981 // R600 Pass Setup
982 //===----------------------------------------------------------------------===//
983 
984 bool R600PassConfig::addPreISel() {
985   AMDGPUPassConfig::addPreISel();
986 
987   if (EnableR600StructurizeCFG)
988     addPass(createStructurizeCFGPass());
989   return false;
990 }
991 
992 bool R600PassConfig::addInstSelector() {
993   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
994   return false;
995 }
996 
997 void R600PassConfig::addPreRegAlloc() {
998   addPass(createR600VectorRegMerger());
999 }
1000 
1001 void R600PassConfig::addPreSched2() {
1002   addPass(createR600EmitClauseMarkers(), false);
1003   if (EnableR600IfConvert)
1004     addPass(&IfConverterID, false);
1005   addPass(createR600ClauseMergePass(), false);
1006 }
1007 
1008 void R600PassConfig::addPreEmitPass() {
1009   addPass(createAMDGPUCFGStructurizerPass(), false);
1010   addPass(createR600ExpandSpecialInstrsPass(), false);
1011   addPass(&FinalizeMachineBundlesID, false);
1012   addPass(createR600Packetizer(), false);
1013   addPass(createR600ControlFlowFinalizer(), false);
1014 }
1015 
1016 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
1017   return new R600PassConfig(*this, PM);
1018 }
1019 
1020 //===----------------------------------------------------------------------===//
1021 // GCN Pass Setup
1022 //===----------------------------------------------------------------------===//
1023 
1024 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1025   MachineSchedContext *C) const {
1026   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1027   if (ST.enableSIScheduler())
1028     return createSIMachineScheduler(C);
1029   return createGCNMaxOccupancyMachineScheduler(C);
1030 }
1031 
1032 bool GCNPassConfig::addPreISel() {
1033   AMDGPUPassConfig::addPreISel();
1034 
1035   addPass(createAMDGPULateCodeGenPreparePass());
1036   if (EnableAtomicOptimizations) {
1037     addPass(createAMDGPUAtomicOptimizerPass());
1038   }
1039 
1040   // FIXME: We need to run a pass to propagate the attributes when calls are
1041   // supported.
1042 
1043   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1044   // regions formed by them.
1045   addPass(&AMDGPUUnifyDivergentExitNodesID);
1046   if (!LateCFGStructurize) {
1047     if (EnableStructurizerWorkarounds) {
1048       addPass(createFixIrreduciblePass());
1049       addPass(createUnifyLoopExitsPass());
1050     }
1051     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1052   }
1053   addPass(createSinkingPass());
1054   addPass(createAMDGPUAnnotateUniformValues());
1055   if (!LateCFGStructurize) {
1056     addPass(createSIAnnotateControlFlowPass());
1057   }
1058   addPass(createLCSSAPass());
1059 
1060   return false;
1061 }
1062 
1063 void GCNPassConfig::addMachineSSAOptimization() {
1064   TargetPassConfig::addMachineSSAOptimization();
1065 
1066   // We want to fold operands after PeepholeOptimizer has run (or as part of
1067   // it), because it will eliminate extra copies making it easier to fold the
1068   // real source operand. We want to eliminate dead instructions after, so that
1069   // we see fewer uses of the copies. We then need to clean up the dead
1070   // instructions leftover after the operands are folded as well.
1071   //
1072   // XXX - Can we get away without running DeadMachineInstructionElim again?
1073   addPass(&SIFoldOperandsID);
1074   if (EnableDPPCombine)
1075     addPass(&GCNDPPCombineID);
1076   addPass(&DeadMachineInstructionElimID);
1077   addPass(&SILoadStoreOptimizerID);
1078   if (EnableSDWAPeephole) {
1079     addPass(&SIPeepholeSDWAID);
1080     addPass(&EarlyMachineLICMID);
1081     addPass(&MachineCSEID);
1082     addPass(&SIFoldOperandsID);
1083     addPass(&DeadMachineInstructionElimID);
1084   }
1085   addPass(createSIShrinkInstructionsPass());
1086 }
1087 
1088 bool GCNPassConfig::addILPOpts() {
1089   if (EnableEarlyIfConversion)
1090     addPass(&EarlyIfConverterID);
1091 
1092   TargetPassConfig::addILPOpts();
1093   return false;
1094 }
1095 
1096 bool GCNPassConfig::addInstSelector() {
1097   AMDGPUPassConfig::addInstSelector();
1098   addPass(&SIFixSGPRCopiesID);
1099   addPass(createSILowerI1CopiesPass());
1100   addPass(createSIAddIMGInitPass());
1101   return false;
1102 }
1103 
1104 bool GCNPassConfig::addIRTranslator() {
1105   addPass(new IRTranslator(getOptLevel()));
1106   return false;
1107 }
1108 
1109 void GCNPassConfig::addPreLegalizeMachineIR() {
1110   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1111   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1112   addPass(new Localizer());
1113 }
1114 
1115 bool GCNPassConfig::addLegalizeMachineIR() {
1116   addPass(new Legalizer());
1117   return false;
1118 }
1119 
1120 void GCNPassConfig::addPreRegBankSelect() {
1121   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1122   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1123 }
1124 
1125 bool GCNPassConfig::addRegBankSelect() {
1126   addPass(new RegBankSelect());
1127   return false;
1128 }
1129 
1130 void GCNPassConfig::addPreGlobalInstructionSelect() {
1131   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1132   addPass(createAMDGPURegBankCombiner(IsOptNone));
1133 }
1134 
1135 bool GCNPassConfig::addGlobalInstructionSelect() {
1136   addPass(new InstructionSelect(getOptLevel()));
1137   // TODO: Fix instruction selection to do the right thing for image
1138   // instructions with tfe or lwe in the first place, instead of running a
1139   // separate pass to fix them up?
1140   addPass(createSIAddIMGInitPass());
1141   return false;
1142 }
1143 
1144 void GCNPassConfig::addPreRegAlloc() {
1145   if (LateCFGStructurize) {
1146     addPass(createAMDGPUMachineCFGStructurizerPass());
1147   }
1148 }
1149 
1150 void GCNPassConfig::addFastRegAlloc() {
1151   // FIXME: We have to disable the verifier here because of PHIElimination +
1152   // TwoAddressInstructions disabling it.
1153 
1154   // This must be run immediately after phi elimination and before
1155   // TwoAddressInstructions, otherwise the processing of the tied operand of
1156   // SI_ELSE will introduce a copy of the tied operand source after the else.
1157   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1158 
1159   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1160   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1161 
1162   TargetPassConfig::addFastRegAlloc();
1163 }
1164 
1165 void GCNPassConfig::addOptimizedRegAlloc() {
1166   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1167   // instructions that cause scheduling barriers.
1168   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1169   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1170 
1171   if (OptExecMaskPreRA)
1172     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1173   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1174 
1175   // This must be run immediately after phi elimination and before
1176   // TwoAddressInstructions, otherwise the processing of the tied operand of
1177   // SI_ELSE will introduce a copy of the tied operand source after the else.
1178   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1179 
1180   if (EnableDCEInRA)
1181     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1182 
1183   TargetPassConfig::addOptimizedRegAlloc();
1184 }
1185 
1186 bool GCNPassConfig::addPreRewrite() {
1187   if (EnableRegReassign) {
1188     addPass(&GCNNSAReassignID);
1189     addPass(&GCNRegBankReassignID);
1190   }
1191   return true;
1192 }
1193 
1194 void GCNPassConfig::addPostRegAlloc() {
1195   addPass(&SIFixVGPRCopiesID);
1196   if (getOptLevel() > CodeGenOpt::None)
1197     addPass(&SIOptimizeExecMaskingID);
1198   TargetPassConfig::addPostRegAlloc();
1199 
1200   // Equivalent of PEI for SGPRs.
1201   addPass(&SILowerSGPRSpillsID);
1202 }
1203 
1204 void GCNPassConfig::addPreSched2() {
1205   addPass(&SIPostRABundlerID);
1206 }
1207 
1208 void GCNPassConfig::addPreEmitPass() {
1209   addPass(createSIMemoryLegalizerPass());
1210   addPass(createSIInsertWaitcntsPass());
1211   addPass(createSIShrinkInstructionsPass());
1212   addPass(createSIModeRegisterPass());
1213 
1214   if (getOptLevel() > CodeGenOpt::None)
1215     addPass(&SIInsertHardClausesID);
1216 
1217   addPass(&SILateBranchLoweringPassID);
1218   if (getOptLevel() > CodeGenOpt::None)
1219     addPass(&SIPreEmitPeepholeID);
1220   // The hazard recognizer that runs as part of the post-ra scheduler does not
1221   // guarantee to be able handle all hazards correctly. This is because if there
1222   // are multiple scheduling regions in a basic block, the regions are scheduled
1223   // bottom up, so when we begin to schedule a region we don't know what
1224   // instructions were emitted directly before it.
1225   //
1226   // Here we add a stand-alone hazard recognizer pass which can handle all
1227   // cases.
1228   addPass(&PostRAHazardRecognizerID);
1229   addPass(&BranchRelaxationPassID);
1230 }
1231 
1232 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1233   return new GCNPassConfig(*this, PM);
1234 }
1235 
1236 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1237   return new yaml::SIMachineFunctionInfo();
1238 }
1239 
1240 yaml::MachineFunctionInfo *
1241 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1242   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1243   return new yaml::SIMachineFunctionInfo(*MFI,
1244                                          *MF.getSubtarget().getRegisterInfo());
1245 }
1246 
1247 bool GCNTargetMachine::parseMachineFunctionInfo(
1248     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1249     SMDiagnostic &Error, SMRange &SourceRange) const {
1250   const yaml::SIMachineFunctionInfo &YamlMFI =
1251       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1252   MachineFunction &MF = PFS.MF;
1253   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1254 
1255   MFI->initializeBaseYamlFields(YamlMFI);
1256 
1257   if (MFI->Occupancy == 0) {
1258     // Fixup the subtarget dependent default value.
1259     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1260     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1261   }
1262 
1263   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1264     Register TempReg;
1265     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1266       SourceRange = RegName.SourceRange;
1267       return true;
1268     }
1269     RegVal = TempReg;
1270 
1271     return false;
1272   };
1273 
1274   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1275     // Create a diagnostic for a the register string literal.
1276     const MemoryBuffer &Buffer =
1277         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1278     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1279                          RegName.Value.size(), SourceMgr::DK_Error,
1280                          "incorrect register class for field", RegName.Value,
1281                          None, None);
1282     SourceRange = RegName.SourceRange;
1283     return true;
1284   };
1285 
1286   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1287       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1288       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1289     return true;
1290 
1291   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1292       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1293     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1294   }
1295 
1296   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1297       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1298     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1299   }
1300 
1301   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1302       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1303     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1304   }
1305 
1306   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1307                                    const TargetRegisterClass &RC,
1308                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1309                                    unsigned SystemSGPRs) {
1310     // Skip parsing if it's not present.
1311     if (!A)
1312       return false;
1313 
1314     if (A->IsRegister) {
1315       Register Reg;
1316       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1317         SourceRange = A->RegisterName.SourceRange;
1318         return true;
1319       }
1320       if (!RC.contains(Reg))
1321         return diagnoseRegisterClass(A->RegisterName);
1322       Arg = ArgDescriptor::createRegister(Reg);
1323     } else
1324       Arg = ArgDescriptor::createStack(A->StackOffset);
1325     // Check and apply the optional mask.
1326     if (A->Mask)
1327       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1328 
1329     MFI->NumUserSGPRs += UserSGPRs;
1330     MFI->NumSystemSGPRs += SystemSGPRs;
1331     return false;
1332   };
1333 
1334   if (YamlMFI.ArgInfo &&
1335       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1336                              AMDGPU::SGPR_128RegClass,
1337                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1338        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1339                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1340                              2, 0) ||
1341        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1342                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1343        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1344                              AMDGPU::SReg_64RegClass,
1345                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1346        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1347                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1348                              2, 0) ||
1349        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1350                              AMDGPU::SReg_64RegClass,
1351                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1352        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1353                              AMDGPU::SGPR_32RegClass,
1354                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1355        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1356                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1357                              0, 1) ||
1358        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1359                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1360                              0, 1) ||
1361        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1362                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1363                              0, 1) ||
1364        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1365                              AMDGPU::SGPR_32RegClass,
1366                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1367        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1368                              AMDGPU::SGPR_32RegClass,
1369                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1370        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1371                              AMDGPU::SReg_64RegClass,
1372                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1373        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1374                              AMDGPU::SReg_64RegClass,
1375                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1376        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1377                              AMDGPU::VGPR_32RegClass,
1378                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1379        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1380                              AMDGPU::VGPR_32RegClass,
1381                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1382        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1383                              AMDGPU::VGPR_32RegClass,
1384                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1385     return true;
1386 
1387   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1388   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1389   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1390   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1391   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1392   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1393 
1394   return false;
1395 }
1396