1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #ifdef LLVM_BUILD_GLOBAL_ISEL
23 #include "AMDGPURegisterBankInfo.h"
24 #endif
25 #include "AMDGPUTargetObjectFile.h"
26 #include "AMDGPUTargetTransformInfo.h"
27 #include "GCNIterativeScheduler.h"
28 #include "GCNSchedStrategy.h"
29 #include "R600MachineScheduler.h"
30 #include "SIMachineScheduler.h"
31 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/TargetPassConfig.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Transforms/IPO.h"
39 #include "llvm/Transforms/IPO/AlwaysInliner.h"
40 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
41 #include "llvm/Transforms/Scalar.h"
42 #include "llvm/Transforms/Scalar/GVN.h"
43 #include "llvm/Transforms/Vectorize.h"
44 #include "llvm/IR/Attributes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/LegacyPassManager.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Target/TargetLoweringObjectFile.h"
51 #include <memory>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool> EnableR600IfConvert(
72   "r600-if-convert",
73   cl::desc("Use if conversion pass"),
74   cl::ReallyHidden,
75   cl::init(true));
76 
77 // Option to disable vectorizer for tests.
78 static cl::opt<bool> EnableLoadStoreVectorizer(
79   "amdgpu-load-store-vectorizer",
80   cl::desc("Enable load store vectorizer"),
81   cl::init(true),
82   cl::Hidden);
83 
84 // Option to to control global loads scalarization
85 static cl::opt<bool> ScalarizeGlobal(
86   "amdgpu-scalarize-global-loads",
87   cl::desc("Enable global load scalarization"),
88   cl::init(false),
89   cl::Hidden);
90 
91 // Option to run internalize pass.
92 static cl::opt<bool> InternalizeSymbols(
93   "amdgpu-internalize-symbols",
94   cl::desc("Enable elimination of non-kernel functions and unused globals"),
95   cl::init(false),
96   cl::Hidden);
97 
98 // Option to inline all early.
99 static cl::opt<bool> EarlyInlineAll(
100   "amdgpu-early-inline-all",
101   cl::desc("Inline all functions early"),
102   cl::init(false),
103   cl::Hidden);
104 
105 static cl::opt<bool> EnableSDWAPeephole(
106   "amdgpu-sdwa-peephole",
107   cl::desc("Enable SDWA peepholer"),
108   cl::init(true));
109 
110 // Enable address space based alias analysis
111 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
112   cl::desc("Enable AMDGPU Alias Analysis"),
113   cl::init(true));
114 
115 // Option to enable new waitcnt insertion pass.
116 static cl::opt<bool> EnableSIInsertWaitcntsPass(
117   "enable-si-insert-waitcnts",
118   cl::desc("Use new waitcnt insertion pass"),
119   cl::init(false));
120 
121 // Option to run late CFG structurizer
122 static cl::opt<bool> LateCFGStructurize(
123   "amdgpu-late-structurize",
124   cl::desc("Enable late CFG structurization"),
125   cl::init(false),
126   cl::Hidden);
127 
128 extern "C" void LLVMInitializeAMDGPUTarget() {
129   // Register the target
130   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
131   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
132 
133   PassRegistry *PR = PassRegistry::getPassRegistry();
134   initializeSILowerI1CopiesPass(*PR);
135   initializeSIFixSGPRCopiesPass(*PR);
136   initializeSIFixVGPRCopiesPass(*PR);
137   initializeSIFoldOperandsPass(*PR);
138   initializeSIPeepholeSDWAPass(*PR);
139   initializeSIShrinkInstructionsPass(*PR);
140   initializeSIFixControlFlowLiveIntervalsPass(*PR);
141   initializeSILoadStoreOptimizerPass(*PR);
142   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
143   initializeAMDGPUAnnotateUniformValuesPass(*PR);
144   initializeAMDGPULowerIntrinsicsPass(*PR);
145   initializeAMDGPUPromoteAllocaPass(*PR);
146   initializeAMDGPUCodeGenPreparePass(*PR);
147   initializeAMDGPUUnifyMetadataPass(*PR);
148   initializeSIAnnotateControlFlowPass(*PR);
149   initializeSIInsertWaitsPass(*PR);
150   initializeSIInsertWaitcntsPass(*PR);
151   initializeSIWholeQuadModePass(*PR);
152   initializeSILowerControlFlowPass(*PR);
153   initializeSIInsertSkipsPass(*PR);
154   initializeSIDebuggerInsertNopsPass(*PR);
155   initializeSIOptimizeExecMaskingPass(*PR);
156   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
157   initializeAMDGPUAAWrapperPassPass(*PR);
158 }
159 
160 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
161   return llvm::make_unique<AMDGPUTargetObjectFile>();
162 }
163 
164 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
165   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
166 }
167 
168 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
169   return new SIScheduleDAGMI(C);
170 }
171 
172 static ScheduleDAGInstrs *
173 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
174   ScheduleDAGMILive *DAG =
175     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
176   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
177   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
178   return DAG;
179 }
180 
181 static ScheduleDAGInstrs *
182 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
183   auto DAG = new GCNIterativeScheduler(C,
184     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
185   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
186   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
187   return DAG;
188 }
189 
190 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
191   return new GCNIterativeScheduler(C,
192     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
193 }
194 
195 static MachineSchedRegistry
196 R600SchedRegistry("r600", "Run R600's custom scheduler",
197                    createR600MachineScheduler);
198 
199 static MachineSchedRegistry
200 SISchedRegistry("si", "Run SI's custom scheduler",
201                 createSIMachineScheduler);
202 
203 static MachineSchedRegistry
204 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
205                              "Run GCN scheduler to maximize occupancy",
206                              createGCNMaxOccupancyMachineScheduler);
207 
208 static MachineSchedRegistry
209 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
210   "Run GCN scheduler to maximize occupancy (experimental)",
211   createIterativeGCNMaxOccupancyMachineScheduler);
212 
213 static MachineSchedRegistry
214 GCNMinRegSchedRegistry("gcn-minreg",
215   "Run GCN iterative scheduler for minimal register usage (experimental)",
216   createMinRegScheduler);
217 
218 static StringRef computeDataLayout(const Triple &TT) {
219   if (TT.getArch() == Triple::r600) {
220     // 32-bit pointers.
221     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
222             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
223   }
224 
225   // 32-bit private, local, and region pointers. 64-bit global, constant and
226   // flat.
227   if (TT.getEnvironmentName() == "amdgiz" ||
228       TT.getEnvironmentName() == "amdgizcl")
229     return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
230          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
231          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
232   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
233       "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
234       "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
235 }
236 
237 LLVM_READNONE
238 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
239   if (!GPU.empty())
240     return GPU;
241 
242   // HSA only supports CI+, so change the default GPU to a CI for HSA.
243   if (TT.getArch() == Triple::amdgcn)
244     return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
245 
246   return "r600";
247 }
248 
249 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
250   // The AMDGPU toolchain only supports generating shared objects, so we
251   // must always use PIC.
252   return Reloc::PIC_;
253 }
254 
255 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
256                                          StringRef CPU, StringRef FS,
257                                          TargetOptions Options,
258                                          Optional<Reloc::Model> RM,
259                                          CodeModel::Model CM,
260                                          CodeGenOpt::Level OptLevel)
261   : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
262                       FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
263     TLOF(createTLOF(getTargetTriple())) {
264   AS = AMDGPU::getAMDGPUAS(TT);
265   initAsmInfo();
266 }
267 
268 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
269 
270 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
271   Attribute GPUAttr = F.getFnAttribute("target-cpu");
272   return GPUAttr.hasAttribute(Attribute::None) ?
273     getTargetCPU() : GPUAttr.getValueAsString();
274 }
275 
276 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
277   Attribute FSAttr = F.getFnAttribute("target-features");
278 
279   return FSAttr.hasAttribute(Attribute::None) ?
280     getTargetFeatureString() :
281     FSAttr.getValueAsString();
282 }
283 
284 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
285   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
286       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
287         AAR.addAAResult(WrapperPass->getResult());
288       });
289 }
290 
291 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
292   Builder.DivergentTarget = true;
293 
294   bool Internalize = InternalizeSymbols &&
295                      (getOptLevel() > CodeGenOpt::None) &&
296                      (getTargetTriple().getArch() == Triple::amdgcn);
297   bool EarlyInline = EarlyInlineAll &&
298                      (getOptLevel() > CodeGenOpt::None);
299   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && getOptLevel() > CodeGenOpt::None;
300 
301   Builder.addExtension(
302     PassManagerBuilder::EP_ModuleOptimizerEarly,
303     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
304                                          legacy::PassManagerBase &PM) {
305       if (AMDGPUAA) {
306         PM.add(createAMDGPUAAWrapperPass());
307         PM.add(createAMDGPUExternalAAWrapperPass());
308       }
309       PM.add(createAMDGPUUnifyMetadataPass());
310       if (Internalize) {
311         PM.add(createInternalizePass([=](const GlobalValue &GV) -> bool {
312           if (const Function *F = dyn_cast<Function>(&GV)) {
313             if (F->isDeclaration())
314                 return true;
315             switch (F->getCallingConv()) {
316             default:
317               return false;
318             case CallingConv::AMDGPU_VS:
319             case CallingConv::AMDGPU_HS:
320             case CallingConv::AMDGPU_GS:
321             case CallingConv::AMDGPU_PS:
322             case CallingConv::AMDGPU_CS:
323             case CallingConv::AMDGPU_KERNEL:
324             case CallingConv::SPIR_KERNEL:
325               return true;
326             }
327           }
328           return !GV.use_empty();
329         }));
330         PM.add(createGlobalDCEPass());
331       }
332       if (EarlyInline)
333         PM.add(createAMDGPUAlwaysInlinePass(false));
334   });
335 
336   Builder.addExtension(
337     PassManagerBuilder::EP_EarlyAsPossible,
338     [AMDGPUAA](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
339       if (AMDGPUAA) {
340         PM.add(createAMDGPUAAWrapperPass());
341         PM.add(createAMDGPUExternalAAWrapperPass());
342       }
343   });
344 }
345 
346 //===----------------------------------------------------------------------===//
347 // R600 Target Machine (R600 -> Cayman)
348 //===----------------------------------------------------------------------===//
349 
350 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
351                                      StringRef CPU, StringRef FS,
352                                      TargetOptions Options,
353                                      Optional<Reloc::Model> RM,
354                                      CodeModel::Model CM, CodeGenOpt::Level OL)
355   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
356   setRequiresStructuredCFG(true);
357 }
358 
359 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
360   const Function &F) const {
361   StringRef GPU = getGPUName(F);
362   StringRef FS = getFeatureString(F);
363 
364   SmallString<128> SubtargetKey(GPU);
365   SubtargetKey.append(FS);
366 
367   auto &I = SubtargetMap[SubtargetKey];
368   if (!I) {
369     // This needs to be done before we create a new subtarget since any
370     // creation will depend on the TM and the code generation flags on the
371     // function that reside in TargetOptions.
372     resetTargetOptions(F);
373     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
374   }
375 
376   return I.get();
377 }
378 
379 //===----------------------------------------------------------------------===//
380 // GCN Target Machine (SI+)
381 //===----------------------------------------------------------------------===//
382 
383 #ifdef LLVM_BUILD_GLOBAL_ISEL
384 namespace {
385 
386 struct SIGISelActualAccessor : public GISelAccessor {
387   std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
388   std::unique_ptr<InstructionSelector> InstSelector;
389   std::unique_ptr<LegalizerInfo> Legalizer;
390   std::unique_ptr<RegisterBankInfo> RegBankInfo;
391   const AMDGPUCallLowering *getCallLowering() const override {
392     return CallLoweringInfo.get();
393   }
394   const InstructionSelector *getInstructionSelector() const override {
395     return InstSelector.get();
396   }
397   const LegalizerInfo *getLegalizerInfo() const override {
398     return Legalizer.get();
399   }
400   const RegisterBankInfo *getRegBankInfo() const override {
401     return RegBankInfo.get();
402   }
403 };
404 
405 } // end anonymous namespace
406 #endif
407 
408 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
409                                    StringRef CPU, StringRef FS,
410                                    TargetOptions Options,
411                                    Optional<Reloc::Model> RM,
412                                    CodeModel::Model CM, CodeGenOpt::Level OL)
413   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
414 
415 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
416   StringRef GPU = getGPUName(F);
417   StringRef FS = getFeatureString(F);
418 
419   SmallString<128> SubtargetKey(GPU);
420   SubtargetKey.append(FS);
421 
422   auto &I = SubtargetMap[SubtargetKey];
423   if (!I) {
424     // This needs to be done before we create a new subtarget since any
425     // creation will depend on the TM and the code generation flags on the
426     // function that reside in TargetOptions.
427     resetTargetOptions(F);
428     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
429 
430 #ifndef LLVM_BUILD_GLOBAL_ISEL
431     GISelAccessor *GISel = new GISelAccessor();
432 #else
433     SIGISelActualAccessor *GISel = new SIGISelActualAccessor();
434     GISel->CallLoweringInfo.reset(
435       new AMDGPUCallLowering(*I->getTargetLowering()));
436     GISel->Legalizer.reset(new AMDGPULegalizerInfo());
437 
438     GISel->RegBankInfo.reset(new AMDGPURegisterBankInfo(*I->getRegisterInfo()));
439     GISel->InstSelector.reset(new AMDGPUInstructionSelector(*I,
440 				*static_cast<AMDGPURegisterBankInfo*>(GISel->RegBankInfo.get())));
441 #endif
442 
443     I->setGISelAccessor(*GISel);
444   }
445 
446   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
447 
448   return I.get();
449 }
450 
451 //===----------------------------------------------------------------------===//
452 // AMDGPU Pass Setup
453 //===----------------------------------------------------------------------===//
454 
455 namespace {
456 
457 class AMDGPUPassConfig : public TargetPassConfig {
458 public:
459   AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
460     : TargetPassConfig(TM, PM) {
461     // Exceptions and StackMaps are not supported, so these passes will never do
462     // anything.
463     disablePass(&StackMapLivenessID);
464     disablePass(&FuncletLayoutID);
465   }
466 
467   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
468     return getTM<AMDGPUTargetMachine>();
469   }
470 
471   ScheduleDAGInstrs *
472   createMachineScheduler(MachineSchedContext *C) const override {
473     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
474     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
475     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
476     return DAG;
477   }
478 
479   void addEarlyCSEOrGVNPass();
480   void addStraightLineScalarOptimizationPasses();
481   void addIRPasses() override;
482   void addCodeGenPrepare() override;
483   bool addPreISel() override;
484   bool addInstSelector() override;
485   bool addGCPasses() override;
486 };
487 
488 class R600PassConfig final : public AMDGPUPassConfig {
489 public:
490   R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
491     : AMDGPUPassConfig(TM, PM) {}
492 
493   ScheduleDAGInstrs *createMachineScheduler(
494     MachineSchedContext *C) const override {
495     return createR600MachineScheduler(C);
496   }
497 
498   bool addPreISel() override;
499   void addPreRegAlloc() override;
500   void addPreSched2() override;
501   void addPreEmitPass() override;
502 };
503 
504 class GCNPassConfig final : public AMDGPUPassConfig {
505 public:
506   GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
507     : AMDGPUPassConfig(TM, PM) {}
508 
509   GCNTargetMachine &getGCNTargetMachine() const {
510     return getTM<GCNTargetMachine>();
511   }
512 
513   ScheduleDAGInstrs *
514   createMachineScheduler(MachineSchedContext *C) const override;
515 
516   bool addPreISel() override;
517   void addMachineSSAOptimization() override;
518   bool addILPOpts() override;
519   bool addInstSelector() override;
520 #ifdef LLVM_BUILD_GLOBAL_ISEL
521   bool addIRTranslator() override;
522   bool addLegalizeMachineIR() override;
523   bool addRegBankSelect() override;
524   bool addGlobalInstructionSelect() override;
525 #endif
526   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
527   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
528   void addPreRegAlloc() override;
529   void addPostRegAlloc() override;
530   void addPreSched2() override;
531   void addPreEmitPass() override;
532 };
533 
534 } // end anonymous namespace
535 
536 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
537   return TargetIRAnalysis([this](const Function &F) {
538     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
539   });
540 }
541 
542 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
543   if (getOptLevel() == CodeGenOpt::Aggressive)
544     addPass(createGVNPass());
545   else
546     addPass(createEarlyCSEPass());
547 }
548 
549 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
550   addPass(createSeparateConstOffsetFromGEPPass());
551   addPass(createSpeculativeExecutionPass());
552   // ReassociateGEPs exposes more opportunites for SLSR. See
553   // the example in reassociate-geps-and-slsr.ll.
554   addPass(createStraightLineStrengthReducePass());
555   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
556   // EarlyCSE can reuse.
557   addEarlyCSEOrGVNPass();
558   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
559   addPass(createNaryReassociatePass());
560   // NaryReassociate on GEPs creates redundant common expressions, so run
561   // EarlyCSE after it.
562   addPass(createEarlyCSEPass());
563 }
564 
565 void AMDGPUPassConfig::addIRPasses() {
566   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
567 
568   // There is no reason to run these.
569   disablePass(&StackMapLivenessID);
570   disablePass(&FuncletLayoutID);
571   disablePass(&PatchableFunctionID);
572 
573   addPass(createAMDGPULowerIntrinsicsPass());
574 
575   // Function calls are not supported, so make sure we inline everything.
576   addPass(createAMDGPUAlwaysInlinePass());
577   addPass(createAlwaysInlinerLegacyPass());
578   // We need to add the barrier noop pass, otherwise adding the function
579   // inlining pass will cause all of the PassConfigs passes to be run
580   // one function at a time, which means if we have a nodule with two
581   // functions, then we will generate code for the first function
582   // without ever running any passes on the second.
583   addPass(createBarrierNoopPass());
584 
585   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
586     // TODO: May want to move later or split into an early and late one.
587 
588     addPass(createAMDGPUCodeGenPreparePass());
589   }
590 
591   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
592   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
593 
594   if (TM.getOptLevel() > CodeGenOpt::None) {
595     addPass(createInferAddressSpacesPass());
596     addPass(createAMDGPUPromoteAlloca());
597 
598     if (EnableSROA)
599       addPass(createSROAPass());
600 
601     addStraightLineScalarOptimizationPasses();
602 
603     if (EnableAMDGPUAliasAnalysis) {
604       addPass(createAMDGPUAAWrapperPass());
605       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
606                                              AAResults &AAR) {
607         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
608           AAR.addAAResult(WrapperPass->getResult());
609         }));
610     }
611   }
612 
613   TargetPassConfig::addIRPasses();
614 
615   // EarlyCSE is not always strong enough to clean up what LSR produces. For
616   // example, GVN can combine
617   //
618   //   %0 = add %a, %b
619   //   %1 = add %b, %a
620   //
621   // and
622   //
623   //   %0 = shl nsw %a, 2
624   //   %1 = shl %a, 2
625   //
626   // but EarlyCSE can do neither of them.
627   if (getOptLevel() != CodeGenOpt::None)
628     addEarlyCSEOrGVNPass();
629 }
630 
631 void AMDGPUPassConfig::addCodeGenPrepare() {
632   TargetPassConfig::addCodeGenPrepare();
633 
634   if (EnableLoadStoreVectorizer)
635     addPass(createLoadStoreVectorizerPass());
636 }
637 
638 bool AMDGPUPassConfig::addPreISel() {
639   addPass(createFlattenCFGPass());
640   return false;
641 }
642 
643 bool AMDGPUPassConfig::addInstSelector() {
644   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));
645   return false;
646 }
647 
648 bool AMDGPUPassConfig::addGCPasses() {
649   // Do nothing. GC is not supported.
650   return false;
651 }
652 
653 //===----------------------------------------------------------------------===//
654 // R600 Pass Setup
655 //===----------------------------------------------------------------------===//
656 
657 bool R600PassConfig::addPreISel() {
658   AMDGPUPassConfig::addPreISel();
659 
660   if (EnableR600StructurizeCFG)
661     addPass(createStructurizeCFGPass());
662   return false;
663 }
664 
665 void R600PassConfig::addPreRegAlloc() {
666   addPass(createR600VectorRegMerger());
667 }
668 
669 void R600PassConfig::addPreSched2() {
670   addPass(createR600EmitClauseMarkers(), false);
671   if (EnableR600IfConvert)
672     addPass(&IfConverterID, false);
673   addPass(createR600ClauseMergePass(), false);
674 }
675 
676 void R600PassConfig::addPreEmitPass() {
677   addPass(createAMDGPUCFGStructurizerPass(), false);
678   addPass(createR600ExpandSpecialInstrsPass(), false);
679   addPass(&FinalizeMachineBundlesID, false);
680   addPass(createR600Packetizer(), false);
681   addPass(createR600ControlFlowFinalizer(), false);
682 }
683 
684 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
685   return new R600PassConfig(this, PM);
686 }
687 
688 //===----------------------------------------------------------------------===//
689 // GCN Pass Setup
690 //===----------------------------------------------------------------------===//
691 
692 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
693   MachineSchedContext *C) const {
694   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
695   if (ST.enableSIScheduler())
696     return createSIMachineScheduler(C);
697   return createGCNMaxOccupancyMachineScheduler(C);
698 }
699 
700 bool GCNPassConfig::addPreISel() {
701   AMDGPUPassConfig::addPreISel();
702 
703   // FIXME: We need to run a pass to propagate the attributes when calls are
704   // supported.
705   addPass(createAMDGPUAnnotateKernelFeaturesPass());
706 
707   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
708   // regions formed by them.
709   addPass(&AMDGPUUnifyDivergentExitNodesID);
710   if (!LateCFGStructurize) {
711     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
712   }
713   addPass(createSinkingPass());
714   addPass(createSITypeRewriter());
715   addPass(createAMDGPUAnnotateUniformValues());
716   if (!LateCFGStructurize) {
717     addPass(createSIAnnotateControlFlowPass());
718   }
719 
720   return false;
721 }
722 
723 void GCNPassConfig::addMachineSSAOptimization() {
724   TargetPassConfig::addMachineSSAOptimization();
725 
726   // We want to fold operands after PeepholeOptimizer has run (or as part of
727   // it), because it will eliminate extra copies making it easier to fold the
728   // real source operand. We want to eliminate dead instructions after, so that
729   // we see fewer uses of the copies. We then need to clean up the dead
730   // instructions leftover after the operands are folded as well.
731   //
732   // XXX - Can we get away without running DeadMachineInstructionElim again?
733   addPass(&SIFoldOperandsID);
734   addPass(&DeadMachineInstructionElimID);
735   addPass(&SILoadStoreOptimizerID);
736   addPass(createSIShrinkInstructionsPass());
737   if (EnableSDWAPeephole) {
738     addPass(&SIPeepholeSDWAID);
739     addPass(&DeadMachineInstructionElimID);
740   }
741 }
742 
743 bool GCNPassConfig::addILPOpts() {
744   if (EnableEarlyIfConversion)
745     addPass(&EarlyIfConverterID);
746 
747   TargetPassConfig::addILPOpts();
748   return false;
749 }
750 
751 bool GCNPassConfig::addInstSelector() {
752   AMDGPUPassConfig::addInstSelector();
753   addPass(createSILowerI1CopiesPass());
754   addPass(&SIFixSGPRCopiesID);
755   return false;
756 }
757 
758 #ifdef LLVM_BUILD_GLOBAL_ISEL
759 bool GCNPassConfig::addIRTranslator() {
760   addPass(new IRTranslator());
761   return false;
762 }
763 
764 bool GCNPassConfig::addLegalizeMachineIR() {
765   addPass(new Legalizer());
766   return false;
767 }
768 
769 bool GCNPassConfig::addRegBankSelect() {
770   addPass(new RegBankSelect());
771   return false;
772 }
773 
774 bool GCNPassConfig::addGlobalInstructionSelect() {
775   addPass(new InstructionSelect());
776   return false;
777 }
778 
779 #endif
780 
781 void GCNPassConfig::addPreRegAlloc() {
782   if (LateCFGStructurize) {
783     addPass(createAMDGPUMachineCFGStructurizerPass());
784   }
785   addPass(createSIWholeQuadModePass());
786 }
787 
788 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
789   // FIXME: We have to disable the verifier here because of PHIElimination +
790   // TwoAddressInstructions disabling it.
791 
792   // This must be run immediately after phi elimination and before
793   // TwoAddressInstructions, otherwise the processing of the tied operand of
794   // SI_ELSE will introduce a copy of the tied operand source after the else.
795   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
796 
797   TargetPassConfig::addFastRegAlloc(RegAllocPass);
798 }
799 
800 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
801   // This needs to be run directly before register allocation because earlier
802   // passes might recompute live intervals.
803   insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
804 
805   // This must be run immediately after phi elimination and before
806   // TwoAddressInstructions, otherwise the processing of the tied operand of
807   // SI_ELSE will introduce a copy of the tied operand source after the else.
808   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
809 
810   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
811 }
812 
813 void GCNPassConfig::addPostRegAlloc() {
814   addPass(&SIFixVGPRCopiesID);
815   addPass(&SIOptimizeExecMaskingID);
816   TargetPassConfig::addPostRegAlloc();
817 }
818 
819 void GCNPassConfig::addPreSched2() {
820 }
821 
822 void GCNPassConfig::addPreEmitPass() {
823   // The hazard recognizer that runs as part of the post-ra scheduler does not
824   // guarantee to be able handle all hazards correctly. This is because if there
825   // are multiple scheduling regions in a basic block, the regions are scheduled
826   // bottom up, so when we begin to schedule a region we don't know what
827   // instructions were emitted directly before it.
828   //
829   // Here we add a stand-alone hazard recognizer pass which can handle all
830   // cases.
831   addPass(&PostRAHazardRecognizerID);
832 
833   if (EnableSIInsertWaitcntsPass)
834     addPass(createSIInsertWaitcntsPass());
835   else
836     addPass(createSIInsertWaitsPass());
837   addPass(createSIShrinkInstructionsPass());
838   addPass(&SIInsertSkipsPassID);
839   addPass(createSIDebuggerInsertNopsPass());
840   addPass(&BranchRelaxationPassID);
841 }
842 
843 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
844   return new GCNPassConfig(this, PM);
845 }
846 
847