1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Utils.h"
49 #include "llvm/Transforms/Vectorize.h"
50 #include <memory>
51 
52 using namespace llvm;
53 
54 static cl::opt<bool> EnableR600StructurizeCFG(
55   "r600-ir-structurize",
56   cl::desc("Use StructurizeCFG IR pass"),
57   cl::init(true));
58 
59 static cl::opt<bool> EnableSROA(
60   "amdgpu-sroa",
61   cl::desc("Run SROA after promote alloca pass"),
62   cl::ReallyHidden,
63   cl::init(true));
64 
65 static cl::opt<bool>
66 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
67                         cl::desc("Run early if-conversion"),
68                         cl::init(false));
69 
70 static cl::opt<bool> EnableR600IfConvert(
71   "r600-if-convert",
72   cl::desc("Use if conversion pass"),
73   cl::ReallyHidden,
74   cl::init(true));
75 
76 // Option to disable vectorizer for tests.
77 static cl::opt<bool> EnableLoadStoreVectorizer(
78   "amdgpu-load-store-vectorizer",
79   cl::desc("Enable load store vectorizer"),
80   cl::init(true),
81   cl::Hidden);
82 
83 // Option to control global loads scalarization
84 static cl::opt<bool> ScalarizeGlobal(
85   "amdgpu-scalarize-global-loads",
86   cl::desc("Enable global load scalarization"),
87   cl::init(true),
88   cl::Hidden);
89 
90 // Option to run internalize pass.
91 static cl::opt<bool> InternalizeSymbols(
92   "amdgpu-internalize-symbols",
93   cl::desc("Enable elimination of non-kernel functions and unused globals"),
94   cl::init(false),
95   cl::Hidden);
96 
97 // Option to inline all early.
98 static cl::opt<bool> EarlyInlineAll(
99   "amdgpu-early-inline-all",
100   cl::desc("Inline all functions early"),
101   cl::init(false),
102   cl::Hidden);
103 
104 static cl::opt<bool> EnableSDWAPeephole(
105   "amdgpu-sdwa-peephole",
106   cl::desc("Enable SDWA peepholer"),
107   cl::init(true));
108 
109 static cl::opt<bool> EnableDPPCombine(
110   "amdgpu-dpp-combine",
111   cl::desc("Enable DPP combiner"),
112   cl::init(false));
113 
114 // Enable address space based alias analysis
115 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
116   cl::desc("Enable AMDGPU Alias Analysis"),
117   cl::init(true));
118 
119 // Option to run late CFG structurizer
120 static cl::opt<bool, true> LateCFGStructurize(
121   "amdgpu-late-structurize",
122   cl::desc("Enable late CFG structurization"),
123   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
124   cl::Hidden);
125 
126 static cl::opt<bool, true> EnableAMDGPUFunctionCalls(
127   "amdgpu-function-calls",
128   cl::desc("Enable AMDGPU function call support"),
129   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
130   cl::init(false),
131   cl::Hidden);
132 
133 // Enable lib calls simplifications
134 static cl::opt<bool> EnableLibCallSimplify(
135   "amdgpu-simplify-libcall",
136   cl::desc("Enable amdgpu library simplifications"),
137   cl::init(true),
138   cl::Hidden);
139 
140 static cl::opt<bool> EnableLowerKernelArguments(
141   "amdgpu-ir-lower-kernel-arguments",
142   cl::desc("Lower kernel argument loads in IR pass"),
143   cl::init(true),
144   cl::Hidden);
145 
146 // Enable atomic optimization
147 static cl::opt<bool> EnableAtomicOptimizations(
148   "amdgpu-atomic-optimizations",
149   cl::desc("Enable atomic optimizations"),
150   cl::init(false),
151   cl::Hidden);
152 
153 extern "C" void LLVMInitializeAMDGPUTarget() {
154   // Register the target
155   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
156   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
157 
158   PassRegistry *PR = PassRegistry::getPassRegistry();
159   initializeR600ClauseMergePassPass(*PR);
160   initializeR600ControlFlowFinalizerPass(*PR);
161   initializeR600PacketizerPass(*PR);
162   initializeR600ExpandSpecialInstrsPassPass(*PR);
163   initializeR600VectorRegMergerPass(*PR);
164   initializeGlobalISel(*PR);
165   initializeAMDGPUDAGToDAGISelPass(*PR);
166   initializeGCNDPPCombinePass(*PR);
167   initializeSILowerI1CopiesPass(*PR);
168   initializeSIFixSGPRCopiesPass(*PR);
169   initializeSIFixVGPRCopiesPass(*PR);
170   initializeSIFixupVectorISelPass(*PR);
171   initializeSIFoldOperandsPass(*PR);
172   initializeSIPeepholeSDWAPass(*PR);
173   initializeSIShrinkInstructionsPass(*PR);
174   initializeSIOptimizeExecMaskingPreRAPass(*PR);
175   initializeSILoadStoreOptimizerPass(*PR);
176   initializeAMDGPUFixFunctionBitcastsPass(*PR);
177   initializeAMDGPUAlwaysInlinePass(*PR);
178   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
179   initializeAMDGPUAnnotateUniformValuesPass(*PR);
180   initializeAMDGPUArgumentUsageInfoPass(*PR);
181   initializeAMDGPUAtomicOptimizerPass(*PR);
182   initializeAMDGPULowerKernelArgumentsPass(*PR);
183   initializeAMDGPULowerKernelAttributesPass(*PR);
184   initializeAMDGPULowerIntrinsicsPass(*PR);
185   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
186   initializeAMDGPUPromoteAllocaPass(*PR);
187   initializeAMDGPUCodeGenPreparePass(*PR);
188   initializeAMDGPURewriteOutArgumentsPass(*PR);
189   initializeAMDGPUUnifyMetadataPass(*PR);
190   initializeSIAnnotateControlFlowPass(*PR);
191   initializeSIInsertWaitcntsPass(*PR);
192   initializeSIWholeQuadModePass(*PR);
193   initializeSILowerControlFlowPass(*PR);
194   initializeSIInsertSkipsPass(*PR);
195   initializeSIMemoryLegalizerPass(*PR);
196   initializeSIDebuggerInsertNopsPass(*PR);
197   initializeSIOptimizeExecMaskingPass(*PR);
198   initializeSIFixWWMLivenessPass(*PR);
199   initializeSIFormMemoryClausesPass(*PR);
200   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
201   initializeAMDGPUAAWrapperPassPass(*PR);
202   initializeAMDGPUExternalAAWrapperPass(*PR);
203   initializeAMDGPUUseNativeCallsPass(*PR);
204   initializeAMDGPUSimplifyLibCallsPass(*PR);
205   initializeAMDGPUInlinerPass(*PR);
206 }
207 
208 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
209   return llvm::make_unique<AMDGPUTargetObjectFile>();
210 }
211 
212 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
213   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
214 }
215 
216 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
217   return new SIScheduleDAGMI(C);
218 }
219 
220 static ScheduleDAGInstrs *
221 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
222   ScheduleDAGMILive *DAG =
223     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
224   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
225   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
226   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
227   return DAG;
228 }
229 
230 static ScheduleDAGInstrs *
231 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
232   auto DAG = new GCNIterativeScheduler(C,
233     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
234   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
235   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
236   return DAG;
237 }
238 
239 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
240   return new GCNIterativeScheduler(C,
241     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
242 }
243 
244 static ScheduleDAGInstrs *
245 createIterativeILPMachineScheduler(MachineSchedContext *C) {
246   auto DAG = new GCNIterativeScheduler(C,
247     GCNIterativeScheduler::SCHEDULE_ILP);
248   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
249   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
250   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
251   return DAG;
252 }
253 
254 static MachineSchedRegistry
255 R600SchedRegistry("r600", "Run R600's custom scheduler",
256                    createR600MachineScheduler);
257 
258 static MachineSchedRegistry
259 SISchedRegistry("si", "Run SI's custom scheduler",
260                 createSIMachineScheduler);
261 
262 static MachineSchedRegistry
263 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
264                              "Run GCN scheduler to maximize occupancy",
265                              createGCNMaxOccupancyMachineScheduler);
266 
267 static MachineSchedRegistry
268 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
269   "Run GCN scheduler to maximize occupancy (experimental)",
270   createIterativeGCNMaxOccupancyMachineScheduler);
271 
272 static MachineSchedRegistry
273 GCNMinRegSchedRegistry("gcn-minreg",
274   "Run GCN iterative scheduler for minimal register usage (experimental)",
275   createMinRegScheduler);
276 
277 static MachineSchedRegistry
278 GCNILPSchedRegistry("gcn-ilp",
279   "Run GCN iterative scheduler for ILP scheduling (experimental)",
280   createIterativeILPMachineScheduler);
281 
282 static StringRef computeDataLayout(const Triple &TT) {
283   if (TT.getArch() == Triple::r600) {
284     // 32-bit pointers.
285       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
286              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
287   }
288 
289   // 32-bit private, local, and region pointers. 64-bit global, constant and
290   // flat.
291     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
292          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
293          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
294 }
295 
296 LLVM_READNONE
297 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
298   if (!GPU.empty())
299     return GPU;
300 
301   if (TT.getArch() == Triple::amdgcn)
302     return "generic";
303 
304   return "r600";
305 }
306 
307 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
308   // The AMDGPU toolchain only supports generating shared objects, so we
309   // must always use PIC.
310   return Reloc::PIC_;
311 }
312 
313 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
314   if (CM)
315     return *CM;
316   return CodeModel::Small;
317 }
318 
319 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
320                                          StringRef CPU, StringRef FS,
321                                          TargetOptions Options,
322                                          Optional<Reloc::Model> RM,
323                                          Optional<CodeModel::Model> CM,
324                                          CodeGenOpt::Level OptLevel)
325     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
326                         FS, Options, getEffectiveRelocModel(RM),
327                         getEffectiveCodeModel(CM), OptLevel),
328       TLOF(createTLOF(getTargetTriple())) {
329   initAsmInfo();
330 }
331 
332 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
333 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
334 
335 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
336 
337 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
338   Attribute GPUAttr = F.getFnAttribute("target-cpu");
339   return GPUAttr.hasAttribute(Attribute::None) ?
340     getTargetCPU() : GPUAttr.getValueAsString();
341 }
342 
343 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
344   Attribute FSAttr = F.getFnAttribute("target-features");
345 
346   return FSAttr.hasAttribute(Attribute::None) ?
347     getTargetFeatureString() :
348     FSAttr.getValueAsString();
349 }
350 
351 /// Predicate for Internalize pass.
352 static bool mustPreserveGV(const GlobalValue &GV) {
353   if (const Function *F = dyn_cast<Function>(&GV))
354     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
355 
356   return !GV.use_empty();
357 }
358 
359 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
360   Builder.DivergentTarget = true;
361 
362   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
363   bool Internalize = InternalizeSymbols;
364   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
365   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
366   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
367 
368   if (EnableAMDGPUFunctionCalls) {
369     delete Builder.Inliner;
370     Builder.Inliner = createAMDGPUFunctionInliningPass();
371   }
372 
373   Builder.addExtension(
374     PassManagerBuilder::EP_ModuleOptimizerEarly,
375     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
376                                          legacy::PassManagerBase &PM) {
377       if (AMDGPUAA) {
378         PM.add(createAMDGPUAAWrapperPass());
379         PM.add(createAMDGPUExternalAAWrapperPass());
380       }
381       PM.add(createAMDGPUUnifyMetadataPass());
382       if (Internalize) {
383         PM.add(createInternalizePass(mustPreserveGV));
384         PM.add(createGlobalDCEPass());
385       }
386       if (EarlyInline)
387         PM.add(createAMDGPUAlwaysInlinePass(false));
388   });
389 
390   const auto &Opt = Options;
391   Builder.addExtension(
392     PassManagerBuilder::EP_EarlyAsPossible,
393     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
394                                       legacy::PassManagerBase &PM) {
395       if (AMDGPUAA) {
396         PM.add(createAMDGPUAAWrapperPass());
397         PM.add(createAMDGPUExternalAAWrapperPass());
398       }
399       PM.add(llvm::createAMDGPUUseNativeCallsPass());
400       if (LibCallSimplify)
401         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
402   });
403 
404   Builder.addExtension(
405     PassManagerBuilder::EP_CGSCCOptimizerLate,
406     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
407       // Add infer address spaces pass to the opt pipeline after inlining
408       // but before SROA to increase SROA opportunities.
409       PM.add(createInferAddressSpacesPass());
410 
411       // This should run after inlining to have any chance of doing anything,
412       // and before other cleanup optimizations.
413       PM.add(createAMDGPULowerKernelAttributesPass());
414   });
415 }
416 
417 //===----------------------------------------------------------------------===//
418 // R600 Target Machine (R600 -> Cayman)
419 //===----------------------------------------------------------------------===//
420 
421 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
422                                      StringRef CPU, StringRef FS,
423                                      TargetOptions Options,
424                                      Optional<Reloc::Model> RM,
425                                      Optional<CodeModel::Model> CM,
426                                      CodeGenOpt::Level OL, bool JIT)
427     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
428   setRequiresStructuredCFG(true);
429 }
430 
431 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
432   const Function &F) const {
433   StringRef GPU = getGPUName(F);
434   StringRef FS = getFeatureString(F);
435 
436   SmallString<128> SubtargetKey(GPU);
437   SubtargetKey.append(FS);
438 
439   auto &I = SubtargetMap[SubtargetKey];
440   if (!I) {
441     // This needs to be done before we create a new subtarget since any
442     // creation will depend on the TM and the code generation flags on the
443     // function that reside in TargetOptions.
444     resetTargetOptions(F);
445     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
446   }
447 
448   return I.get();
449 }
450 
451 TargetTransformInfo
452 R600TargetMachine::getTargetTransformInfo(const Function &F) {
453   return TargetTransformInfo(R600TTIImpl(this, F));
454 }
455 
456 //===----------------------------------------------------------------------===//
457 // GCN Target Machine (SI+)
458 //===----------------------------------------------------------------------===//
459 
460 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
461                                    StringRef CPU, StringRef FS,
462                                    TargetOptions Options,
463                                    Optional<Reloc::Model> RM,
464                                    Optional<CodeModel::Model> CM,
465                                    CodeGenOpt::Level OL, bool JIT)
466     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
467 
468 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
469   StringRef GPU = getGPUName(F);
470   StringRef FS = getFeatureString(F);
471 
472   SmallString<128> SubtargetKey(GPU);
473   SubtargetKey.append(FS);
474 
475   auto &I = SubtargetMap[SubtargetKey];
476   if (!I) {
477     // This needs to be done before we create a new subtarget since any
478     // creation will depend on the TM and the code generation flags on the
479     // function that reside in TargetOptions.
480     resetTargetOptions(F);
481     I = llvm::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
482   }
483 
484   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
485 
486   return I.get();
487 }
488 
489 TargetTransformInfo
490 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
491   return TargetTransformInfo(GCNTTIImpl(this, F));
492 }
493 
494 //===----------------------------------------------------------------------===//
495 // AMDGPU Pass Setup
496 //===----------------------------------------------------------------------===//
497 
498 namespace {
499 
500 class AMDGPUPassConfig : public TargetPassConfig {
501 public:
502   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
503     : TargetPassConfig(TM, PM) {
504     // Exceptions and StackMaps are not supported, so these passes will never do
505     // anything.
506     disablePass(&StackMapLivenessID);
507     disablePass(&FuncletLayoutID);
508   }
509 
510   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
511     return getTM<AMDGPUTargetMachine>();
512   }
513 
514   ScheduleDAGInstrs *
515   createMachineScheduler(MachineSchedContext *C) const override {
516     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
517     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
518     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
519     return DAG;
520   }
521 
522   void addEarlyCSEOrGVNPass();
523   void addStraightLineScalarOptimizationPasses();
524   void addIRPasses() override;
525   void addCodeGenPrepare() override;
526   bool addPreISel() override;
527   bool addInstSelector() override;
528   bool addGCPasses() override;
529 };
530 
531 class R600PassConfig final : public AMDGPUPassConfig {
532 public:
533   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
534     : AMDGPUPassConfig(TM, PM) {}
535 
536   ScheduleDAGInstrs *createMachineScheduler(
537     MachineSchedContext *C) const override {
538     return createR600MachineScheduler(C);
539   }
540 
541   bool addPreISel() override;
542   bool addInstSelector() override;
543   void addPreRegAlloc() override;
544   void addPreSched2() override;
545   void addPreEmitPass() override;
546 };
547 
548 class GCNPassConfig final : public AMDGPUPassConfig {
549 public:
550   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
551     : AMDGPUPassConfig(TM, PM) {
552     // It is necessary to know the register usage of the entire call graph.  We
553     // allow calls without EnableAMDGPUFunctionCalls if they are marked
554     // noinline, so this is always required.
555     setRequiresCodeGenSCCOrder(true);
556   }
557 
558   GCNTargetMachine &getGCNTargetMachine() const {
559     return getTM<GCNTargetMachine>();
560   }
561 
562   ScheduleDAGInstrs *
563   createMachineScheduler(MachineSchedContext *C) const override;
564 
565   bool addPreISel() override;
566   void addMachineSSAOptimization() override;
567   bool addILPOpts() override;
568   bool addInstSelector() override;
569   bool addIRTranslator() override;
570   bool addLegalizeMachineIR() override;
571   bool addRegBankSelect() override;
572   bool addGlobalInstructionSelect() override;
573   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
574   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
575   void addPreRegAlloc() override;
576   void addPostRegAlloc() override;
577   void addPreSched2() override;
578   void addPreEmitPass() override;
579 };
580 
581 } // end anonymous namespace
582 
583 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
584   if (getOptLevel() == CodeGenOpt::Aggressive)
585     addPass(createGVNPass());
586   else
587     addPass(createEarlyCSEPass());
588 }
589 
590 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
591   addPass(createLICMPass());
592   addPass(createSeparateConstOffsetFromGEPPass());
593   addPass(createSpeculativeExecutionPass());
594   // ReassociateGEPs exposes more opportunites for SLSR. See
595   // the example in reassociate-geps-and-slsr.ll.
596   addPass(createStraightLineStrengthReducePass());
597   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
598   // EarlyCSE can reuse.
599   addEarlyCSEOrGVNPass();
600   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
601   addPass(createNaryReassociatePass());
602   // NaryReassociate on GEPs creates redundant common expressions, so run
603   // EarlyCSE after it.
604   addPass(createEarlyCSEPass());
605 }
606 
607 void AMDGPUPassConfig::addIRPasses() {
608   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
609 
610   // There is no reason to run these.
611   disablePass(&StackMapLivenessID);
612   disablePass(&FuncletLayoutID);
613   disablePass(&PatchableFunctionID);
614 
615   addPass(createAtomicExpandPass());
616 
617   // This must occur before inlining, as the inliner will not look through
618   // bitcast calls.
619   addPass(createAMDGPUFixFunctionBitcastsPass());
620 
621   addPass(createAMDGPULowerIntrinsicsPass());
622 
623   // Function calls are not supported, so make sure we inline everything.
624   addPass(createAMDGPUAlwaysInlinePass());
625   addPass(createAlwaysInlinerLegacyPass());
626   // We need to add the barrier noop pass, otherwise adding the function
627   // inlining pass will cause all of the PassConfigs passes to be run
628   // one function at a time, which means if we have a nodule with two
629   // functions, then we will generate code for the first function
630   // without ever running any passes on the second.
631   addPass(createBarrierNoopPass());
632 
633   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
634     // TODO: May want to move later or split into an early and late one.
635 
636     addPass(createAMDGPUCodeGenPreparePass());
637   }
638 
639   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
640   if (TM.getTargetTriple().getArch() == Triple::r600)
641     addPass(createR600OpenCLImageTypeLoweringPass());
642 
643   // Replace OpenCL enqueued block function pointers with global variables.
644   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
645 
646   if (TM.getOptLevel() > CodeGenOpt::None) {
647     addPass(createInferAddressSpacesPass());
648     addPass(createAMDGPUPromoteAlloca());
649 
650     if (EnableSROA)
651       addPass(createSROAPass());
652 
653     addStraightLineScalarOptimizationPasses();
654 
655     if (EnableAMDGPUAliasAnalysis) {
656       addPass(createAMDGPUAAWrapperPass());
657       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
658                                              AAResults &AAR) {
659         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
660           AAR.addAAResult(WrapperPass->getResult());
661         }));
662     }
663   }
664 
665   TargetPassConfig::addIRPasses();
666 
667   // EarlyCSE is not always strong enough to clean up what LSR produces. For
668   // example, GVN can combine
669   //
670   //   %0 = add %a, %b
671   //   %1 = add %b, %a
672   //
673   // and
674   //
675   //   %0 = shl nsw %a, 2
676   //   %1 = shl %a, 2
677   //
678   // but EarlyCSE can do neither of them.
679   if (getOptLevel() != CodeGenOpt::None)
680     addEarlyCSEOrGVNPass();
681 }
682 
683 void AMDGPUPassConfig::addCodeGenPrepare() {
684   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
685       EnableLowerKernelArguments)
686     addPass(createAMDGPULowerKernelArgumentsPass());
687 
688   TargetPassConfig::addCodeGenPrepare();
689 
690   if (EnableLoadStoreVectorizer)
691     addPass(createLoadStoreVectorizerPass());
692 }
693 
694 bool AMDGPUPassConfig::addPreISel() {
695   addPass(createLowerSwitchPass());
696   addPass(createFlattenCFGPass());
697   return false;
698 }
699 
700 bool AMDGPUPassConfig::addInstSelector() {
701   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
702   return false;
703 }
704 
705 bool AMDGPUPassConfig::addGCPasses() {
706   // Do nothing. GC is not supported.
707   return false;
708 }
709 
710 //===----------------------------------------------------------------------===//
711 // R600 Pass Setup
712 //===----------------------------------------------------------------------===//
713 
714 bool R600PassConfig::addPreISel() {
715   AMDGPUPassConfig::addPreISel();
716 
717   if (EnableR600StructurizeCFG)
718     addPass(createStructurizeCFGPass());
719   return false;
720 }
721 
722 bool R600PassConfig::addInstSelector() {
723   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
724   return false;
725 }
726 
727 void R600PassConfig::addPreRegAlloc() {
728   addPass(createR600VectorRegMerger());
729 }
730 
731 void R600PassConfig::addPreSched2() {
732   addPass(createR600EmitClauseMarkers(), false);
733   if (EnableR600IfConvert)
734     addPass(&IfConverterID, false);
735   addPass(createR600ClauseMergePass(), false);
736 }
737 
738 void R600PassConfig::addPreEmitPass() {
739   addPass(createAMDGPUCFGStructurizerPass(), false);
740   addPass(createR600ExpandSpecialInstrsPass(), false);
741   addPass(&FinalizeMachineBundlesID, false);
742   addPass(createR600Packetizer(), false);
743   addPass(createR600ControlFlowFinalizer(), false);
744 }
745 
746 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
747   return new R600PassConfig(*this, PM);
748 }
749 
750 //===----------------------------------------------------------------------===//
751 // GCN Pass Setup
752 //===----------------------------------------------------------------------===//
753 
754 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
755   MachineSchedContext *C) const {
756   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
757   if (ST.enableSIScheduler())
758     return createSIMachineScheduler(C);
759   return createGCNMaxOccupancyMachineScheduler(C);
760 }
761 
762 bool GCNPassConfig::addPreISel() {
763   AMDGPUPassConfig::addPreISel();
764 
765   if (EnableAtomicOptimizations) {
766     addPass(createAMDGPUAtomicOptimizerPass());
767   }
768 
769   // FIXME: We need to run a pass to propagate the attributes when calls are
770   // supported.
771   addPass(createAMDGPUAnnotateKernelFeaturesPass());
772 
773   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
774   // regions formed by them.
775   addPass(&AMDGPUUnifyDivergentExitNodesID);
776   if (!LateCFGStructurize) {
777     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
778   }
779   addPass(createSinkingPass());
780   addPass(createAMDGPUAnnotateUniformValues());
781   if (!LateCFGStructurize) {
782     addPass(createSIAnnotateControlFlowPass());
783   }
784 
785   return false;
786 }
787 
788 void GCNPassConfig::addMachineSSAOptimization() {
789   TargetPassConfig::addMachineSSAOptimization();
790 
791   // We want to fold operands after PeepholeOptimizer has run (or as part of
792   // it), because it will eliminate extra copies making it easier to fold the
793   // real source operand. We want to eliminate dead instructions after, so that
794   // we see fewer uses of the copies. We then need to clean up the dead
795   // instructions leftover after the operands are folded as well.
796   //
797   // XXX - Can we get away without running DeadMachineInstructionElim again?
798   addPass(&SIFoldOperandsID);
799   if (EnableDPPCombine)
800     addPass(&GCNDPPCombineID);
801   addPass(&DeadMachineInstructionElimID);
802   addPass(&SILoadStoreOptimizerID);
803   if (EnableSDWAPeephole) {
804     addPass(&SIPeepholeSDWAID);
805     addPass(&EarlyMachineLICMID);
806     addPass(&MachineCSEID);
807     addPass(&SIFoldOperandsID);
808     addPass(&DeadMachineInstructionElimID);
809   }
810   addPass(createSIShrinkInstructionsPass());
811 }
812 
813 bool GCNPassConfig::addILPOpts() {
814   if (EnableEarlyIfConversion)
815     addPass(&EarlyIfConverterID);
816 
817   TargetPassConfig::addILPOpts();
818   return false;
819 }
820 
821 bool GCNPassConfig::addInstSelector() {
822   AMDGPUPassConfig::addInstSelector();
823   addPass(&SIFixSGPRCopiesID);
824   addPass(createSILowerI1CopiesPass());
825   addPass(createSIFixupVectorISelPass());
826   return false;
827 }
828 
829 bool GCNPassConfig::addIRTranslator() {
830   addPass(new IRTranslator());
831   return false;
832 }
833 
834 bool GCNPassConfig::addLegalizeMachineIR() {
835   addPass(new Legalizer());
836   return false;
837 }
838 
839 bool GCNPassConfig::addRegBankSelect() {
840   addPass(new RegBankSelect());
841   return false;
842 }
843 
844 bool GCNPassConfig::addGlobalInstructionSelect() {
845   addPass(new InstructionSelect());
846   return false;
847 }
848 
849 void GCNPassConfig::addPreRegAlloc() {
850   if (LateCFGStructurize) {
851     addPass(createAMDGPUMachineCFGStructurizerPass());
852   }
853   addPass(createSIWholeQuadModePass());
854 }
855 
856 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
857   // FIXME: We have to disable the verifier here because of PHIElimination +
858   // TwoAddressInstructions disabling it.
859 
860   // This must be run immediately after phi elimination and before
861   // TwoAddressInstructions, otherwise the processing of the tied operand of
862   // SI_ELSE will introduce a copy of the tied operand source after the else.
863   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
864 
865   // This must be run after SILowerControlFlow, since it needs to use the
866   // machine-level CFG, but before register allocation.
867   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
868 
869   TargetPassConfig::addFastRegAlloc(RegAllocPass);
870 }
871 
872 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
873   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
874 
875   insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
876 
877   // This must be run immediately after phi elimination and before
878   // TwoAddressInstructions, otherwise the processing of the tied operand of
879   // SI_ELSE will introduce a copy of the tied operand source after the else.
880   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
881 
882   // This must be run after SILowerControlFlow, since it needs to use the
883   // machine-level CFG, but before register allocation.
884   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
885 
886   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
887 }
888 
889 void GCNPassConfig::addPostRegAlloc() {
890   addPass(&SIFixVGPRCopiesID);
891   if (getOptLevel() > CodeGenOpt::None)
892     addPass(&SIOptimizeExecMaskingID);
893   TargetPassConfig::addPostRegAlloc();
894 }
895 
896 void GCNPassConfig::addPreSched2() {
897 }
898 
899 void GCNPassConfig::addPreEmitPass() {
900   addPass(createSIMemoryLegalizerPass());
901   addPass(createSIInsertWaitcntsPass());
902   addPass(createSIShrinkInstructionsPass());
903 
904   // The hazard recognizer that runs as part of the post-ra scheduler does not
905   // guarantee to be able handle all hazards correctly. This is because if there
906   // are multiple scheduling regions in a basic block, the regions are scheduled
907   // bottom up, so when we begin to schedule a region we don't know what
908   // instructions were emitted directly before it.
909   //
910   // Here we add a stand-alone hazard recognizer pass which can handle all
911   // cases.
912   //
913   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
914   // be better for it to emit S_NOP <N> when possible.
915   addPass(&PostRAHazardRecognizerID);
916 
917   addPass(&SIInsertSkipsPassID);
918   addPass(createSIDebuggerInsertNopsPass());
919   addPass(&BranchRelaxationPassID);
920 }
921 
922 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
923   return new GCNPassConfig(*this, PM);
924 }
925