1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUExportClustering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
28 #include "R600MachineScheduler.h"
29 #include "SIMachineFunctionInfo.h"
30 #include "SIMachineScheduler.h"
31 #include "TargetInfo/AMDGPUTargetInfo.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
35 #include "llvm/CodeGen/GlobalISel/Localizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MIRParser/MIParser.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/LegacyPassManager.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/Pass.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Transforms/IPO.h"
50 #include "llvm/Transforms/IPO/AlwaysInliner.h"
51 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
52 #include "llvm/Transforms/Scalar.h"
53 #include "llvm/Transforms/Scalar/GVN.h"
54 #include "llvm/Transforms/Utils.h"
55 #include "llvm/Transforms/Vectorize.h"
56 #include <memory>
57 
58 using namespace llvm;
59 
60 static cl::opt<bool> EnableR600StructurizeCFG(
61   "r600-ir-structurize",
62   cl::desc("Use StructurizeCFG IR pass"),
63   cl::init(true));
64 
65 static cl::opt<bool> EnableSROA(
66   "amdgpu-sroa",
67   cl::desc("Run SROA after promote alloca pass"),
68   cl::ReallyHidden,
69   cl::init(true));
70 
71 static cl::opt<bool>
72 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
73                         cl::desc("Run early if-conversion"),
74                         cl::init(false));
75 
76 static cl::opt<bool>
77 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
78             cl::desc("Run pre-RA exec mask optimizations"),
79             cl::init(true));
80 
81 static cl::opt<bool> EnableR600IfConvert(
82   "r600-if-convert",
83   cl::desc("Use if conversion pass"),
84   cl::ReallyHidden,
85   cl::init(true));
86 
87 // Option to disable vectorizer for tests.
88 static cl::opt<bool> EnableLoadStoreVectorizer(
89   "amdgpu-load-store-vectorizer",
90   cl::desc("Enable load store vectorizer"),
91   cl::init(true),
92   cl::Hidden);
93 
94 // Option to control global loads scalarization
95 static cl::opt<bool> ScalarizeGlobal(
96   "amdgpu-scalarize-global-loads",
97   cl::desc("Enable global load scalarization"),
98   cl::init(true),
99   cl::Hidden);
100 
101 // Option to run internalize pass.
102 static cl::opt<bool> InternalizeSymbols(
103   "amdgpu-internalize-symbols",
104   cl::desc("Enable elimination of non-kernel functions and unused globals"),
105   cl::init(false),
106   cl::Hidden);
107 
108 // Option to inline all early.
109 static cl::opt<bool> EarlyInlineAll(
110   "amdgpu-early-inline-all",
111   cl::desc("Inline all functions early"),
112   cl::init(false),
113   cl::Hidden);
114 
115 static cl::opt<bool> EnableSDWAPeephole(
116   "amdgpu-sdwa-peephole",
117   cl::desc("Enable SDWA peepholer"),
118   cl::init(true));
119 
120 static cl::opt<bool> EnableDPPCombine(
121   "amdgpu-dpp-combine",
122   cl::desc("Enable DPP combiner"),
123   cl::init(true));
124 
125 // Enable address space based alias analysis
126 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
127   cl::desc("Enable AMDGPU Alias Analysis"),
128   cl::init(true));
129 
130 // Option to run late CFG structurizer
131 static cl::opt<bool, true> LateCFGStructurize(
132   "amdgpu-late-structurize",
133   cl::desc("Enable late CFG structurization"),
134   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
135   cl::Hidden);
136 
137 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
138   "amdgpu-function-calls",
139   cl::desc("Enable AMDGPU function call support"),
140   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
141   cl::init(true),
142   cl::Hidden);
143 
144 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
145   "amdgpu-fixed-function-abi",
146   cl::desc("Enable all implicit function arguments"),
147   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
148   cl::init(false),
149   cl::Hidden);
150 
151 // Enable lib calls simplifications
152 static cl::opt<bool> EnableLibCallSimplify(
153   "amdgpu-simplify-libcall",
154   cl::desc("Enable amdgpu library simplifications"),
155   cl::init(true),
156   cl::Hidden);
157 
158 static cl::opt<bool> EnableLowerKernelArguments(
159   "amdgpu-ir-lower-kernel-arguments",
160   cl::desc("Lower kernel argument loads in IR pass"),
161   cl::init(true),
162   cl::Hidden);
163 
164 static cl::opt<bool> EnableRegReassign(
165   "amdgpu-reassign-regs",
166   cl::desc("Enable register reassign optimizations on gfx10+"),
167   cl::init(true),
168   cl::Hidden);
169 
170 // Enable atomic optimization
171 static cl::opt<bool> EnableAtomicOptimizations(
172   "amdgpu-atomic-optimizations",
173   cl::desc("Enable atomic optimizations"),
174   cl::init(false),
175   cl::Hidden);
176 
177 // Enable Mode register optimization
178 static cl::opt<bool> EnableSIModeRegisterPass(
179   "amdgpu-mode-register",
180   cl::desc("Enable mode register pass"),
181   cl::init(true),
182   cl::Hidden);
183 
184 // Option is used in lit tests to prevent deadcoding of patterns inspected.
185 static cl::opt<bool>
186 EnableDCEInRA("amdgpu-dce-in-ra",
187     cl::init(true), cl::Hidden,
188     cl::desc("Enable machine DCE inside regalloc"));
189 
190 static cl::opt<bool> EnableScalarIRPasses(
191   "amdgpu-scalar-ir-passes",
192   cl::desc("Enable scalar IR passes"),
193   cl::init(true),
194   cl::Hidden);
195 
196 static cl::opt<bool> EnableStructurizerWorkarounds(
197     "amdgpu-enable-structurizer-workarounds",
198     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
199     cl::Hidden);
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFoldOperandsPass(*PR);
220   initializeSIPeepholeSDWAPass(*PR);
221   initializeSIShrinkInstructionsPass(*PR);
222   initializeSIOptimizeExecMaskingPreRAPass(*PR);
223   initializeSILoadStoreOptimizerPass(*PR);
224   initializeAMDGPUFixFunctionBitcastsPass(*PR);
225   initializeAMDGPUAlwaysInlinePass(*PR);
226   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
227   initializeAMDGPUAnnotateUniformValuesPass(*PR);
228   initializeAMDGPUArgumentUsageInfoPass(*PR);
229   initializeAMDGPUAtomicOptimizerPass(*PR);
230   initializeAMDGPULowerKernelArgumentsPass(*PR);
231   initializeAMDGPULowerKernelAttributesPass(*PR);
232   initializeAMDGPULowerIntrinsicsPass(*PR);
233   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
234   initializeAMDGPUPostLegalizerCombinerPass(*PR);
235   initializeAMDGPUPreLegalizerCombinerPass(*PR);
236   initializeAMDGPUPromoteAllocaPass(*PR);
237   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
238   initializeAMDGPUCodeGenPreparePass(*PR);
239   initializeAMDGPULateCodeGenPreparePass(*PR);
240   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
241   initializeAMDGPUPropagateAttributesLatePass(*PR);
242   initializeAMDGPURewriteOutArgumentsPass(*PR);
243   initializeAMDGPUUnifyMetadataPass(*PR);
244   initializeSIAnnotateControlFlowPass(*PR);
245   initializeSIInsertHardClausesPass(*PR);
246   initializeSIInsertWaitcntsPass(*PR);
247   initializeSIModeRegisterPass(*PR);
248   initializeSIWholeQuadModePass(*PR);
249   initializeSILowerControlFlowPass(*PR);
250   initializeSIRemoveShortExecBranchesPass(*PR);
251   initializeSIPreEmitPeepholePass(*PR);
252   initializeSIInsertSkipsPass(*PR);
253   initializeSIMemoryLegalizerPass(*PR);
254   initializeSIOptimizeExecMaskingPass(*PR);
255   initializeSIPreAllocateWWMRegsPass(*PR);
256   initializeSIFormMemoryClausesPass(*PR);
257   initializeSIPostRABundlerPass(*PR);
258   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
259   initializeAMDGPUAAWrapperPassPass(*PR);
260   initializeAMDGPUExternalAAWrapperPass(*PR);
261   initializeAMDGPUUseNativeCallsPass(*PR);
262   initializeAMDGPUSimplifyLibCallsPass(*PR);
263   initializeAMDGPUInlinerPass(*PR);
264   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
265   initializeGCNRegBankReassignPass(*PR);
266   initializeGCNNSAReassignPass(*PR);
267   initializeSIAddIMGInitPass(*PR);
268 }
269 
270 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
271   return std::make_unique<AMDGPUTargetObjectFile>();
272 }
273 
274 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
275   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
276 }
277 
278 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
279   return new SIScheduleDAGMI(C);
280 }
281 
282 static ScheduleDAGInstrs *
283 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
284   ScheduleDAGMILive *DAG =
285     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
286   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
287   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
288   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
289   return DAG;
290 }
291 
292 static ScheduleDAGInstrs *
293 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
294   auto DAG = new GCNIterativeScheduler(C,
295     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
296   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
297   return DAG;
298 }
299 
300 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
301   return new GCNIterativeScheduler(C,
302     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
303 }
304 
305 static ScheduleDAGInstrs *
306 createIterativeILPMachineScheduler(MachineSchedContext *C) {
307   auto DAG = new GCNIterativeScheduler(C,
308     GCNIterativeScheduler::SCHEDULE_ILP);
309   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
310   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
311   return DAG;
312 }
313 
314 static MachineSchedRegistry
315 R600SchedRegistry("r600", "Run R600's custom scheduler",
316                    createR600MachineScheduler);
317 
318 static MachineSchedRegistry
319 SISchedRegistry("si", "Run SI's custom scheduler",
320                 createSIMachineScheduler);
321 
322 static MachineSchedRegistry
323 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
324                              "Run GCN scheduler to maximize occupancy",
325                              createGCNMaxOccupancyMachineScheduler);
326 
327 static MachineSchedRegistry
328 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
329   "Run GCN scheduler to maximize occupancy (experimental)",
330   createIterativeGCNMaxOccupancyMachineScheduler);
331 
332 static MachineSchedRegistry
333 GCNMinRegSchedRegistry("gcn-minreg",
334   "Run GCN iterative scheduler for minimal register usage (experimental)",
335   createMinRegScheduler);
336 
337 static MachineSchedRegistry
338 GCNILPSchedRegistry("gcn-ilp",
339   "Run GCN iterative scheduler for ILP scheduling (experimental)",
340   createIterativeILPMachineScheduler);
341 
342 static StringRef computeDataLayout(const Triple &TT) {
343   if (TT.getArch() == Triple::r600) {
344     // 32-bit pointers.
345     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
346            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
347   }
348 
349   // 32-bit private, local, and region pointers. 64-bit global, constant and
350   // flat, non-integral buffer fat pointers.
351   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
352          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
353          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
354          "-ni:7";
355 }
356 
357 LLVM_READNONE
358 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
359   if (!GPU.empty())
360     return GPU;
361 
362   // Need to default to a target with flat support for HSA.
363   if (TT.getArch() == Triple::amdgcn)
364     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
365 
366   return "r600";
367 }
368 
369 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
370   // The AMDGPU toolchain only supports generating shared objects, so we
371   // must always use PIC.
372   return Reloc::PIC_;
373 }
374 
375 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
376                                          StringRef CPU, StringRef FS,
377                                          TargetOptions Options,
378                                          Optional<Reloc::Model> RM,
379                                          Optional<CodeModel::Model> CM,
380                                          CodeGenOpt::Level OptLevel)
381     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
382                         FS, Options, getEffectiveRelocModel(RM),
383                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
384       TLOF(createTLOF(getTargetTriple())) {
385   initAsmInfo();
386   if (TT.getArch() == Triple::amdgcn) {
387     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
388       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
389     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
390       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
391   }
392 }
393 
394 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
395 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
396 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
397 
398 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
399 
400 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
401   Attribute GPUAttr = F.getFnAttribute("target-cpu");
402   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
403 }
404 
405 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
406   Attribute FSAttr = F.getFnAttribute("target-features");
407 
408   return FSAttr.isValid() ? FSAttr.getValueAsString()
409                           : getTargetFeatureString();
410 }
411 
412 /// Predicate for Internalize pass.
413 static bool mustPreserveGV(const GlobalValue &GV) {
414   if (const Function *F = dyn_cast<Function>(&GV))
415     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
416 
417   return !GV.use_empty();
418 }
419 
420 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
421   Builder.DivergentTarget = true;
422 
423   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
424   bool Internalize = InternalizeSymbols;
425   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
426   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
427   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
428 
429   if (EnableFunctionCalls) {
430     delete Builder.Inliner;
431     Builder.Inliner = createAMDGPUFunctionInliningPass();
432   }
433 
434   Builder.addExtension(
435     PassManagerBuilder::EP_ModuleOptimizerEarly,
436     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
437                                                legacy::PassManagerBase &PM) {
438       if (AMDGPUAA) {
439         PM.add(createAMDGPUAAWrapperPass());
440         PM.add(createAMDGPUExternalAAWrapperPass());
441       }
442       PM.add(createAMDGPUUnifyMetadataPass());
443       PM.add(createAMDGPUPrintfRuntimeBinding());
444       if (Internalize)
445         PM.add(createInternalizePass(mustPreserveGV));
446       PM.add(createAMDGPUPropagateAttributesLatePass(this));
447       if (Internalize)
448         PM.add(createGlobalDCEPass());
449       if (EarlyInline)
450         PM.add(createAMDGPUAlwaysInlinePass(false));
451   });
452 
453   Builder.addExtension(
454     PassManagerBuilder::EP_EarlyAsPossible,
455     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
456                                       legacy::PassManagerBase &PM) {
457       if (AMDGPUAA) {
458         PM.add(createAMDGPUAAWrapperPass());
459         PM.add(createAMDGPUExternalAAWrapperPass());
460       }
461       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
462       PM.add(llvm::createAMDGPUUseNativeCallsPass());
463       if (LibCallSimplify)
464         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
465   });
466 
467   Builder.addExtension(
468     PassManagerBuilder::EP_CGSCCOptimizerLate,
469     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
470       // Add infer address spaces pass to the opt pipeline after inlining
471       // but before SROA to increase SROA opportunities.
472       PM.add(createInferAddressSpacesPass());
473 
474       // This should run after inlining to have any chance of doing anything,
475       // and before other cleanup optimizations.
476       PM.add(createAMDGPULowerKernelAttributesPass());
477 
478       // Promote alloca to vector before SROA and loop unroll. If we manage
479       // to eliminate allocas before unroll we may choose to unroll less.
480       if (EnableOpt)
481         PM.add(createAMDGPUPromoteAllocaToVector());
482   });
483 }
484 
485 //===----------------------------------------------------------------------===//
486 // R600 Target Machine (R600 -> Cayman)
487 //===----------------------------------------------------------------------===//
488 
489 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
490                                      StringRef CPU, StringRef FS,
491                                      TargetOptions Options,
492                                      Optional<Reloc::Model> RM,
493                                      Optional<CodeModel::Model> CM,
494                                      CodeGenOpt::Level OL, bool JIT)
495     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
496   setRequiresStructuredCFG(true);
497 
498   // Override the default since calls aren't supported for r600.
499   if (EnableFunctionCalls &&
500       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
501     EnableFunctionCalls = false;
502 }
503 
504 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
505   const Function &F) const {
506   StringRef GPU = getGPUName(F);
507   StringRef FS = getFeatureString(F);
508 
509   SmallString<128> SubtargetKey(GPU);
510   SubtargetKey.append(FS);
511 
512   auto &I = SubtargetMap[SubtargetKey];
513   if (!I) {
514     // This needs to be done before we create a new subtarget since any
515     // creation will depend on the TM and the code generation flags on the
516     // function that reside in TargetOptions.
517     resetTargetOptions(F);
518     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
519   }
520 
521   return I.get();
522 }
523 
524 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
525                                               unsigned DestAS) const {
526   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
527          AMDGPU::isFlatGlobalAddrSpace(DestAS);
528 }
529 
530 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
531   const auto *LD = dyn_cast<LoadInst>(V);
532   if (!LD)
533     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
534 
535   // It must be a generic pointer loaded.
536   assert(V->getType()->isPointerTy() &&
537          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
538 
539   const auto *Ptr = LD->getPointerOperand();
540   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
541     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
542   // For a generic pointer loaded from the constant memory, it could be assumed
543   // as a global pointer since the constant memory is only populated on the
544   // host side. As implied by the offload programming model, only global
545   // pointers could be referenced on the host side.
546   return AMDGPUAS::GLOBAL_ADDRESS;
547 }
548 
549 TargetTransformInfo
550 R600TargetMachine::getTargetTransformInfo(const Function &F) {
551   return TargetTransformInfo(R600TTIImpl(this, F));
552 }
553 
554 //===----------------------------------------------------------------------===//
555 // GCN Target Machine (SI+)
556 //===----------------------------------------------------------------------===//
557 
558 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
559                                    StringRef CPU, StringRef FS,
560                                    TargetOptions Options,
561                                    Optional<Reloc::Model> RM,
562                                    Optional<CodeModel::Model> CM,
563                                    CodeGenOpt::Level OL, bool JIT)
564     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
565 
566 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
567   StringRef GPU = getGPUName(F);
568   StringRef FS = getFeatureString(F);
569 
570   SmallString<128> SubtargetKey(GPU);
571   SubtargetKey.append(FS);
572 
573   auto &I = SubtargetMap[SubtargetKey];
574   if (!I) {
575     // This needs to be done before we create a new subtarget since any
576     // creation will depend on the TM and the code generation flags on the
577     // function that reside in TargetOptions.
578     resetTargetOptions(F);
579     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
580   }
581 
582   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
583 
584   return I.get();
585 }
586 
587 TargetTransformInfo
588 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
589   return TargetTransformInfo(GCNTTIImpl(this, F));
590 }
591 
592 //===----------------------------------------------------------------------===//
593 // AMDGPU Pass Setup
594 //===----------------------------------------------------------------------===//
595 
596 namespace {
597 
598 class AMDGPUPassConfig : public TargetPassConfig {
599 public:
600   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
601     : TargetPassConfig(TM, PM) {
602     // Exceptions and StackMaps are not supported, so these passes will never do
603     // anything.
604     disablePass(&StackMapLivenessID);
605     disablePass(&FuncletLayoutID);
606   }
607 
608   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
609     return getTM<AMDGPUTargetMachine>();
610   }
611 
612   ScheduleDAGInstrs *
613   createMachineScheduler(MachineSchedContext *C) const override {
614     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
615     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
616     return DAG;
617   }
618 
619   void addEarlyCSEOrGVNPass();
620   void addStraightLineScalarOptimizationPasses();
621   void addIRPasses() override;
622   void addCodeGenPrepare() override;
623   bool addPreISel() override;
624   bool addInstSelector() override;
625   bool addGCPasses() override;
626 
627   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
628 };
629 
630 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
631   return getStandardCSEConfigForOpt(TM->getOptLevel());
632 }
633 
634 class R600PassConfig final : public AMDGPUPassConfig {
635 public:
636   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
637     : AMDGPUPassConfig(TM, PM) {}
638 
639   ScheduleDAGInstrs *createMachineScheduler(
640     MachineSchedContext *C) const override {
641     return createR600MachineScheduler(C);
642   }
643 
644   bool addPreISel() override;
645   bool addInstSelector() override;
646   void addPreRegAlloc() override;
647   void addPreSched2() override;
648   void addPreEmitPass() override;
649 };
650 
651 class GCNPassConfig final : public AMDGPUPassConfig {
652 public:
653   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
654     : AMDGPUPassConfig(TM, PM) {
655     // It is necessary to know the register usage of the entire call graph.  We
656     // allow calls without EnableAMDGPUFunctionCalls if they are marked
657     // noinline, so this is always required.
658     setRequiresCodeGenSCCOrder(true);
659   }
660 
661   GCNTargetMachine &getGCNTargetMachine() const {
662     return getTM<GCNTargetMachine>();
663   }
664 
665   ScheduleDAGInstrs *
666   createMachineScheduler(MachineSchedContext *C) const override;
667 
668   bool addPreISel() override;
669   void addMachineSSAOptimization() override;
670   bool addILPOpts() override;
671   bool addInstSelector() override;
672   bool addIRTranslator() override;
673   void addPreLegalizeMachineIR() override;
674   bool addLegalizeMachineIR() override;
675   void addPreRegBankSelect() override;
676   bool addRegBankSelect() override;
677   bool addGlobalInstructionSelect() override;
678   void addFastRegAlloc() override;
679   void addOptimizedRegAlloc() override;
680   void addPreRegAlloc() override;
681   bool addPreRewrite() override;
682   void addPostRegAlloc() override;
683   void addPreSched2() override;
684   void addPreEmitPass() override;
685 };
686 
687 } // end anonymous namespace
688 
689 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
690   if (getOptLevel() == CodeGenOpt::Aggressive)
691     addPass(createGVNPass());
692   else
693     addPass(createEarlyCSEPass());
694 }
695 
696 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
697   addPass(createLICMPass());
698   addPass(createSeparateConstOffsetFromGEPPass());
699   addPass(createSpeculativeExecutionPass());
700   // ReassociateGEPs exposes more opportunites for SLSR. See
701   // the example in reassociate-geps-and-slsr.ll.
702   addPass(createStraightLineStrengthReducePass());
703   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
704   // EarlyCSE can reuse.
705   addEarlyCSEOrGVNPass();
706   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
707   addPass(createNaryReassociatePass());
708   // NaryReassociate on GEPs creates redundant common expressions, so run
709   // EarlyCSE after it.
710   addPass(createEarlyCSEPass());
711 }
712 
713 void AMDGPUPassConfig::addIRPasses() {
714   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
715 
716   // There is no reason to run these.
717   disablePass(&StackMapLivenessID);
718   disablePass(&FuncletLayoutID);
719   disablePass(&PatchableFunctionID);
720 
721   addPass(createAMDGPUPrintfRuntimeBinding());
722 
723   // This must occur before inlining, as the inliner will not look through
724   // bitcast calls.
725   addPass(createAMDGPUFixFunctionBitcastsPass());
726 
727   // A call to propagate attributes pass in the backend in case opt was not run.
728   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
729 
730   addPass(createAtomicExpandPass());
731 
732 
733   addPass(createAMDGPULowerIntrinsicsPass());
734 
735   // Function calls are not supported, so make sure we inline everything.
736   addPass(createAMDGPUAlwaysInlinePass());
737   addPass(createAlwaysInlinerLegacyPass());
738   // We need to add the barrier noop pass, otherwise adding the function
739   // inlining pass will cause all of the PassConfigs passes to be run
740   // one function at a time, which means if we have a nodule with two
741   // functions, then we will generate code for the first function
742   // without ever running any passes on the second.
743   addPass(createBarrierNoopPass());
744 
745   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
746   if (TM.getTargetTriple().getArch() == Triple::r600)
747     addPass(createR600OpenCLImageTypeLoweringPass());
748 
749   // Replace OpenCL enqueued block function pointers with global variables.
750   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
751 
752   if (TM.getOptLevel() > CodeGenOpt::None) {
753     addPass(createInferAddressSpacesPass());
754     addPass(createAMDGPUPromoteAlloca());
755 
756     if (EnableSROA)
757       addPass(createSROAPass());
758 
759     if (EnableScalarIRPasses)
760       addStraightLineScalarOptimizationPasses();
761 
762     if (EnableAMDGPUAliasAnalysis) {
763       addPass(createAMDGPUAAWrapperPass());
764       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
765                                              AAResults &AAR) {
766         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
767           AAR.addAAResult(WrapperPass->getResult());
768         }));
769     }
770   }
771 
772   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
773     // TODO: May want to move later or split into an early and late one.
774     addPass(createAMDGPUCodeGenPreparePass());
775   }
776 
777   TargetPassConfig::addIRPasses();
778 
779   // EarlyCSE is not always strong enough to clean up what LSR produces. For
780   // example, GVN can combine
781   //
782   //   %0 = add %a, %b
783   //   %1 = add %b, %a
784   //
785   // and
786   //
787   //   %0 = shl nsw %a, 2
788   //   %1 = shl %a, 2
789   //
790   // but EarlyCSE can do neither of them.
791   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
792     addEarlyCSEOrGVNPass();
793 }
794 
795 void AMDGPUPassConfig::addCodeGenPrepare() {
796   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
797     addPass(createAMDGPUAnnotateKernelFeaturesPass());
798 
799   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
800       EnableLowerKernelArguments)
801     addPass(createAMDGPULowerKernelArgumentsPass());
802 
803   addPass(&AMDGPUPerfHintAnalysisID);
804 
805   TargetPassConfig::addCodeGenPrepare();
806 
807   if (EnableLoadStoreVectorizer)
808     addPass(createLoadStoreVectorizerPass());
809 
810   // LowerSwitch pass may introduce unreachable blocks that can
811   // cause unexpected behavior for subsequent passes. Placing it
812   // here seems better that these blocks would get cleaned up by
813   // UnreachableBlockElim inserted next in the pass flow.
814   addPass(createLowerSwitchPass());
815 }
816 
817 bool AMDGPUPassConfig::addPreISel() {
818   addPass(createFlattenCFGPass());
819   return false;
820 }
821 
822 bool AMDGPUPassConfig::addInstSelector() {
823   // Defer the verifier until FinalizeISel.
824   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
825   return false;
826 }
827 
828 bool AMDGPUPassConfig::addGCPasses() {
829   // Do nothing. GC is not supported.
830   return false;
831 }
832 
833 //===----------------------------------------------------------------------===//
834 // R600 Pass Setup
835 //===----------------------------------------------------------------------===//
836 
837 bool R600PassConfig::addPreISel() {
838   AMDGPUPassConfig::addPreISel();
839 
840   if (EnableR600StructurizeCFG)
841     addPass(createStructurizeCFGPass());
842   return false;
843 }
844 
845 bool R600PassConfig::addInstSelector() {
846   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
847   return false;
848 }
849 
850 void R600PassConfig::addPreRegAlloc() {
851   addPass(createR600VectorRegMerger());
852 }
853 
854 void R600PassConfig::addPreSched2() {
855   addPass(createR600EmitClauseMarkers(), false);
856   if (EnableR600IfConvert)
857     addPass(&IfConverterID, false);
858   addPass(createR600ClauseMergePass(), false);
859 }
860 
861 void R600PassConfig::addPreEmitPass() {
862   addPass(createAMDGPUCFGStructurizerPass(), false);
863   addPass(createR600ExpandSpecialInstrsPass(), false);
864   addPass(&FinalizeMachineBundlesID, false);
865   addPass(createR600Packetizer(), false);
866   addPass(createR600ControlFlowFinalizer(), false);
867 }
868 
869 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
870   return new R600PassConfig(*this, PM);
871 }
872 
873 //===----------------------------------------------------------------------===//
874 // GCN Pass Setup
875 //===----------------------------------------------------------------------===//
876 
877 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
878   MachineSchedContext *C) const {
879   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
880   if (ST.enableSIScheduler())
881     return createSIMachineScheduler(C);
882   return createGCNMaxOccupancyMachineScheduler(C);
883 }
884 
885 bool GCNPassConfig::addPreISel() {
886   AMDGPUPassConfig::addPreISel();
887 
888   addPass(createAMDGPULateCodeGenPreparePass());
889   if (EnableAtomicOptimizations) {
890     addPass(createAMDGPUAtomicOptimizerPass());
891   }
892 
893   // FIXME: We need to run a pass to propagate the attributes when calls are
894   // supported.
895 
896   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
897   // regions formed by them.
898   addPass(&AMDGPUUnifyDivergentExitNodesID);
899   if (!LateCFGStructurize) {
900     if (EnableStructurizerWorkarounds) {
901       addPass(createFixIrreduciblePass());
902       addPass(createUnifyLoopExitsPass());
903     }
904     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
905   }
906   addPass(createSinkingPass());
907   addPass(createAMDGPUAnnotateUniformValues());
908   if (!LateCFGStructurize) {
909     addPass(createSIAnnotateControlFlowPass());
910   }
911   addPass(createLCSSAPass());
912 
913   return false;
914 }
915 
916 void GCNPassConfig::addMachineSSAOptimization() {
917   TargetPassConfig::addMachineSSAOptimization();
918 
919   // We want to fold operands after PeepholeOptimizer has run (or as part of
920   // it), because it will eliminate extra copies making it easier to fold the
921   // real source operand. We want to eliminate dead instructions after, so that
922   // we see fewer uses of the copies. We then need to clean up the dead
923   // instructions leftover after the operands are folded as well.
924   //
925   // XXX - Can we get away without running DeadMachineInstructionElim again?
926   addPass(&SIFoldOperandsID);
927   if (EnableDPPCombine)
928     addPass(&GCNDPPCombineID);
929   addPass(&DeadMachineInstructionElimID);
930   addPass(&SILoadStoreOptimizerID);
931   if (EnableSDWAPeephole) {
932     addPass(&SIPeepholeSDWAID);
933     addPass(&EarlyMachineLICMID);
934     addPass(&MachineCSEID);
935     addPass(&SIFoldOperandsID);
936     addPass(&DeadMachineInstructionElimID);
937   }
938   addPass(createSIShrinkInstructionsPass());
939 }
940 
941 bool GCNPassConfig::addILPOpts() {
942   if (EnableEarlyIfConversion)
943     addPass(&EarlyIfConverterID);
944 
945   TargetPassConfig::addILPOpts();
946   return false;
947 }
948 
949 bool GCNPassConfig::addInstSelector() {
950   AMDGPUPassConfig::addInstSelector();
951   addPass(&SIFixSGPRCopiesID);
952   addPass(createSILowerI1CopiesPass());
953   addPass(createSIAddIMGInitPass());
954   return false;
955 }
956 
957 bool GCNPassConfig::addIRTranslator() {
958   addPass(new IRTranslator(getOptLevel()));
959   return false;
960 }
961 
962 void GCNPassConfig::addPreLegalizeMachineIR() {
963   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
964   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
965   addPass(new Localizer());
966 }
967 
968 bool GCNPassConfig::addLegalizeMachineIR() {
969   addPass(new Legalizer());
970   return false;
971 }
972 
973 void GCNPassConfig::addPreRegBankSelect() {
974   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
975   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
976 }
977 
978 bool GCNPassConfig::addRegBankSelect() {
979   addPass(new RegBankSelect());
980   return false;
981 }
982 
983 bool GCNPassConfig::addGlobalInstructionSelect() {
984   addPass(new InstructionSelect());
985   return false;
986 }
987 
988 void GCNPassConfig::addPreRegAlloc() {
989   if (LateCFGStructurize) {
990     addPass(createAMDGPUMachineCFGStructurizerPass());
991   }
992 }
993 
994 void GCNPassConfig::addFastRegAlloc() {
995   // FIXME: We have to disable the verifier here because of PHIElimination +
996   // TwoAddressInstructions disabling it.
997 
998   // This must be run immediately after phi elimination and before
999   // TwoAddressInstructions, otherwise the processing of the tied operand of
1000   // SI_ELSE will introduce a copy of the tied operand source after the else.
1001   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1002 
1003   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1004   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1005 
1006   TargetPassConfig::addFastRegAlloc();
1007 }
1008 
1009 void GCNPassConfig::addOptimizedRegAlloc() {
1010   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1011   // instructions that cause scheduling barriers.
1012   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1013   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1014 
1015   if (OptExecMaskPreRA)
1016     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1017   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1018 
1019   // This must be run immediately after phi elimination and before
1020   // TwoAddressInstructions, otherwise the processing of the tied operand of
1021   // SI_ELSE will introduce a copy of the tied operand source after the else.
1022   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1023 
1024   if (EnableDCEInRA)
1025     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1026 
1027   TargetPassConfig::addOptimizedRegAlloc();
1028 }
1029 
1030 bool GCNPassConfig::addPreRewrite() {
1031   if (EnableRegReassign) {
1032     addPass(&GCNNSAReassignID);
1033     addPass(&GCNRegBankReassignID);
1034   }
1035   return true;
1036 }
1037 
1038 void GCNPassConfig::addPostRegAlloc() {
1039   addPass(&SIFixVGPRCopiesID);
1040   if (getOptLevel() > CodeGenOpt::None)
1041     addPass(&SIOptimizeExecMaskingID);
1042   TargetPassConfig::addPostRegAlloc();
1043 
1044   // Equivalent of PEI for SGPRs.
1045   addPass(&SILowerSGPRSpillsID);
1046 }
1047 
1048 void GCNPassConfig::addPreSched2() {
1049   addPass(&SIPostRABundlerID);
1050 }
1051 
1052 void GCNPassConfig::addPreEmitPass() {
1053   addPass(createSIMemoryLegalizerPass());
1054   addPass(createSIInsertWaitcntsPass());
1055   addPass(createSIShrinkInstructionsPass());
1056   addPass(createSIModeRegisterPass());
1057 
1058   if (getOptLevel() > CodeGenOpt::None)
1059     addPass(&SIInsertHardClausesID);
1060 
1061   addPass(&SIRemoveShortExecBranchesID);
1062   addPass(&SIInsertSkipsPassID);
1063   addPass(&SIPreEmitPeepholeID);
1064   // The hazard recognizer that runs as part of the post-ra scheduler does not
1065   // guarantee to be able handle all hazards correctly. This is because if there
1066   // are multiple scheduling regions in a basic block, the regions are scheduled
1067   // bottom up, so when we begin to schedule a region we don't know what
1068   // instructions were emitted directly before it.
1069   //
1070   // Here we add a stand-alone hazard recognizer pass which can handle all
1071   // cases.
1072   addPass(&PostRAHazardRecognizerID);
1073   addPass(&BranchRelaxationPassID);
1074 }
1075 
1076 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1077   return new GCNPassConfig(*this, PM);
1078 }
1079 
1080 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1081   return new yaml::SIMachineFunctionInfo();
1082 }
1083 
1084 yaml::MachineFunctionInfo *
1085 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1086   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1087   return new yaml::SIMachineFunctionInfo(*MFI,
1088                                          *MF.getSubtarget().getRegisterInfo());
1089 }
1090 
1091 bool GCNTargetMachine::parseMachineFunctionInfo(
1092     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1093     SMDiagnostic &Error, SMRange &SourceRange) const {
1094   const yaml::SIMachineFunctionInfo &YamlMFI =
1095       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1096   MachineFunction &MF = PFS.MF;
1097   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1098 
1099   MFI->initializeBaseYamlFields(YamlMFI);
1100 
1101   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1102     Register TempReg;
1103     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1104       SourceRange = RegName.SourceRange;
1105       return true;
1106     }
1107     RegVal = TempReg;
1108 
1109     return false;
1110   };
1111 
1112   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1113     // Create a diagnostic for a the register string literal.
1114     const MemoryBuffer &Buffer =
1115         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1116     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1117                          RegName.Value.size(), SourceMgr::DK_Error,
1118                          "incorrect register class for field", RegName.Value,
1119                          None, None);
1120     SourceRange = RegName.SourceRange;
1121     return true;
1122   };
1123 
1124   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1125       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1126       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1127     return true;
1128 
1129   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1130       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1131     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1132   }
1133 
1134   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1135       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1136     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1137   }
1138 
1139   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1140       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1141     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1142   }
1143 
1144   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1145                                    const TargetRegisterClass &RC,
1146                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1147                                    unsigned SystemSGPRs) {
1148     // Skip parsing if it's not present.
1149     if (!A)
1150       return false;
1151 
1152     if (A->IsRegister) {
1153       Register Reg;
1154       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1155         SourceRange = A->RegisterName.SourceRange;
1156         return true;
1157       }
1158       if (!RC.contains(Reg))
1159         return diagnoseRegisterClass(A->RegisterName);
1160       Arg = ArgDescriptor::createRegister(Reg);
1161     } else
1162       Arg = ArgDescriptor::createStack(A->StackOffset);
1163     // Check and apply the optional mask.
1164     if (A->Mask)
1165       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1166 
1167     MFI->NumUserSGPRs += UserSGPRs;
1168     MFI->NumSystemSGPRs += SystemSGPRs;
1169     return false;
1170   };
1171 
1172   if (YamlMFI.ArgInfo &&
1173       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1174                              AMDGPU::SGPR_128RegClass,
1175                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1176        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1177                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1178                              2, 0) ||
1179        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1180                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1181        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1182                              AMDGPU::SReg_64RegClass,
1183                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1184        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1185                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1186                              2, 0) ||
1187        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1188                              AMDGPU::SReg_64RegClass,
1189                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1190        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1191                              AMDGPU::SGPR_32RegClass,
1192                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1193        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1194                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1195                              0, 1) ||
1196        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1197                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1198                              0, 1) ||
1199        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1200                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1201                              0, 1) ||
1202        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1203                              AMDGPU::SGPR_32RegClass,
1204                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1205        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1206                              AMDGPU::SGPR_32RegClass,
1207                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1208        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1209                              AMDGPU::SReg_64RegClass,
1210                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1211        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1212                              AMDGPU::SReg_64RegClass,
1213                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1214        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1215                              AMDGPU::VGPR_32RegClass,
1216                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1217        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1218                              AMDGPU::VGPR_32RegClass,
1219                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1220        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1221                              AMDGPU::VGPR_32RegClass,
1222                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1223     return true;
1224 
1225   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1226   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1227   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1228   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1229   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1230   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1231 
1232   return false;
1233 }
1234