1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #ifdef LLVM_BUILD_GLOBAL_ISEL
23 #include "AMDGPURegisterBankInfo.h"
24 #endif
25 #include "AMDGPUTargetObjectFile.h"
26 #include "AMDGPUTargetTransformInfo.h"
27 #include "GCNIterativeScheduler.h"
28 #include "GCNSchedStrategy.h"
29 #include "R600MachineScheduler.h"
30 #include "SIMachineScheduler.h"
31 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/TargetPassConfig.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Transforms/IPO.h"
39 #include "llvm/Transforms/IPO/AlwaysInliner.h"
40 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
41 #include "llvm/Transforms/Scalar.h"
42 #include "llvm/Transforms/Scalar/GVN.h"
43 #include "llvm/Transforms/Vectorize.h"
44 #include "llvm/IR/Attributes.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/IR/LegacyPassManager.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Target/TargetLoweringObjectFile.h"
51 #include <memory>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool> EnableR600IfConvert(
72   "r600-if-convert",
73   cl::desc("Use if conversion pass"),
74   cl::ReallyHidden,
75   cl::init(true));
76 
77 // Option to disable vectorizer for tests.
78 static cl::opt<bool> EnableLoadStoreVectorizer(
79   "amdgpu-load-store-vectorizer",
80   cl::desc("Enable load store vectorizer"),
81   cl::init(true),
82   cl::Hidden);
83 
84 // Option to to control global loads scalarization
85 static cl::opt<bool> ScalarizeGlobal(
86   "amdgpu-scalarize-global-loads",
87   cl::desc("Enable global load scalarization"),
88   cl::init(false),
89   cl::Hidden);
90 
91 // Option to run internalize pass.
92 static cl::opt<bool> InternalizeSymbols(
93   "amdgpu-internalize-symbols",
94   cl::desc("Enable elimination of non-kernel functions and unused globals"),
95   cl::init(false),
96   cl::Hidden);
97 
98 static cl::opt<bool> EnableSDWAPeephole(
99   "amdgpu-sdwa-peephole",
100   cl::desc("Enable SDWA peepholer"),
101   cl::init(false));
102 
103 // Enable address space based alias analysis
104 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
105   cl::desc("Enable AMDGPU Alias Analysis"),
106   cl::init(true));
107 
108 extern "C" void LLVMInitializeAMDGPUTarget() {
109   // Register the target
110   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
111   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
112 
113   PassRegistry *PR = PassRegistry::getPassRegistry();
114   initializeSILowerI1CopiesPass(*PR);
115   initializeSIFixSGPRCopiesPass(*PR);
116   initializeSIFixVGPRCopiesPass(*PR);
117   initializeSIFoldOperandsPass(*PR);
118   initializeSIPeepholeSDWAPass(*PR);
119   initializeSIShrinkInstructionsPass(*PR);
120   initializeSIFixControlFlowLiveIntervalsPass(*PR);
121   initializeSILoadStoreOptimizerPass(*PR);
122   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
123   initializeAMDGPUAnnotateUniformValuesPass(*PR);
124   initializeAMDGPULowerIntrinsicsPass(*PR);
125   initializeAMDGPUPromoteAllocaPass(*PR);
126   initializeAMDGPUCodeGenPreparePass(*PR);
127   initializeAMDGPUUnifyMetadataPass(*PR);
128   initializeSIAnnotateControlFlowPass(*PR);
129   initializeSIInsertWaitsPass(*PR);
130   initializeSIWholeQuadModePass(*PR);
131   initializeSILowerControlFlowPass(*PR);
132   initializeSIInsertSkipsPass(*PR);
133   initializeSIDebuggerInsertNopsPass(*PR);
134   initializeSIOptimizeExecMaskingPass(*PR);
135   initializeAMDGPUAAWrapperPassPass(*PR);
136 }
137 
138 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
139   return llvm::make_unique<AMDGPUTargetObjectFile>();
140 }
141 
142 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
143   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
144 }
145 
146 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
147   return new SIScheduleDAGMI(C);
148 }
149 
150 static ScheduleDAGInstrs *
151 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
152   ScheduleDAGMILive *DAG =
153     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
154   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
155   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
156   return DAG;
157 }
158 
159 static ScheduleDAGInstrs *
160 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
161   auto DAG = new GCNIterativeScheduler(C,
162     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
163   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
164   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
165   return DAG;
166 }
167 
168 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
169   return new GCNIterativeScheduler(C,
170     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
171 }
172 
173 static MachineSchedRegistry
174 R600SchedRegistry("r600", "Run R600's custom scheduler",
175                    createR600MachineScheduler);
176 
177 static MachineSchedRegistry
178 SISchedRegistry("si", "Run SI's custom scheduler",
179                 createSIMachineScheduler);
180 
181 static MachineSchedRegistry
182 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
183                              "Run GCN scheduler to maximize occupancy",
184                              createGCNMaxOccupancyMachineScheduler);
185 
186 static MachineSchedRegistry
187 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
188   "Run GCN scheduler to maximize occupancy (experimental)",
189   createIterativeGCNMaxOccupancyMachineScheduler);
190 
191 static MachineSchedRegistry
192 GCNMinRegSchedRegistry("gcn-minreg",
193   "Run GCN iterative scheduler for minimal register usage (experimental)",
194   createMinRegScheduler);
195 
196 static StringRef computeDataLayout(const Triple &TT) {
197   if (TT.getArch() == Triple::r600) {
198     // 32-bit pointers.
199     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
200             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
201   }
202 
203   // 32-bit private, local, and region pointers. 64-bit global, constant and
204   // flat.
205   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
206          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
207          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
208 }
209 
210 LLVM_READNONE
211 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
212   if (!GPU.empty())
213     return GPU;
214 
215   // HSA only supports CI+, so change the default GPU to a CI for HSA.
216   if (TT.getArch() == Triple::amdgcn)
217     return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
218 
219   return "r600";
220 }
221 
222 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
223   // The AMDGPU toolchain only supports generating shared objects, so we
224   // must always use PIC.
225   return Reloc::PIC_;
226 }
227 
228 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
229                                          StringRef CPU, StringRef FS,
230                                          TargetOptions Options,
231                                          Optional<Reloc::Model> RM,
232                                          CodeModel::Model CM,
233                                          CodeGenOpt::Level OptLevel)
234   : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
235                       FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
236     TLOF(createTLOF(getTargetTriple())) {
237   initAsmInfo();
238 }
239 
240 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
241 
242 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
243   Attribute GPUAttr = F.getFnAttribute("target-cpu");
244   return GPUAttr.hasAttribute(Attribute::None) ?
245     getTargetCPU() : GPUAttr.getValueAsString();
246 }
247 
248 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
249   Attribute FSAttr = F.getFnAttribute("target-features");
250 
251   return FSAttr.hasAttribute(Attribute::None) ?
252     getTargetFeatureString() :
253     FSAttr.getValueAsString();
254 }
255 
256 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
257   Builder.DivergentTarget = true;
258 
259   bool Internalize = InternalizeSymbols &&
260                      (getOptLevel() > CodeGenOpt::None) &&
261                      (getTargetTriple().getArch() == Triple::amdgcn);
262   Builder.addExtension(
263     PassManagerBuilder::EP_ModuleOptimizerEarly,
264     [Internalize](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
265       PM.add(createAMDGPUUnifyMetadataPass());
266       if (Internalize) {
267         PM.add(createInternalizePass([=](const GlobalValue &GV) -> bool {
268           if (const Function *F = dyn_cast<Function>(&GV)) {
269             if (F->isDeclaration())
270                 return true;
271             switch (F->getCallingConv()) {
272             default:
273               return false;
274             case CallingConv::AMDGPU_VS:
275             case CallingConv::AMDGPU_GS:
276             case CallingConv::AMDGPU_PS:
277             case CallingConv::AMDGPU_CS:
278             case CallingConv::AMDGPU_KERNEL:
279             case CallingConv::SPIR_KERNEL:
280               return true;
281             }
282           }
283           return !GV.use_empty();
284         }));
285         PM.add(createGlobalDCEPass());
286         PM.add(createAMDGPUAlwaysInlinePass());
287       }
288   });
289 }
290 
291 //===----------------------------------------------------------------------===//
292 // R600 Target Machine (R600 -> Cayman)
293 //===----------------------------------------------------------------------===//
294 
295 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
296                                      StringRef CPU, StringRef FS,
297                                      TargetOptions Options,
298                                      Optional<Reloc::Model> RM,
299                                      CodeModel::Model CM, CodeGenOpt::Level OL)
300   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
301   setRequiresStructuredCFG(true);
302 }
303 
304 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
305   const Function &F) const {
306   StringRef GPU = getGPUName(F);
307   StringRef FS = getFeatureString(F);
308 
309   SmallString<128> SubtargetKey(GPU);
310   SubtargetKey.append(FS);
311 
312   auto &I = SubtargetMap[SubtargetKey];
313   if (!I) {
314     // This needs to be done before we create a new subtarget since any
315     // creation will depend on the TM and the code generation flags on the
316     // function that reside in TargetOptions.
317     resetTargetOptions(F);
318     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
319   }
320 
321   return I.get();
322 }
323 
324 //===----------------------------------------------------------------------===//
325 // GCN Target Machine (SI+)
326 //===----------------------------------------------------------------------===//
327 
328 #ifdef LLVM_BUILD_GLOBAL_ISEL
329 namespace {
330 
331 struct SIGISelActualAccessor : public GISelAccessor {
332   std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
333   std::unique_ptr<InstructionSelector> InstSelector;
334   std::unique_ptr<LegalizerInfo> Legalizer;
335   std::unique_ptr<RegisterBankInfo> RegBankInfo;
336   const AMDGPUCallLowering *getCallLowering() const override {
337     return CallLoweringInfo.get();
338   }
339   const InstructionSelector *getInstructionSelector() const override {
340     return InstSelector.get();
341   }
342   const LegalizerInfo *getLegalizerInfo() const override {
343     return Legalizer.get();
344   }
345   const RegisterBankInfo *getRegBankInfo() const override {
346     return RegBankInfo.get();
347   }
348 };
349 
350 } // end anonymous namespace
351 #endif
352 
353 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
354                                    StringRef CPU, StringRef FS,
355                                    TargetOptions Options,
356                                    Optional<Reloc::Model> RM,
357                                    CodeModel::Model CM, CodeGenOpt::Level OL)
358   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
359 
360 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
361   StringRef GPU = getGPUName(F);
362   StringRef FS = getFeatureString(F);
363 
364   SmallString<128> SubtargetKey(GPU);
365   SubtargetKey.append(FS);
366 
367   auto &I = SubtargetMap[SubtargetKey];
368   if (!I) {
369     // This needs to be done before we create a new subtarget since any
370     // creation will depend on the TM and the code generation flags on the
371     // function that reside in TargetOptions.
372     resetTargetOptions(F);
373     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
374 
375 #ifndef LLVM_BUILD_GLOBAL_ISEL
376     GISelAccessor *GISel = new GISelAccessor();
377 #else
378     SIGISelActualAccessor *GISel = new SIGISelActualAccessor();
379     GISel->CallLoweringInfo.reset(
380       new AMDGPUCallLowering(*I->getTargetLowering()));
381     GISel->Legalizer.reset(new AMDGPULegalizerInfo());
382 
383     GISel->RegBankInfo.reset(new AMDGPURegisterBankInfo(*I->getRegisterInfo()));
384     GISel->InstSelector.reset(new AMDGPUInstructionSelector(*I,
385 				*static_cast<AMDGPURegisterBankInfo*>(GISel->RegBankInfo.get())));
386 #endif
387 
388     I->setGISelAccessor(*GISel);
389   }
390 
391   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
392 
393   return I.get();
394 }
395 
396 //===----------------------------------------------------------------------===//
397 // AMDGPU Pass Setup
398 //===----------------------------------------------------------------------===//
399 
400 namespace {
401 
402 class AMDGPUPassConfig : public TargetPassConfig {
403 public:
404   AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
405     : TargetPassConfig(TM, PM) {
406     // Exceptions and StackMaps are not supported, so these passes will never do
407     // anything.
408     disablePass(&StackMapLivenessID);
409     disablePass(&FuncletLayoutID);
410   }
411 
412   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
413     return getTM<AMDGPUTargetMachine>();
414   }
415 
416   ScheduleDAGInstrs *
417   createMachineScheduler(MachineSchedContext *C) const override {
418     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
419     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
420     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
421     return DAG;
422   }
423 
424   void addEarlyCSEOrGVNPass();
425   void addStraightLineScalarOptimizationPasses();
426   void addIRPasses() override;
427   void addCodeGenPrepare() override;
428   bool addPreISel() override;
429   bool addInstSelector() override;
430   bool addGCPasses() override;
431 };
432 
433 class R600PassConfig final : public AMDGPUPassConfig {
434 public:
435   R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
436     : AMDGPUPassConfig(TM, PM) {}
437 
438   ScheduleDAGInstrs *createMachineScheduler(
439     MachineSchedContext *C) const override {
440     return createR600MachineScheduler(C);
441   }
442 
443   bool addPreISel() override;
444   void addPreRegAlloc() override;
445   void addPreSched2() override;
446   void addPreEmitPass() override;
447 };
448 
449 class GCNPassConfig final : public AMDGPUPassConfig {
450 public:
451   GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
452     : AMDGPUPassConfig(TM, PM) {}
453 
454   GCNTargetMachine &getGCNTargetMachine() const {
455     return getTM<GCNTargetMachine>();
456   }
457 
458   ScheduleDAGInstrs *
459   createMachineScheduler(MachineSchedContext *C) const override;
460 
461   bool addPreISel() override;
462   void addMachineSSAOptimization() override;
463   bool addILPOpts() override;
464   bool addInstSelector() override;
465 #ifdef LLVM_BUILD_GLOBAL_ISEL
466   bool addIRTranslator() override;
467   bool addLegalizeMachineIR() override;
468   bool addRegBankSelect() override;
469   bool addGlobalInstructionSelect() override;
470 #endif
471   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
472   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
473   void addPreRegAlloc() override;
474   void addPostRegAlloc() override;
475   void addPreSched2() override;
476   void addPreEmitPass() override;
477 };
478 
479 } // end anonymous namespace
480 
481 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
482   return TargetIRAnalysis([this](const Function &F) {
483     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
484   });
485 }
486 
487 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
488   if (getOptLevel() == CodeGenOpt::Aggressive)
489     addPass(createGVNPass());
490   else
491     addPass(createEarlyCSEPass());
492 }
493 
494 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
495   addPass(createSeparateConstOffsetFromGEPPass());
496   addPass(createSpeculativeExecutionPass());
497   // ReassociateGEPs exposes more opportunites for SLSR. See
498   // the example in reassociate-geps-and-slsr.ll.
499   addPass(createStraightLineStrengthReducePass());
500   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
501   // EarlyCSE can reuse.
502   addEarlyCSEOrGVNPass();
503   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
504   addPass(createNaryReassociatePass());
505   // NaryReassociate on GEPs creates redundant common expressions, so run
506   // EarlyCSE after it.
507   addPass(createEarlyCSEPass());
508 }
509 
510 void AMDGPUPassConfig::addIRPasses() {
511   // There is no reason to run these.
512   disablePass(&StackMapLivenessID);
513   disablePass(&FuncletLayoutID);
514   disablePass(&PatchableFunctionID);
515 
516   addPass(createAMDGPULowerIntrinsicsPass());
517 
518   // Function calls are not supported, so make sure we inline everything.
519   addPass(createAMDGPUAlwaysInlinePass());
520   addPass(createAlwaysInlinerLegacyPass());
521   // We need to add the barrier noop pass, otherwise adding the function
522   // inlining pass will cause all of the PassConfigs passes to be run
523   // one function at a time, which means if we have a nodule with two
524   // functions, then we will generate code for the first function
525   // without ever running any passes on the second.
526   addPass(createBarrierNoopPass());
527 
528   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
529 
530   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
531     // TODO: May want to move later or split into an early and late one.
532 
533     addPass(createAMDGPUCodeGenPreparePass(
534               static_cast<const GCNTargetMachine *>(&TM)));
535   }
536 
537   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
538   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
539 
540   if (TM.getOptLevel() > CodeGenOpt::None) {
541     addPass(createInferAddressSpacesPass());
542     addPass(createAMDGPUPromoteAlloca(&TM));
543 
544     if (EnableSROA)
545       addPass(createSROAPass());
546 
547     addStraightLineScalarOptimizationPasses();
548 
549     if (EnableAMDGPUAliasAnalysis) {
550       addPass(createAMDGPUAAWrapperPass());
551       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
552                                              AAResults &AAR) {
553         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
554           AAR.addAAResult(WrapperPass->getResult());
555         }));
556     }
557   }
558 
559   TargetPassConfig::addIRPasses();
560 
561   // EarlyCSE is not always strong enough to clean up what LSR produces. For
562   // example, GVN can combine
563   //
564   //   %0 = add %a, %b
565   //   %1 = add %b, %a
566   //
567   // and
568   //
569   //   %0 = shl nsw %a, 2
570   //   %1 = shl %a, 2
571   //
572   // but EarlyCSE can do neither of them.
573   if (getOptLevel() != CodeGenOpt::None)
574     addEarlyCSEOrGVNPass();
575 }
576 
577 void AMDGPUPassConfig::addCodeGenPrepare() {
578   TargetPassConfig::addCodeGenPrepare();
579 
580   if (EnableLoadStoreVectorizer)
581     addPass(createLoadStoreVectorizerPass());
582 }
583 
584 bool AMDGPUPassConfig::addPreISel() {
585   addPass(createFlattenCFGPass());
586   return false;
587 }
588 
589 bool AMDGPUPassConfig::addInstSelector() {
590   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));
591   return false;
592 }
593 
594 bool AMDGPUPassConfig::addGCPasses() {
595   // Do nothing. GC is not supported.
596   return false;
597 }
598 
599 //===----------------------------------------------------------------------===//
600 // R600 Pass Setup
601 //===----------------------------------------------------------------------===//
602 
603 bool R600PassConfig::addPreISel() {
604   AMDGPUPassConfig::addPreISel();
605 
606   if (EnableR600StructurizeCFG)
607     addPass(createStructurizeCFGPass());
608   return false;
609 }
610 
611 void R600PassConfig::addPreRegAlloc() {
612   addPass(createR600VectorRegMerger(*TM));
613 }
614 
615 void R600PassConfig::addPreSched2() {
616   addPass(createR600EmitClauseMarkers(), false);
617   if (EnableR600IfConvert)
618     addPass(&IfConverterID, false);
619   addPass(createR600ClauseMergePass(*TM), false);
620 }
621 
622 void R600PassConfig::addPreEmitPass() {
623   addPass(createAMDGPUCFGStructurizerPass(), false);
624   addPass(createR600ExpandSpecialInstrsPass(*TM), false);
625   addPass(&FinalizeMachineBundlesID, false);
626   addPass(createR600Packetizer(*TM), false);
627   addPass(createR600ControlFlowFinalizer(*TM), false);
628 }
629 
630 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
631   return new R600PassConfig(this, PM);
632 }
633 
634 //===----------------------------------------------------------------------===//
635 // GCN Pass Setup
636 //===----------------------------------------------------------------------===//
637 
638 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
639   MachineSchedContext *C) const {
640   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
641   if (ST.enableSIScheduler())
642     return createSIMachineScheduler(C);
643   return createGCNMaxOccupancyMachineScheduler(C);
644 }
645 
646 bool GCNPassConfig::addPreISel() {
647   AMDGPUPassConfig::addPreISel();
648 
649   // FIXME: We need to run a pass to propagate the attributes when calls are
650   // supported.
651   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
652   addPass(createAMDGPUAnnotateKernelFeaturesPass(&TM));
653   addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
654   addPass(createSinkingPass());
655   addPass(createSITypeRewriter());
656   addPass(createAMDGPUAnnotateUniformValues());
657   addPass(createSIAnnotateControlFlowPass());
658 
659   return false;
660 }
661 
662 void GCNPassConfig::addMachineSSAOptimization() {
663   TargetPassConfig::addMachineSSAOptimization();
664 
665   // We want to fold operands after PeepholeOptimizer has run (or as part of
666   // it), because it will eliminate extra copies making it easier to fold the
667   // real source operand. We want to eliminate dead instructions after, so that
668   // we see fewer uses of the copies. We then need to clean up the dead
669   // instructions leftover after the operands are folded as well.
670   //
671   // XXX - Can we get away without running DeadMachineInstructionElim again?
672   addPass(&SIFoldOperandsID);
673   addPass(&DeadMachineInstructionElimID);
674   addPass(&SILoadStoreOptimizerID);
675 }
676 
677 bool GCNPassConfig::addILPOpts() {
678   if (EnableEarlyIfConversion)
679     addPass(&EarlyIfConverterID);
680 
681   TargetPassConfig::addILPOpts();
682   return false;
683 }
684 
685 bool GCNPassConfig::addInstSelector() {
686   AMDGPUPassConfig::addInstSelector();
687   addPass(createSILowerI1CopiesPass());
688   addPass(&SIFixSGPRCopiesID);
689   return false;
690 }
691 
692 #ifdef LLVM_BUILD_GLOBAL_ISEL
693 bool GCNPassConfig::addIRTranslator() {
694   addPass(new IRTranslator());
695   return false;
696 }
697 
698 bool GCNPassConfig::addLegalizeMachineIR() {
699   addPass(new Legalizer());
700   return false;
701 }
702 
703 bool GCNPassConfig::addRegBankSelect() {
704   addPass(new RegBankSelect());
705   return false;
706 }
707 
708 bool GCNPassConfig::addGlobalInstructionSelect() {
709   addPass(new InstructionSelect());
710   return false;
711 }
712 
713 #endif
714 
715 void GCNPassConfig::addPreRegAlloc() {
716   addPass(createSIShrinkInstructionsPass());
717   if (EnableSDWAPeephole) {
718     addPass(&SIPeepholeSDWAID);
719     addPass(&DeadMachineInstructionElimID);
720   }
721   addPass(createSIWholeQuadModePass());
722 }
723 
724 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
725   // FIXME: We have to disable the verifier here because of PHIElimination +
726   // TwoAddressInstructions disabling it.
727 
728   // This must be run immediately after phi elimination and before
729   // TwoAddressInstructions, otherwise the processing of the tied operand of
730   // SI_ELSE will introduce a copy of the tied operand source after the else.
731   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
732 
733   TargetPassConfig::addFastRegAlloc(RegAllocPass);
734 }
735 
736 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
737   // This needs to be run directly before register allocation because earlier
738   // passes might recompute live intervals.
739   insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
740 
741   // This must be run immediately after phi elimination and before
742   // TwoAddressInstructions, otherwise the processing of the tied operand of
743   // SI_ELSE will introduce a copy of the tied operand source after the else.
744   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
745 
746   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
747 }
748 
749 void GCNPassConfig::addPostRegAlloc() {
750   addPass(&SIFixVGPRCopiesID);
751   addPass(&SIOptimizeExecMaskingID);
752   TargetPassConfig::addPostRegAlloc();
753 }
754 
755 void GCNPassConfig::addPreSched2() {
756 }
757 
758 void GCNPassConfig::addPreEmitPass() {
759   // The hazard recognizer that runs as part of the post-ra scheduler does not
760   // guarantee to be able handle all hazards correctly. This is because if there
761   // are multiple scheduling regions in a basic block, the regions are scheduled
762   // bottom up, so when we begin to schedule a region we don't know what
763   // instructions were emitted directly before it.
764   //
765   // Here we add a stand-alone hazard recognizer pass which can handle all
766   // cases.
767   addPass(&PostRAHazardRecognizerID);
768 
769   addPass(createSIInsertWaitsPass());
770   addPass(createSIShrinkInstructionsPass());
771   addPass(&SIInsertSkipsPassID);
772   addPass(createSIDebuggerInsertNopsPass());
773   addPass(&BranchRelaxationPassID);
774 }
775 
776 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
777   return new GCNPassConfig(this, PM);
778 }
779